Abstract: A data processing apparatus and method for a flash memory, which make it easy to determine whether data stored in the flash memory is valid, are provided. The data processing apparatus includes a user request unit which issues a request for performing a data operation on a flash memory using a predetermined logical address, a conversion unit which converts the logical address into a physical address, and a control unit which performs the data operation on the physical address and writes inverted data obtained by inverting error correction code (ECC) corresponding to data used in the data operation to a region indicating whether the ECC is erroneous.

Abstract: A method adapted to detect the activity of individual partitions within a packetized frame. The method provides for the encoding of those portions of the data stream having higher activity more than those portions having less activity. This enables a protection differentiation depending on the importance of the data within the specific portion of the stream.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors.

Abstract: A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: A technique wherein High Availability (HA) hardware is used to automatically validate control and configuration registers, e.g. automatically generate parity, detect parity errors, and report errors within software-written configuration and control registers of ASIC and IC products. Parity control logic and Masking Registers are utilized to facilitate automatic parity generation and subsequent parity error reporting. The specific location of where the error occurred can be stored to enable software to correct and/or reconfigure the registers. The HA hardware verifies the validity of control and configuration registers coupled to a bus, utilizing idle cycles in addition to valid bus cycles so there is no impact on system throughput.

Abstract: Embodiments of the invention provide methods and systems for improving the reliability of data stored on disk media. Logical redundancy is introduced into the data, and the data within a logical storage unit is divided into sectors that are spatially separated by interleaving them with sectors of other logical storage units. The logical redundancy and spatial separation reduce or minimize the effects of localized damage to the storage disk, such as the damage caused by a scratch or fingerprint. Thus, the data is stored on the disk in a layout that improves the likelihood that the data can be recovered despite the presence of an error that prevents one sector from being read correctly.

Abstract: Provided are a method, system, and an article of manufacture for detecting errors while accessing a storage device. A host system writes an identical initialization pattern into each block of a plurality of blocks while formatting the storage device. Each block of the plurality of blocks has a checksum field capable of containing a value. Any host system generates an error when data from a retrieved block from the plurality of blocks computes to a checksum that is different from the value contained within the checksum field for the retrieved block, and the retrieved block does not contain the initialization pattern.

Abstract: The present invention relates to a method and a corresponding device for managing defective storage units on a record carrier, in particular on a rewritable optical record carrier. To avoid synchronization errors of a drive when accessing storage units located before or after a defective storage unit, it is proposed according to the present invention not only to map the actual defective storage unit (U1) but also one or more storage units (U2-U5) located before and/or after the defective storage unit (U1) as defective.

Abstract: A circuit for transmitting a block of data is disclosed. The circuit comprises a memory array having a plurality of memory locations coupled to receive data; a first data source coupled to the memory array, wherein data from the first data source is stored at sequential addressable memory locations of the plurality of memory locations on a first in, first out basis; a second data source coupled to the memory array, the second data source providing data to be stored in a predetermined memory location of the sequential addressable memory locations storing data from the second data source; and a selection circuit coupled to the first data source and the second data source for selecting data to be stored in the plurality of memory locations.

Abstract: A method and apparatus for decoding inner and/or outer codes in a mobile communication system. The inner and/or outer codes are decoded at low power and high speed. An inner decoder performs channel decoding and cyclic redundancy checking (CRC) on symbols received through a wireless network. An outer decoder performs outer coding on the received symbols. An erasure symbol identifier outputs information of erasure symbols in which a reception error has occurred. The reception error is determined from a result of the CRC on the received symbols. A controller counts the number of received symbols and the number of erasure symbols, and stops an operation of at least one of the inner and outer decoders when at least one of the number of received symbols and the number of erasure symbols is equal to a preset reference value.

Abstract: A method for operating a volatile random access memory as a detector, with predetermined information being stored in at least one area of the volatile random access memory. The method includes interrupting a supply voltage for the at least one area of the random access memory during a time period, reading information from the at least one area of the random access memory, and checking the extent to which the predetermined information and the information that has been read match or whether the predetermined information and the information which has been read have a predetermined relationship.

Abstract: The error tolerance of an array of m storage units is increased by using a technique referred to as “dodging.” A plurality of k stripes are stored across the array of storage units in which each stripe has n+r elements that correspond to a symmetric code having a minimum Hamming distance d=r+1. Each respective element of a stripe is stored on a different storage unit. An element is selected when a difference between a minimum distance of the donor stripe and a minimum distance of a recipient stripe is greater or equal to 2. The selected element is also stored on a storage unit having no elements of the recipient stripe. A lost element of the recipient stripe is then rebuilt on the selected element.

Abstract: Data are stored on a random-access storage medium. A user set of data is received. The user set of data is mapped to multiple frames. For each frame, error-correction bytes are generated over the data mapped to that frame. In addition, the data mapped to that frame are written to a number of data blocks of that frame and the error-correction bytes generated for that frame are written to a number of error-correction blocks of that frame. At least one of the number of error-correction blocks and the number of data blocks differs among at least some of the frames.

Abstract: Data latches, multiplexers, an ECC circuit section, and an input/output circuit section are arranged in columns and adjacent to each other, in an extending direction of data lines that are formed in a direction orthogonal to word lines. A layout of a data path system is formed in bit slices. Further, parity bits are equally distributed so as to cause delay times of bits to be uniform.

Abstract: A system and method for organizing a non-volatile memory is provided. The system includes a non-volatile memory with a first data region and a first redundant memory area associated with the first data region. The first redundant memory area includes a first portion associated with a first data sector. The first portion of the redundant memory area includes a relative sector index and a block number. The redundant memory area also includes a second portion including error correction code (ECC) data.

Abstract: Systems and methods for providing access to shared storage, for example, using multiple information handling system nodes configured as server nodes. Each server node is given ownership of different portions of data on the shared storage so that each portion of data is allowed to have only one owner at any given time. Data ownership information may be globally stored and used by the multiple server nodes to determine ownership and control access to a requested portion of data.

Abstract: A memory circuit includes a data storage section for storing a plurality of data sets and a plurality of redundant data sets, which are used for error correction for the data sets; and an error correction section for performing at least error detection for the data sets in the data storage section by using the redundant data sets when the memory circuit is not accessed from outside for data input or output, and outputting at least result of the error detection as an error detection signal. When the memory circuit is accessed so as to output a designated one of the stored data sets, the designated data set is outputted without being subjected to the error detection by the error correction section.

Abstract: A system for detecting write errors in a storage device is disclosed. The system includes a storage device having means for storing one or more data blocks in a storage group. The storage group includes one or more data blocks and a check block having one of the group of: a combination of the one or more data blocks of the storage group, a combination of one or more bits of a logical block address associated with the storage group, and a combination of one or more bits of a phase field that is updated each time the storage group is written. The system also includes means for updating the check block each time the storage group is written, and means for detecting write errors by checking the check block when a storage group is read.

Abstract: A method is disclosed to transfer information from a first information storage and retrieval system to a second information storage and retrieval system. The method provides a first information storage and retrieval system comprising a first track size and a plurality of first tracks, and a second information storage and retrieval system comprising a second track size and a plurality of second tracks. The method determines if the first track size is greater than the second track size. If the method determines that the first track size is greater than said second track size, then the method sets a ratio (R) equal to the first track size divided by the second track size, provides the (i)th first track from the first information storage and retrieval system to the second information storage and retrieval system, provides (R) second tracks, and maps the (i)th first track onto the (R) second tracks.

Abstract: A semiconductor memory device comprising: a memory array having a data area and a check code area; refresh control means which controls a refresh operation in a data holding state; operation means which executes an encoding operation for generating the check code using a bit string in the data area, and executes a decoding operation for performing the error detection/correction of the data using the check code; encode control means for controlling an encode process in which in a change to the data holding state, a first and second code are written in the check code area; and decode control means for controlling a decode process in which at the end of the data holding state, first and second bit error correction based on each code are alternately performed, and the first and the second bit error correction are performed at least twice respectively.

Abstract: A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can be accessed without incurring an additional RAS access penalty. Each group is logically split into a plurality of segments for storing data with at least one segment for storing ECC for the data segments. For a write operation, data are written in a data segment and then ECC for the data are written in an ECC segment. For a read operation, ECC are read from an ECC segment, then data are read from the data segment.

Abstract: A data transfer apparatus improving data transfer rate regardless of the original transfer mode in a USB interface is disclosed. A computer includes a bulk packet generation unit and an isochronous packet transmission unit. The bulk packet generation unit generates a bulk packet (or a control packet) which is a USB packet and has a predetermined structure including a first data area by describing data which is taken as an object of transfer in the first data area. The isochronous packet transmission unit generates an isochronous packet which is a packet in USB isochronous transfer and has a predetermined structure including a second data area by incorporating at least one bulk packet into the second data area, and isochronously transfers the isochronous packet to the mobile telephone over the USB interface.

Abstract: Memory space of a digital device may be configured for both instructions/data (op-code) and ECC or parity when required, otherwise the entire memory space may be configured for just the program instructions/data. A standard word width memory may be configured for ECC or non-ECC functionality, or parity or non-parity functionality, based upon a desired application. The last portion of the memory may be allocated for ECC or parity data rather then application code when an ECC or parity implementation is required. When an ECC or parity implementation is not required, the entire memory may be used for the application code. This allows a digital device and memory to be used in applications having different robustness (e.g., application code integrity) requirements without have to fabricate different digital devices.

Abstract: A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.

Abstract: Segregation of redundant control bits in an ECC permuted, systematic modulation code. Appropriately encoding of user information via combined modulation and RS (Reed-Solomon) encoding ensures segregation of scrambled user information, modulation redundancy bits, and RS redundancy bits in such a way that each of the components thereof can be segregated and stored within any desirable digital information memory storage device. By providing this segregated capability, when accessing a portion of a RS codeword from the memory, an entire RS codeword need not be read from the memory. In fact, only the particular field (or bits) needs to be accessed to perform correction thereon. This segregation provides for a reduction in the hardware complexity of translation between user information and a modulation codeword. Also, this segregation provides for the ability to perform correction of only one of the scrambled user information, the modulation redundancy bits, or the RS redundancy bits.

Abstract: A data transmitting method, a data recording apparatus, a data record medium and a data reproducing apparatus are provided to disallow the encryption to be easily decoded and keep the secrecy of key information higher. The data transmitting apparatus includes an error correction coding process block. In the block, an input converting circuit operates to perform a logic operation with respect to the information data from an interface circuit 12 according to the key data. The converted information data is sent to an encoder 15 for generating parity data. This parity data is mixed with information data before conversion in a mixing circuit. The error correction coding block operates to send the resulting data to a modulating circuit 17 for modulating the data. The modulated data is recorded on a disk record medium.

Abstract: A method, system, and machine-readable medium for controlling access to data of a tape data storage medium are disclosed. In accordance with one embodiment, a method is provided which comprises conveying data access control metadata from a tape cartridge comprising a tape data storage medium to a host, receiving decrypted metadata from the host, comparing a checksum value determined utilizing the decrypted metadata with checksum data stored within the tape cartridge; and processing a request to access the tape data storage medium received from the host based upon a comparison of the checksum value and checksum data. In the described method embodiment, the data access control metadata comprises encrypted metadata corresponding to a data storage parameter, where data is stored within the tape data storage medium utilizing the data storage parameter and the decrypted metadata is generated by the host utilizing the encrypted metadata.

Abstract: A system for detecting write errors in a storage device is disclosed. The system comprises a storage device; within the storage device, means for storing one or more data blocks in a storage group, the storage group comprising the one or more data blocks and a check block, wherein the check block comprises one of the group of: a combination of the one or more data blocks of the storage group, a combination of one or more bits of a logical block address associated with the storage group, and a combination of one or more bits of a phase field that is updated each time the storage group is written; means for updating the check block each time the storage group is written; and means for detecting write errors by checking the check block.

Abstract: A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to an address. A test write control circuit operates in the test mode, and thus writes test data into a regular memory cell at a location corresponding to a location of a parity memory cell into which test parity data are written in each of regular cell arrays. Therefore, since a common test pattern can be used to test both the regular memory cell and the parity memory cell, test cost can be curtailed.

Abstract: In one embodiment, a memory device comprises a first partition to divide the memory device into a first segment to hold a first data block and a second segment to hold a second data block, and a codeword in a single internal word of the memory device.

Abstract: In an iterative error correction method and apparatus for correcting errors in digital data read from a storage medium, re-reads are combined with the error correction procedure in a single error recovery procedure. The data read from the storage medium are represented as a multi-dimensional data structure, and the error recovery procedure is undertaken for each dimension of the data structure. In each dimension, an erasure map is generated that contains errors in the initial read of the data for that dimension, and the errors in the erasure map are deducted as they are corrected in subsequent re-reads. After a predetermined number of re-reads, or when no further errors exist, the error recovery procedure is ended.

Abstract: A multi-level cell memory that includes storing data in multiple cell densities is disclosed. The multi-level cell memory selectively includes error correction code. The multi-level cell memory may also include splitting cells into higher bits and lower bits in codewords.

Abstract: A more convenient checksum writing method and checksum checking apparatus. The method includes: calculating a first checksum by reading values from the memory and summing the read values; calculating a first mode checksum by subtracting values written in a predetermined area of the memory from the first checksum; initializing a second checksum to be zero if the first mode checksum does not meet a predetermined condition; calculating a second mode checksum by inverting the second checksum and adding the inverted second checksum to the first mode checksum; and writing the inverted second checksum value in the predetermined area of the memory, if the second mode checksum is equal to the second checksum.

Abstract: A parity assignment technique enables parity declustering in a large, balanced parity (“super-stripe”) array of a storage system. The balanced array may be constructed by combining a plurality of unbalanced parity stripe arrays, each having parity blocks on a set of storage devices, such as disks, that are disjoint from the set of disks storing the data blocks. The technique distributes the assignment of disks to parity groups among the combined super-stripe array such that all disks contain the same amount of data or parity information. Moreover, the technique ensures that all surviving data disks of the array are loaded uniformly during a reconstruction phase after a single or double disk failure.

Abstract: A method and apparatus are provided for storing data. The method and apparatus generate a plurality of ECC codewords, which define a cooperative block. Each ECC codeword includes a plurality of information symbols and first and second sets of corresponding redundancy symbols. Shared redundancy symbols are generated for the cooperative block based on a combination of the second sets of redundancy symbols from the plurality of ECC codewords. A respective set of parity codewords is generated for the cooperative block based on the shared redundancy symbols. The second set of redundancy symbols for each ECC codeword in the cooperative block is derivable from the parity codewords. The cooperative block and the respective parity codewords are stored, without the second set of redundancy symbols, on a storage medium.

Abstract: A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of a pair of BLs for parity bits, a third memory cell coupled to a second WL and the other of the pair of BLs for information bits, a fourth memory cell coupled to the second WL and the other of the pair of BLs for parity bits, column switches which connect the pair of complementary BLs for parity bits to a pair of data lines for parity bits, and a logic correction circuit connected to one of the pair of data lines for parity bits. The logic correction circuit executes a parity bit rewrite operation.

Abstract: There is disclosed systems and methods for testing a memory where at least one bit field at certain address locations cannot be directly accessed. In one embodiment, random bits are populated into a data field at one of the certain address locations, and at least some of the random data bits that are copied into non-directly accessible data field. The bits which were copied from the data field are replaced with bits resulting from X/ORing the copied data bits with bits read from the non-directly accessible field, and all the data field bits as the address locations are checked for mismatched data bits.

Abstract: Systems, method, and computer program products for utilizing a spare lane for additional checkbits. Systems include computer, storage or communications systems with bitlanes for transferring error correcting code (ECC) words in packets over a bus in multiple cycles, a spare bitlane available to the bus, a spared mode and an initial mode. The spared mode is executed when the spare bitlane has been deployed as a replacement bitlane for carrying data for one of the other bitlanes. The initial mode is executed when the spare bitlane has not been deployed as a replacement bitlane. The initial mode includes utilizing the spare bitlane for carrying one or more additional ECC checkbits. The initial mode provides at least one of a more robust error detecting function for the bus than the spared mode and a more robust error correcting function for the bus than the spared mode.

Abstract: The present invention is directed to a method and system for disk drive data recovery utilizing CRC information and RAID parity. CRC meta data is compared with either the CRC generated from the data read from the disk drive or the CRC generated from the data reconstructed from the parity drive. If the CRC metadata matches the CRC generated from the data read from the disk drive, the data from the disk drive is accepted as valid. Otherwise, another comparison is made between the CRC generated from data reconstructed from RAID parity and the CRC metadata. If there is a match, the reconstructed data is used as the valid data; otherwise, the data read from the disk drive is used as valid data.

Abstract: A flash memory system, including a flash memory device and a controller, and having improved efficiency error correction coding (ECC), is disclosed. Each page in the flash memory device has the capacity to store multiple sectors' worth of data. However, partial page programming (i.e., followed by a later write to fill the page) is prohibited for reliability reasons. A scratchpad block within the flash memory device is designed, and stores both user data and control data. ECC efficiency is improved by encoding the ECC, or parity, bits over the entire data block corresponding to the user and control data in the page. Retrieval of a particular sector of data requires reading and decoding of the entire page. Especially for codes such as Reed-Solomon and BCH codes, the larger data block including multiple sectors' data improves the error correction capability, and thus enables either fewer redundant memory cells in each page or improved error correction.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: A nonvolatile ferroelectric memory device including a failed cell correcting circuit which effectively processes randomly distributed cell data. The nonvolatile ferroelectric memory device checks horizontal parity of a main memory cell array and stores the parity in a horizontal parity check cell array, and checks vertical parity of a main memory cell array and stores the parity in the vertical parity check cell array. Then, code data stored in the horizontal parity check cell array and the vertical parity check cell array are compared to sensing data of the main memory cell to correct an error datum. As a result, a 1 bit failure randomly generated within a predetermined column is corrected.

Abstract: One embodiment of the disclosures made herein is an apparatus adapted to facilitate error detection for Content Addressable Memory (CAM) modules. The apparatus includes an input error detection module and an output error detection module. The input error detection module includes a parity word generator that generates a key-based parity word after receiving a key. The key-based parity word and the key jointly define a comparand that is provided to the CAM module. The output error detection module includes a protection word generator that generates a key-based protection word after receiving the key and memory. The output error detection module includes a comparator connected to the protection word generator and to the memory. The comparator enables the predetermined protection word to be compared with the key-based protection word for facilitating issuance of an output error indication when the predetermined protection word is different than the key-based protection word.

Abstract: An apparatus and method for accessing data from a storage medium is disclosed. The apparatus fetches a data block from the storage medium via an accessing unit, and corrects an error of the data block by an error correction code (ECC) decoder according to an ECC of the data block. The apparatus also includes an error detection code (EDC) processor for calculating an EDC of each data sector of the data block, and a flag register for storing a flag associated with each data sector. The method includes re-fetching a data sector if the associated flag indicates the EDC of the data sector is incorrect; and bypassing a data sector if the associated flag indicates that the EDC of the data sector is correct, even though the ECC of the data block indicates that the data sector contains an error.

Abstract: A method of and apparatus for handling errors occurring in data stored in memory is presented. Data to be stored in a buffer memory is applied to a generator matrix to generate parity check bits. The parity check bits are stored in the buffer memory along with the data. The stored data and parity check bits are read and the read data is used to regenerate the parity check bits. A result produced from the stored and regenerated parity check bits is usable to directly identify a location of an erroneous bit of the data in the buffer memory.

Abstract: A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error correcting circuit comprising an encoder (107). A first address register (104) is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register (105) is connected to the input data bus of the circuit (108) for storing data transmitted to the encoder (107). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.

Abstract: A converting circuit, for preventing wrong error correction code from occurring due to an error correction rule during data reading operation is provided. When the flash memory controller writes all 0xFF data into the flash memory, the byte error correction rule generates a set of correct error correction codes and the error correction code converting circuit converts the set of correct error correction codes into 0xFF error correction codes, and values stored in the data area and error correction code area of the flash memory are converted into 0xFF to prevent wrong error correction code from occurring during data reading operation when the error correction codes are not completely 0xFF.

Abstract: A method for hardening an extensible firmware framework and system in which the framework is implemented. In accordance with the method, a resource access policy that defines rules to allow or disallow access to designated system resources, such as memory and I/O, is defined. During execution of firmware-based event handlers, event handler code may seek to access a designated system resource. In response thereto, access to the system resource may be determined based on a security status of a firmware-based event handler in consideration of any applicable rules defined by the resource access policy. For example, a resource access policy may allow only secure event handlers to access selected portions of memory, while preventing non-secure event handlers from accessing the same. In this manner, errant and malicious event handlers are prevented from damaging critical resources.

Abstract: A method of storing data in a memory device is disclosed. The method comprises dividing data to be stored in a memory device into one or more data segments; storing the one or more data segments in the memory device; for a particular data segment among the one or more data segments, creating an error detection code; storing the error detection code in the memory device; for the particular data segment, determining an error correction segment that is a logical combination of the particular data segment with a second data segment, wherein the error correction can be used to reconstruct the particular data segment; and storing the error correction segment in the memory device.