Abstract: Methods, systems, and devices for memory operations are described. A read command may be received at a memory device from a host device. As part of an error control operation, a first set of error control bits may be generated for the set of data. Based on the first set of error control bits, a failure of a matching operation associated with the error control operation may be determined. Based on determining the failure of the matching operation, a second set of error control bits that is different than the first set of error control bits may be transmitted to the host device. The second set of error control bits may indicate that the matching operation failed at the memory device.

Abstract: A multi-channel decoder for generating a binaural signal from a downmix signal using upmix rule information on an energy-error introducing upmix rule for calculating a gain factor based on the upmix rule information and characteristics of head related transfer function based filters corresponding to upmix channels. The one or more gain factors are used by a filter processor for filtering the downmix signal so that an energy corrected binaural signal having a left binaural channel and a right binaural channel is obtained.

Abstract: An embodiment method includes: mapping a to-be-transmitted optical channel unit signal of n times a benchmark rate to X first optical channel physical link signals; adding a link sequence indicator overhead to each of the X first optical channel physical link signals, to generate X second optical channel physical link signals; and modulating and sending the X second optical channel physical link signals by using X preset optical modules in a one-to-one manner. A rate of the first optical channel physical link signal is mi times the benchmark rate, n?2, X?2, mi?1, and ? i = 1 X m i = n .

Abstract: Embodiments include methods performed by a copy engine of a computing device for generating a cyclic redundancy check (CRC) in a safety network, including copying a first dataset received from an interface bus to obtain a first dataset copy, copying a second dataset received from the interface bus to obtain a second dataset copy, generating, via a first stream-wise CRC engine in the hardware of the copy engine, a first CRC value for the first dataset copy and, in parallel, generating, via a second stream-wise CRC engine in the hardware of the copy engine, a second CRC value for the second dataset copy, transmitting, to a processor of the computing device, a first stream-wise CRC message including the first dataset copy and the first CRC value, and a second stream-wise CRC message including the second dataset copy and the second CRC value.

Abstract: After installation, a device may be asleep. A light signal device may send a message to the sleeping device to wake it up. This wake-up message may comprise the light signal device sending programmed light signals, the programmed light signals in modified morse code. An authentication part may also be included in the message. The light signal device may request an authentication message from the sleeping device.

Abstract: Methods, systems, and devices for wireless communication are described. A device—such as a base station or user equipment (UE)—may transmit a demodulation reference signal (DMRS) including signaling information in addition to channel estimation information. To improve reception of the DMRS signaling information, the transmitting device may employ data protection techniques to the signaling information and modify a data payload transmitted in the physical data channel associated with the DMRS. In one aspect, the transmitting device may modify cyclic redundancy check (CRC) bits in the payload to include verification for the signaling information. In another aspect, the transmitting device may determine a scrambling code based on the signaling information, and may scramble the payload based on the scrambling code.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for improving communication throughput despite periodic blockages. In some implementations, a method includes receiving, by a receiver and from a transmitter, code blocks transmitted according to a first set of communication parameters that includes one or more first interleaver parameters used to interleave information in the code blocks prior to transmission. Corrupted portions of at least some of the received code blocks are identified. A blockage duration and a blockage interval of a blockage of communication channel between the transmitter and the receiver are determined based on the corrupted portions of the received code blocks. A second set of communication parameters that includes one or more second interleaver parameters are determined based on the blockage duration and blockage interval.

Abstract: A method of image processing in wireless channel environment comprises steps of: dividing a frame of content image data into multiple blocks defined by a line; wirelessly transmitting the multiple blocks per line by coding channels in channel coding units by defining a transmission code rate according to a wireless channel environment information; determining whether there is a channel error for each block after decoding a received data; extracting an information of an image of an errored block; determining an image error correction method suitable for the extracted information; replacing the errored block with an error-corrected block according to the determined image correction method; and performing a post processing process to eliminate visual unnaturalness between the replaced block and a neighboring block at a block boundary.

Abstract: A circuit device includes a first physical layer circuit to which a first bus is connected, a second physical layer circuit to which a second bus is connected, and a processing circuit that performs transfer processing in which a packet received from the first bus via the first physical layer circuit is transmitted to the second bus via the second physical layer circuit. The processing circuit includes a SYNC generation circuit that generates an m-bit SYNC, and when the packet is received from the first bus, the processing circuit outputs the m-bit SYNC to the second physical layer circuit.

Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.

Abstract: A collector included in a data collection apparatus performs data collection to collect data from a PLC. A controller included in the data collection apparatus determines whether the collector is valid depending on whether the collector at a time when an instruction to start the data collection is provided matches the collector at a preset time, and causes the collector to start the data collection in response to the collector being valid.

Abstract: A differential signal processing device is described which includes an encoder configured to encode input data into one or more differential signals and a transmitter configured to sequentially transmit the one or more differential signals using a plurality of transmission lines. The encoder converts a plurality of bits, corresponding to a transmission time interval, among the input data into an encoding code array in the transmission time interval obtained by increasing an encoding unit time, encoded for each of the one or more differential signals, by an integer multiple.

Abstract: Disclosed are devices, systems and methods for providing hardware implementations of a quasi-cyclic syndrome decoder. An example method of reducing the complexity of a decoder includes receiving a noisy codeword that is a based on a transmitted codeword generated from a quasi-cyclic linear code; computing a plurality of syndromes based on the noisy codeword; selecting a first syndrome from the plurality of syndromes; generating a memory cell address as a function of the first syndrome; reading, based on the memory cell address, a coset leader corresponding to the first syndrome; and determining, based on the noisy codeword and the coset leader, a candidate version of the transmitted codeword.

Abstract: An example system to represent data with multi-dimensional cyclic symbols is provided. The system includes a representation engine, a symbol engine, and a translation engine. The representation engine is to provide a plurality of display symbols. Display symbols are selected from a set of multi-dimensional cyclic symbols. The symbol engine is to receive a plurality of received symbols. The translation engine is to convert the plurality of received symbols into a plurality of display symbols.

Abstract: A method and a transmitter for transmitting a pay load sequence are provided. The transmitter includes a ternary sequence mapper configured to map a binary data sequence to a ternary sequence stored in the transmitter, and a pulse shaping filter configured to generate a first signal based on the mapped ternary sequence. The ternary sequence includes elements of ?1, 0, and 1.

Abstract: A solid state storage device comprises a non-volatile memory controller configured to store data in a non-volatile memory, wherein the stored data is encoded using a first error-correcting code and a second Low Density Parity Check (LDPC) code. The non-volatile memory controller includes a hard-decision LDPC decoder to decode encoded data received from the non-volatile memory and provide a decoded data output. The hard-decision LDPC decoder selects a voting scheme at each iteration in a sequence of iterations of decoding to determine when to implement bit flipping at a variable node amongst a plurality of check nodes, each of the plurality of check nodes connected to a plurality of variable nodes.

Abstract: An SCI can perform transmission only or reception only, however, it is necessary to reset the SCI when transmission and reception is switched to transmission only or to reception only. A semiconductor device includes an interface circuit which performs a sequential communication of transmit or receive according to a synchronous clock. The interface circuit includes a register to specify an operation enabled state which is at least one of a transmit state and a receive state, and a mode control circuit to change at least one mode of transmit or receive in the operation enabled state.

Abstract: A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.

Abstract: A phase ambiguity processing method and device are provided. The phase ambiguity processing method includes: deciding symbols on a Y polarization state and an X polarization state of a received signal, and mapping to obtain first bit information, where the received signal includes a plurality of first signals; checking and analyzing the first bit information to generate a first check result; judging the first check result to obtain a judgment result as to whether the received signal has phase ambiguity; acquiring at least one of the plurality of first signals in the received signal when the judgment result indicates that the received signal has phase ambiguity; performing phase rotation on the first signal to obtain a second signal; and checking and analyzing the second signal, storing the second signal so that the first signal is replaced with the second signal for decoding processing if a check result is normal.

Abstract: A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.

Abstract: Systems and methods that employ an application-assisted approach to adaptive spatio-temporal error concealment in video decoders. The systems and methods employ a video receiver that can receive real-time video frames from a video transmitter over a wired and/or wireless network. The video receiver includes an end system configurable as an application for consuming the content of the real-time video frames. The end system application can determine whether each received real-time video frame is complete or incomplete, whether each received slice is complete or incomplete, and provide such information to the video decoder for use in avoiding errors while decoding the respective real-time video frames.

Abstract: A method for protecting encoded data from algebraic manipulation includes receiving a data word s?Kd to be protected, randomly selecting two integers a ?{0, . . . , q?1} and b ?{0, . . . , ?q?1}, finding a point (?, ?) on a Hermitian curve over a field Fq that corresponds to the randomly selected integers (a, b) from a mapping (a, b)(?, ?)=(ua, ua?q+1z+vb), where u a := { 0 if ? ? a = 0 , ? 1 a - 1 otherwise , ? V b := { 0 if ? ? b = 0 , ? 2 b - 1 otherwise , and z is an element of the field Fq of unit trace, and where ?1 is a fixed primitive element of the field Fq and ?2 is a primitive element of a field F?q?Fq, and calculating a sum fs(?, ?)=?id+1?jd+1+?k=1d?ik?kjk for a set of d+1 integers pairs I ={(ik,jk)}k=1d+1, where the encoded word is a triple (s, (?, ?),fs(?, ?)).

Abstract: Disk drives with a Channel System and Write Driver Preamp architecture that dynamically adjusts the write driver's signal wave-shape depending on the write data signal pattern are described. The wave-shape control signal is generated in the Channel and transmitted to the Write Driver Preamp. Embodiments of the invention provide discrete n-level overshoot amplitude control using amplitude-level modulated (AML) signal. One embodiment implements a look-ahead strategy overshoot amplitude control where the overshoot amplitude for each transition depends only on the subsequent (following) bits in the data stream and not on any previously recorded data.

Abstract: The technology disclosed herein provides a method of verifying data read from a data block when the cell number of the data block does not match an ECC value stored in the data block. In particular, the method includes accessing a data block in an indexed sequence of data blocks based on a cell number, wherein each data block in the indexed sequence includes a stored ECC value; retrieving an offset associated with the cell number of the data block; generating an ECC value based on the cell number and the offset; and determining whether the generated ECC value and the stored ECC value satisfy an integrity condition.

Abstract: Disclosed are an LDPC encoding/decoding method and a device using same. The method includes the steps of: (a) generating an information bit sequence by determining information bits to be encoded from among a group of information bits; (b) generating a modified information bit sequence by inserting a preset error floor prevention bit into at least one preset position in the information bit sequence; (c) generating a parity check bit on the basis of the modified information bit sequence; and (d) performing encoding by using the modified information bit sequence and the parity check bit. According to the disclosed method, performance degradation of LDPC encoding and decoding due to an error floor phenomenon can be prevented.

Abstract: Systems and methods are provided for decoding data stored on a storage device. A decoding method is described for retrieving data from the storage device, wherein the retrieved data are encoded using a product code having a first dimension and a second dimension. The decoding method includes processing at least one codeword from the first dimension to form detector soft information, decoding the at least one codeword from the first dimension based on the detector soft information to form a first decoder soft information, and decoding at least one codeword from the second dimension based on the first decoder soft information to form a second decoder soft information.

Abstract: A multi-link input/output (I/O) interface uses both feed-forward and feedback signaling to reduce the impact of noise on data capture at a memory controller. To transfer data from a source module to a destination module, a defined pattern is communicated from the memory module along a master channel concurrent with the memory module providing data via one or more slave channels. Based on the phase of the defined pattern as it is received, the multi-link I/O interface feeds forward to the slave channels control signaling whose phase reflects a predicted noise pattern for the system. Each slave channel performs CDR by adjusting timing of its corresponding capture clock signal based on the fed forward control signaling and based on feedback signaling for the corresponding slave channel, whereby the feedback signaling reflects an error measurement between a phase of a capture clock signal and transitions in received data.

Abstract: Apparatus, system and method for encoding and decoding ancillary code for digital audio, where multiple encoding layers are merged. The merging allows a greater number of ancillary codes to be embedded into the encoding space, and further introduces efficiencies in the encoding process. Utilizing certain error correction techniques, the decoding of ancillary code may be improved and made more reliable.

Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Abstract: A memory device includes but is not limited to a non-volatile memory array and control logic integrated with and distributed over the non-volatile memory array. The control logic can be operable to maintain a plurality of copies of data in the non-volatile memory array and detect errors by comparison of selected ones of the plurality of copies.

Abstract: Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.

Abstract: One embodiment provides a PHY having a Media Access Control (MAC) and a Forward Error Correction (FEC) decoder, capable of error detection and error correction for FEC encoded packets based on FEC parity data included in the FEC encoded packets. The FEC decoder is capable of being enabled into different configurations of different operations to perform on FEC parity data included in the FEC encoded packets. The different configurations having different respective associated latencies.

Abstract: In operation, a transmitting device selects a synchronization pattern associated with the desired timeslot that is at least mutually exclusive from synchronization patterns associated with other timeslots on the same frequency in the system. Once selected, the transmitting device transmits a burst embedding the synchronization pattern that was selected, where appropriate. If the receiving device detects the synchronization pattern, it immediately synchronizes with the timeslot with confidence that it is synchronizing to the desired timeslot by using sets of synchronization patterns associated with the desired timeslot that are at least mutually exclusive from synchronization patterns associated with the other timeslots on the same frequency.

Abstract: Apparatus, system and method for encoding and decoding ancillary code for digital audio, where multiple encoding layers are merged. The merging allows a greater number of ancillary codes to be embedded into the encoding space, and further introduces efficiencies in the encoding process. Utilizing certain error correction techniques, the decoding of ancillary code may be improved and made more reliable.

Abstract: A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables.

Abstract: A method for determining an initial alignment for a frame of input data is provided. A frame for the input data is set, and the frame is synchronized. Specifically, a syndrome check of the frame is performed using a first predetermined number of bits, and a slip of a second predetermined number of bits is requested following the syndrome check. Evaluation of the syndrome check to determine whether the frame is aligned can then be performed in parallel with the slipping. The evaluation and slipping can then be repeated if the frame is misaligned. When the frame is aligned, a lock condition can be indicated, and the slip performed in parallel with the evaluation indicating that the frame is aligned can be deasserted. In addition, when the frame is aligned, error correction on the frame can be performed, and the error corrected frame can be formatted.

Abstract: A cache device is disposed on a connection path between a user computer executing a software application and a network. The application exchanges data with a further computer via the network. The cache device includes a cache memory and a processor. The cache device is configured to measure, by the processor, a first latency between the user computer and the further computer. The cache device is further configured to determine an acceptable latency range based on the latency and a requirement of the software application. The cache device is further configured to measure a second latency between the user computer and the further computer. The cache device is further configured to store, in the cache memory, a set of data transmitted from the user computer to the further computer, if the second latency is not within the acceptable latency range.

Abstract: An embodiment of an apparatus includes a detector to receive a first input signal and a second input signal to provide a first error signal and a second error signal. A pulse width determination block receives the first and second error signals, as well as a digital oscillating signal, to output a first pulse width value and a second pulse width value, respectively. A pulse width accumulator accumulates the first and second pulse width values responsive to at least one cycle of the digital oscillating signal to provide a first accumulated value and a second accumulated value. An error generator provides an error value as a difference between the first accumulated value and the second accumulated value. The error value represents a pulse width difference between the first input signal and the second input signal indicative of a phase difference between the first input signal and the second input signal.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract: A data encoding method includes receiving a sequence of N scrambled blocks produced by scrambling a sequence of N preliminary blocks comprising one of a data block and a control block, the control block being one of K types and including a block-type field, each scrambled block having a block header indicating a scrambled data block or a scrambled control block; encoding the sequence of N scrambled blocks into an encoded block by deleting the block headers, and in the event the sequence contains any scrambled control blocks, deleting a set of scrambled bits corresponding to respective block-type field bits of at least one control block in the sequence of preliminary blocks such that the other block-type field bits are sufficient to indicate the type of control block, and adding position indicator bits indicating position of each scrambled control block in the received sequence of scrambled blocks.

Abstract: Error concealment guided robustness may include identifying a current portion of a current video stream. Identifying the current portion may include identifying a feature, or a vector of features, for the current portion. An estimated vulnerability metric may be identified based on the feature and an associated learned feature weight. An error correction code for the current portion may be generated based on the estimated vulnerability metric. Error concealment guided robustness may include generating learned feature weights based on one or more training videos by generating vulnerability metrics for the training videos and identifying relationships between features of the training videos and the vulnerability metrics generated for the training videos.

Abstract: A multiple access scheme is described. A first bit stream is scrambled from a first terminal according to a first scrambling signature. A second bit stream is scrambled from a second terminal according to a second scrambling signature, wherein the first bit stream and the second bit stream are encoded using a low rate code. The first scrambling signature and the second scrambling signature are assigned, respectively, to the first terminal and the second terminal to provide a multiple access scheme.

Abstract: A receiving apparatus for receiving a radio signal through an antenna. The radio signal is transmitted by a moving transmitting apparatus and has a frame configuration which includes at least a main information portion that includes information main part based on an image signal and an added portion that includes synchronization information and parameter information specific to the transmitting apparatus. The receiving apparatus includes a detecting unit that is configured to detect, from the received radio signal, an arrangement position of the parameter information in a frame configuration in which an error-correcting code is added immediately after the parameter information to be transmitted in a predetermined arrangement position of the frame configuration. A parameter information error correcting unit is configured to perform error correction on the parameter information with the error-correcting code that is added immediately after the detected arrangement position of the parameter information.

Abstract: A communication apparatus realizes an FEC function. In the communication apparatus, a T_FEC-pattern comparing unit calculates a code distance between a pattern of an input FEC frame falling in a certain detection window and the pre-defined T_FEC pattern for each of the detection windows one after another. Moreover, a code-distance comparing unit compares the code distances with each other to detect a code for boundary identification T_FEC between an IEEE802.3 frame and a FEC parity. Finally, a boundary-signal generating unit generates, based on the detected code for boundary identification T_FEC, a T_FEC boundary signal that indicates a detection position of the T_FEC in the input FEC frame.

Abstract: Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.

Abstract: A received optical signal is coherently demodulated and converted into orthogonal x-polarization samples, and y-polarization samples. These samples are converted into signal x-samples and signal y-samples by an FIR butterfly filter. Correction values are calculated in an error calculating circuit of a control unit and added to filter transfer functions derived by a standard algorithm to determine corrected filter coefficients. Degenerate convergences calculating the transfer functions are avoided.

Abstract: Transmission techniques are provided that improve service continuity and reduce interruptions in delivery of content that can be caused by transitions that occur when the User Equipment (UE) moves from one cell to the other, or when the delivery of content changes from a Point-to-Point (PTP) connection to a Point-to-Multipoint (PTM) connection in the same serving cell, and vice-versa. Such transmission techniques enable seamless delivery of content across cell borders and/or between different transmission schemes such as Point-to-Multipoint (PTM) and Point-to-Point (PTP). Mechanisms for adjusting different streams and for recovering content from each data block during such transitions are also provided so that data is not lost during a transition. In addition, mechanisms for realigning data during decoding at a receiving terminal are also provided.

Abstract: The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads.

Abstract: Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.

Abstract: In one embodiment, a Television (TV) receiver to perform a method of synchronizing a demodulator at a Viterbi decode input in the TV receiver using one or more bit de-interleaved even and odd Orthogonal Frequency Division Multiplexing (OFDM) symbols is provided. The method includes (i) performing a Viterbi decoding on the bit de-interleaved even and odd OFDM symbols when a frame boundary does not exist for the bit de-interleaved even and odd OFDM symbols, (ii) performing a convolutional encoding on an decoded data output of the Viterbi decoding, (iii) determining whether an output of the convolutional encoding of the bit de-interleaved OFDM symbols matches an input at a Viterbi decode, and (iv) determining whether the output of the convolutional encoding of the bit de-interleaved even and odd OFDM symbols matches with a SYNC pattern or a SYNC? pattern to obtain a RS packet align boundary.