Abstract: A data file (22) having a plurality of frames is received, with each frame having a syncword. A data string (52) including a plurality of potential syncwords (54) is identified in the data file (22). One of the potential syncwords (54) is randomly selected. A subsequent potential syncword address is determined based on the selected potential syncword (54). Whether a subsequent potential syncword exists at the subsequent potential syncword address is determined. The data file (22) is decoded based on the subsequent potential syncword in response to the subsequent potential syncword existing at the subsequent potential syncword address.

Abstract: A signal used in the transmission of data in a communication system (for example in an ATM network), comprised of immediately successive cells. For the purpose of cell synchronization, filler cells (I) containing a predefined bit pattern are provided. This pattern is provided with an error protection code that differs from the error protection code used for the user data. Even if the user data should coincidentally contain the predefined bit pattern, the synchronization circuit will not be able to be simulated, since this false bit pattern is provided with a different error protection code. In order to test and ensure the synchronization state, a BIP value at the end of the cell is checked at the receiver end.

Abstract: In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in a code string, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.

Abstract: In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in a code string, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.

Abstract: A method and apparatus for reacquiring synchronization of a clock synchronization signal with a data signal in a non-tracking storage device is presented. A packet error detector detects errors in data packets from a data signal and generates a packet error status for each reconstructed packet. A read quality detector monitors the packet error status and determines whether the quality of the data signal is of an acceptable versus unacceptable read quality condition. The read quality condition is based on the number of consecutive packets in which an error is detected. Upon detection of an unacceptable read quality condition, the read channel is disabled and the clock synchronize signal is relocked to a known reference frequency. The read channel is then reenabled and the clock synchronization signal is relocked to the data signal.

Abstract: The present invention provides checking on information units sent and received as packets over fiber channel networks by providing check bits on the header information and separate check bits on the data.

Abstract: An apparatus and a method to access data from a digital recording medium configured to store data in sectors delimited by a predetermined sequence of sync patterns. The apparatus includes a sync pattern detector and a sync sequence detector to detect whether a sequence of sync patterns detected by the sync pattern detector matches the predetermined sync pattern sequence. The sync sequence detector generates a sync error signal whenever a detected sync pattern fails to match an expected sync pattern taken from the predetermined sync pattern sequence. A sync error signal counter counts the number of sync error signals generated by the sync sequence detector and a comparator compares the number of sync error signals counted by the sync error signal counter with a sync error threshold, the comparator generating a disk error signal when the threshold is exceeded.

Abstract: A method and apparatus for controlling a memory to record data received at random rate into a fixed rate and to reproduce the data recorded in a fixed rate includes a shuffle memory with a plurality of memory banks for recording and reproducing a digital data at a fixed rate and the smoothing memory is also allocated to a surplus region of the shuffle memory. By using a serial clock and a plurality of FIFOs, the data can be efficiently recorded and reproduced without collision.

Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.

Abstract: A process and apparatus for synchronizing the block counter of an RDS radio data receiver is described. According to the process, the bits stored in a 26-bit shift register, are cycled at least n times in said register, n being the number of allowable offset words, and the shift register content is X-OR gated with another offset word in a given sequence for each cycle. The gating result is received by a syndrome detection circuit, which triggers a sync pulse when the zero syndrome is detected, and the sync pulse resets the bit counter to zero and sets the block counter to the address counter status assigned to the offset word in the offset word generator.

Abstract: A data reception unit having improved robustness against synchronization code errors. In data transmission, the synchronization code is always located in the headers of coded data contained in the package payload. Where the number of synchronization code bit errors falls below a threshold value, decoding is performed ignoring the errors. Where the number of bit errors exceeds the threshold value, the encoded data in the packet is discarded. Robustness against errors are modified through manipulation of the threshold value in response to transmission path type and error status.

Abstract: Disclosed is a peripheral device for reliably detecting synchronization patterns in CD-ROM media. The peripheral device has an internal circuitry for controlling and processing data that is read from a medium of the peripheral device is disclosed. The peripheral device comprises a digital signal processor, a decoder circuit, and a state machine. The digital signal processor is configured to receive the data that is being read from the medium of the peripheral device. The decoder circuit is coupled to the digital signal processor and forms a part of the internal circuitry. Further, the decoder circuit includes an internal RAM that is configured to store a sector of the data including a current sync pattern and a next sync pattern. The state machine resides in the decoder for analyzing the current sync pattern and the next sync pattern of the sector of the data. In the analysis mode, the state code is configured to determine whether a fatal error is present in the data.

Abstract: A digital subscriber line communication system does not require the use of a plain old telephone service (POTS) splitter in the resident's home. Digital signal processing is utilized to adapt to varying subscriber line conditions coming from POTS telephone equipment. The digital subscriber line modem includes a control circuit that utilizes a Reed-Solomon decoder and a synchronization error generator. The Reed-Solomon decoder provides a frame error signal, and the synchronization error generator responds to the frame error signal to generate a synchronization error signal. The synchronization error generator is configured as a leaking integrator to provide the synchronization error signal in response to a relatively large number of frame error signals occurring in a period of time. A resynchronization operation is performed in the modem in response to the synchronization error signal.

Abstract: An ATM cell synchronization circuit can be realized by a circuit construction operable at low speed. Cell strings developed into eight parallel strings by a serial to parallel development circuit are further developed into 8n parallel strings. A frequency of a clock signal synchronous with bytes of the input cell string is divided into n by a frequency divider circuit for lowering speed to be 1/n. The parallel developed signals are rearranged by a shifted register into a signal string for detection by HEC (Header Error Control) detecting circuit. Then, an HEC byte is detected by the HEC detecting circuit. In order to detect the HEC bytes located at n positions, n in number of HEC detecting circuits are provided, At this time, the HEC byte after n cells becomes the same position. The interval of n cell is fifty-three. Therefore, a counter counting fifty-three is provided. Respectively predetermined values are detected by the decoders to generate detection signals.

Abstract: A bit shift value of a synchronizing signal is detected. That is, after respective hamming distances between data from the first part of the synchronization signal and the respective pre-detects words, which are calculated by hamming distance calculators, are respectively compared with a predetermined value by comparators, the compared results are encoded by an encoder and the results are output as the bit shift value. Such bit shift value may be utilized to shift positions of the synchronizing signals of synchronizing blocks.

Abstract: A disc recording medium is provided for enhancing a capability of correcting a burst error caused by small dust left on the surface of a disc substrate. The data of two-dimensionally arrayed ECC blocks consisting of 172 words.times.192 rows contains the PI parity and the PO parity added in the two error-correcting systems. The PI parity is intended for error correction for data arranged to go down by one row with advance of one word in the direction of a bit stream. The PI parity is intended for going back to the first row when the data being interleaved exceeds 192 rows. The PO parity is intended for error correction for data arranged to interleave the data perpendicularly to the bit stream.

Abstract: A de-framer (72) in a communications gateway (22) translates videoconferencing information from a circuit-switched format to a packet-switched format. A demultiplexor (78) extracts a bitstream containing video information that includes error-correction-code fields disposed at predetermined locations with respect to synchronization bits spaced by a synchronization interval and forming a predetermined synchronization sequence. A frame checker (88) for checking the error-correction code finds codeword boundaries by comparing the predetermined synchronization sequence with sequences of synchronization-interval-spaced video-bitstream bits until it finds a match. To do so, the frame checker (88) takes a group of video-bitstream words offset from each other by the synchronization interval. It compares each word in the group with a respective synchronization word consisting of a word-width replication of a respective synchronization bit.

Abstract: A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit and each including at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit provided internally of the node. The system further includes a transfer end signal indicating an end of the data transfer, in synchronism with the clock signal, and a phase reference signal bus connected to each of the plural nodes, a data bus connected to each of the plural nodes for transmitting the data and a transfer end signal bus connected to each of the plural nodes for transmitting the transfer end signal.

Abstract: A disk storage system is disclosed wherein user data received from a host system is first encoded according to a first channel code having a high code rate, and then encoded according to an ECC code, such as a Reed-Solomon code, wherein the ECC redundancy symbols are encoded according to a second channel code having low error propagation. In the preferred embodiment, the first channel code is a RLL (d,k) code having a long k constraint which allows for longer block lengths (and higher code rates). During read back, a synchronous read channel samples the analog read signal a synchronously and interpolates the asynchronous sample values to generate sample values substantially synchronized to the baud rate. In contrast to conventional synchronous-sampling timing recovery, interpolated timing recovery can tolerate a longer RLL k constraint because it is less sensitive to noise in the read signal and not affected by process variations in fabrication.

Abstract: In a system recording compressed video and audio signals or computer user data on a disk in the sector unit, to reproduce the data in a simple fashion at a high speed, data to be recorded on the disk is divided into data in a predetermined unit so as to add a first error correction (C1) code to each of the resultant data, which form (C1) correction blocks. Sectors are produced each including a plurality of (C1) correction blocks. Added to each (C1) correction block is a code enabling identification of a sector. To all data in the plural (C1) correction blocks, a second error correction (C2) code is added to record the resultant data on the disk to allow interleaving or deinterleaving completing in a block. The capacity of each sector is set to be substantially equal to that of a plurality of transport packets.

Abstract: In a system recording compressed video and audio signals or computer user data on a disk in the sector unit, to reproduce the data in a simple fashion at a high speed, data to be recorded on the disk is divided into data in a predetermined unit so as to add a first error correction (C1) code to each of the resultant data, which form (C1) correction blocks. Sectors are produced each including a plurality of (C1) correction blocks. Added to each (C1) correction block is a code enabling identification of a sector. To all data in the plural (C1) correction blocks, a second error correction (C2) code is added to record the resultant data on the disk to allow interleaving or deinterleaving completing in a block. The capacity of each sector is set to be substantially equal to that of a plurality of transport packets.

Abstract: An error protection method for multimedia improves data recovery and channel throughput in channels which cause a random error and a burst error by using a rate compatible punctured convolutional code (RCPC) and an automatic retransmission on request (ARQ). In a process of decoding a plurality of packets of given information, the error protection method includes the steps of a) decoding one of the plurality of packets, b) decoding another packet when an error occurs during the decoding in step a), c) decoding a combination of the packets from steps a) and b) or a third packet when an error occurs in step b), and d) repeating step c) until the decoding error no longer occurs. The error protection method has the characteristics of both Type-1 and Type-2 ARQ methods. Therefore, one can obtain constant channel throughput in a channel containing burst errors, a channel containing random errors, and a channel in which the two types of error patterns coexist simultaneously.

Abstract: Methods and apparatus for performing packet synchronization recovery and error detection operation on packets including a CRC check byte, e.g., MCNS packets, are described. The present invention uses a memory during a sync acquisition mode of operation to serve as a storage device for the output of a first function circuit. The delayed bits are used as the input along with current bits from the packet stream to a second function circuit. The second function circuit generates a syndrome byte of interest. When the received packets are error free and the decoder is properly aligned with the packet structure of the bitstream, the syndrome byte of interest will assume a preselected value, e.g., 47 Hex. Once packet synchronization has been achieved, the relatively few bits output by the first function circuit which are required as delayed inputs to the second function circuit are identified and stored using a delay register which is much smaller than the memory.