Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

Abstract: A method to synchronize Fault Code Memory between at least a first module and a second module in an engine controller unit; each said module in electronic communication with each other and having volatile and non volatile memory; said modules in electronic communication; when compatibility of versions of static fault codes between the modules is established, the first module downloads and saves the static fault code table resident on the second module in nonvolatile memory for access by a diagnostic tool.

Abstract: A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting are preformed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization is effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization.

Abstract: A receiver including a switch for switching output of a memory to one of paths according to content of the output. The memory stores information bits, first check bits and second check bits. The first check bits and second check bits are switched to one of the paths via a rate dematch apparatus to a decoder. The information bits are switched directly to the decoder.

Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.

Abstract: In a method for synchronizing to a signal encoded as a group of blocks, a data symbol is received and stored with previously received data symbols as a current potential group. Errors, if any, are detected in the current potential group, and a level of errors associated with the current potential group is deter mined. The current potential group is determined to be an actual group if the current potential group is without errors. Also, the current potential group is determined to be an actual group if a set of potential groups including the current potential group and at least one previous potential group has an acceptable level of errors.

Abstract: The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M1(x)), a second polynomial (M2(x)), and a parity code polynomial (R(x)). The method comprises: first, designing a first code generator polynomial (G1(x)); next, dividing M1(x)x4 by G1(x) to obtain a first remainder polynomial (R1(x)); next, generating a second code generator polynomial (G2(x)) from G1(x); next, generating a third polynomial (M3(x)); next, dividing M3(x)x4 by G2(x) to obtain a second remainder polynomial (R2(x)); next, performing an adding procedure to R1(x) and R2(x) to obtain R(x); finally, obtaining the parity code from each coefficient of R(x).

Abstract: FEC frame synchronization in a DAB-IP system comprising FEC frames includes receiving FEC packets each comprising a FEC packet header and a FEC data field comprising padding bytes at an end of a last FEC packet received; comparing a received FEC packet header with a known FEC packet header until a number of bit errors in the received FEC packet header is less than or equal to a predetermined amount; and matching the received FEC packet header and the padding bytes until at least one of the following actions occur thereby resulting in receiver locking: a number of successive FEC packet headers mismatches in the received FEC packet header; a predetermined number of FEC packets end without padding matching; and FEC packet header and padding matching occurs. The received FEC packets are tracked after receiver locking has occurred to ensure FEC parity packets are positioned properly in the FEC frames.

Abstract: The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads.

Abstract: Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors even when those errors are not confined to a single block. Disclosed techniques permit a reduction in the amount of forward error correction used. For example, in general, to correct t errors, a linear cyclic error correction code requires a Hamming distance of at least 1+(2t)[wt(s(x))]. Embodiments of the invention allow correcting the multiplied errors with a Hamming distance of only 1+(t)(1+wt(s(x))) over the block size n, wherein wt(s(x)) is the weight of the scrambler polynomial s(x).

Abstract: An FEC frame structuring device includes a multi-lane distributing unit that distributes a data frame to be transmitted to n lanes, FEC coding units each performs FEC coding of the distributed data frame independently for each of the n lanes to generate an FEC frame, a multiplexing unit that multiplexes the FEC frame from the FEC coding units by relating to m channels of an optical signal, a demultiplexing unit that demultiplexes the m channels of the received optical signal by relating to the n lanes, FEC decoding units each performs FEC decoding of the demultiplexed FEC frame independently for each of the n lanes, and a multi-lane synchronizing unit that synchronizes the n lanes with each other after the FEC decoding performed by the FEC decoding units to reconstruct the original data frame.

Abstract: A system and method for reducing delay introduced by de-jitter buffers in a VoIP network is presented. The method aspect for receiving and presenting speech data received from a VoIP network comprises monitoring speech-related packets received from a packet network and based on the monitoring, either maintaining a normal speech rate, compressing the speech rate or expanding the speech rate. The speech associated with the received packets is played out (presented audible via a speaker or other means) at the normal, compressed or expanded speech rate.

Abstract: There is provided a signal demodulating device, including: a time frequency converting unit (6) for converting a frequency division multiplexing signal on a time axis into a signal on a frequency axis to output a data carrier, a pilot carrier, and a transmission control carrier; an equalizer (7) for equalizing the data carrier and the transmission control carrier according to a characteristic value of a transmission line obtained from the pilot carrier to output an equalized data carrier and an equalized transmission control carrier; a first decoding unit (9) for decoding the equalized transmission control carrier; and a first correcting unit (10) for performing first error-correction on an output of said first decoding unit (9) to output first control information and a first decoding flag that indicates a status of the first error-correction.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract: A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form.

Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Abstract: Methods and apparatus for extracting a portion of data from a plurality of BIS data are disclosed. The portion of data can be extracted from the plurality of BIS data stored in a first storage unit when those BIS data are accessed by other components. Alternatively, the extraction of the portion of data can be performed when the plurality of BIS data is written into the first storage unit. The extracted data are stored in a second storage unit to improve the accessing efficiency thereof.

Abstract: This invention relates to a circuit technique for rapidly and efficiently correcting for read and write data errors in a digital semiconductor memory. More generally, this can also be in any type of digital memory or digital communication channel. As semiconductor memories get smaller and smaller, the memory cells are subject to higher rates of manufacturing defects and soft errors. Correction of manufacturing defects is achieved through extensive testing and use of redundant memory cells to replace defective memory cells. Soft errors are very difficult to detect and correct and only the simplest parity check codes have been implemented. The cost in terms of delay time and computational complexity are barriers to the implementation of ECC. This invention represents a device that introduces very little delay and requires minimal hardware complexity to implement.

Abstract: Encoded data is transmitted between synchronized sending and receiving digital systems across a lossy transmission media. The systems include respective encoder and decoder information records. If data packets are lost, the encoder rebuilds the encoder record without the missing packet data. Encoding continues using previous encoder records. In a method, packet data is encoded using encoding information in an encoder information record. A new encoder information record is built. The encoded packet data is transmitted to the receiving system with a header. The receiving system examines the header. The packet is decoded using a decoder information record and the decoder information record is updated. The packet is acknowledged to the sending system to enable the sending system to update encoder information. If the packet is lost, the encoder information is conditioned to rebuild new encoder information without the lost packet data. Thus, encoding history is used even when packets are lost.

Abstract: A demodulator circuit for demodulating a signal modulated by frequency shift keying discriminates the frequency of the signal to produce demodulated data. When the demodulated data match a known synchronization pattern, or are complementary to the known synchronization pattern, the demodulator circuit latches a value indicating whether the demodulated data match or are complementary to the synchronization pattern. If the latched signal indicates matching data, subsequent demodulated data are output as is. If the latched signal indicates complementary data, subsequent demodulated data are inverted and the inverted data are output. The output data are therefore correct even if the demodulated data are inverted.

Abstract: An RDS compatible receiver has a demodulator which demodulates RDS data, a register which converts the demodulated RDS data to block data and outputs the block data, an offset generating unit which predicts and outputs an offset word of the block data based on values of a pattern match flag signal and a synchronization flag signal, an error correction processing unit which performs error correction of the block data using the predicted offset word, compares the number of error corrections with a predetermined correction threshold, determines whether the predicted offset word is right or not based on the comparison result, and outputs the pattern match flag signal based on the determination result, and a synchronization determining unit which detects whether or not the predicted offset word determined to be right matches a predetermined offset sequence pattern, determines whether RDS block synchronization is established or not, and outputs the synchronization flag signal based on the determination result.

Abstract: In a synchronous information reproduction apparatus, a receiving section sequentially receives a clock signal. A storing section stores object information to be sequentially reproduced from a series of reproduction points. A reproduction point generating section generates location information indicative of a reproduction point of the object information stored in the storing section. A reproducing section reads and reproduces the object information from the storing section based on the reproduction point generated by the reproduction point generating section. A synchronizing section synchronizes an incremental speed of the reproduction point generated by the reproduction point generating section with a reception timing of the clock signal based on a reception time interval of the clock signals. An outputting section outputs contents of the object information reproduced by the reproducing section.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: Improved error correction techniques and circuitry are provided. The error correction circuitry may be integrated with a programmable logic device (PLD), or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of providing data recovery during extended drop out periods of a high speed serial link with an embedded clock signal.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: A semiconductor device includes a CPU core circuit, a bus connected to the CPU core circuit, and a memory BIST circuit configured to perform a memory test in response to an instruction supplied from the CPU core circuit through the bus.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: A communication system includes a transmitter and a receiver. The transmitter transmits a signal encoded by a low-density parity-check (LDPC) coding. The receiver includes a decoder, a phase error estimator, and a correction unit. The decoder decodes the signal at a plurality of sampling points using a single iteration of sum-product decoding. The phase error estimator estimates a phase error of the signal using minimum mean square error (MMSE) estimation and soft decision information obtained by the sum-product decoding. The correction unit corrects the signal using the phase error.

Abstract: A data transfer apparatus improving data transfer rate regardless of the original transfer mode in a USB interface is disclosed. A computer includes a bulk packet generation unit and an isochronous packet transmission unit. The bulk packet generation unit generates a bulk packet (or a control packet) which is a USB packet and has a predetermined structure including a first data area by describing data which is taken as an object of transfer in the first data area. The isochronous packet transmission unit generates an isochronous packet which is a packet in USB isochronous transfer and has a predetermined structure including a second data area by incorporating at least one bulk packet into the second data area, and isochronously transfers the isochronous packet to the mobile telephone over the USB interface.

Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

Abstract: An error flag generation apparatus and method for error correction, wherein the apparatus includes: a frame-sync error memory which stores frame-sync error information for each data block; a BIS (Burst Indicator Subcode) error flag memory which stores a BIS error flag for each data block; and an error flag generator, which generates an error flag indicating error existence/absence for ECC (Error-Correction Coding) data with reference to the frame-sync error information stored in the frame-sync error memory and the BIS error flag stored in the BIS error flag memory.

Abstract: A method of recording data as presence/absence of marks on an information recording medium includes a step of obtaining data pieces, each of which has size of one block and is made by adding error-correction-purpose data to information data, a step of attaching to each of the data pieces a synchronizing signal that includes a portion having the marks and a portion having no mark, a step of recording the data pieces on the information recording medium in units of the one block inclusive of the synchronizing signal, and a step of placing a concatenation point at a predetermined position within the synchronizing signal when adding, or writing in an overwriting manner, the data pieces in units of the one block, the concatenation point defining a position at which said adding or said writing starts.

Abstract: A method and arrangement for using Synchronous Dynamic Random Access Memory (SDRAM) as storage for correction and track buffering in front end ICs of optical recording or reproduction devices. Data to be stored or read is organized in appropriate bursts for accelerating the SDRAM (SDR) traffic. The SDRAM is built around two banks of memory, and are accessed using a pipelined address logic, thereby accelerating access speeds.

Abstract: An mp3-standard bitstream is formatted into a sequence of fixed-length data frames. These include headers, side information, main information and a remaining data field without generally defined information denoted as ‘ancillary data’. The mp3PRO format is an extension of the mp3 format, wherein the additional mp3PRO data are transferred in the ancillary data fields. In various applications, e.g. Internet music search machines, a necessity arises for a fast determination of the bitstream types. Such determination is normally executed using an mp3PRO decoder. However, because the frame header does not contain a corresponding pointer to the start address of the ancillary data field, an mp3PRO decoder must first completely decode at least one data frame according to the mp3 standard in order to find the end address of the mp3 data and thereby the following start address of the mp3PRO data in that data frame.

Abstract: An example receiving apparatus includes a reception clock controlling section for controlling clock supply to the components thereof. A reception section receives a communication packet transmitted from a destination and a received packet analyzing section judges whether or not the received packet is correct and analyzing the received packet. A reception memory section stores the received packet of any packet type and a reception registering section stores the received packet until a clock is supplied to the reception memory section. A received data outputting section outputs the received packet stored in the reception registering section and the reception memory section to a host CPU.

Abstract: A low overhead coding technique is disclosed. In one particular exemplary embodiment, the low overhead coding technique may be realized as a method for coding information comprising receiving a block of information, and encoding the block of information such that a first value of a first symbol in the encoded block of information is not equal to a second value of an adjacent second symbol in the encoded block of information or a third value of an adjacent last symbol in a previously encoded block of information.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: The present invention relates to a method of synchronization between communication networks exchanging information by frame of informations, each communication network having clock and the number of clock pulses is monitored by a counter the synchronization is made by reading information representing the counted clock pulses of the clock of the first network at the appearance of a reference event, inserting at least said information or calculated information on the basis of said information into the frame of information as the synchronization information, transferring said frame of information from the first to the second network, reading information representing the number of counted clock pulse of the clock of the second network at the appearance of reference event, reading synchronization information inserted in received frame of information from the first network, calculating a difference between information and synchronizing the second network.

Abstract: In a frame sync method, a receiver searches for the presence of an N-symbol long unique word pattern. For each possible frame sync detected, the receiver proceeds to demodulation and FEC processing. After each iteration of the FEC decoder, the detected unique word pattern is compared to the expected one and the frame sync is detected if the number of unique word errors has decreased.

Abstract: A synchronization variable intended for a second clock signal is generated from a first clock signal and a phase variation signal. A first approximation of the second clock signal is determined, and other approximations close to the first approximation are also determined. An error is calculated for each of the approximations, and the best approximation is taken as the second clock signal.

Abstract: A data processing apparatus according an aspect of this invention has a syndrome calculation unit configured to calculate the syndrome of a demodulated data sequence. The syndrome calculation unit includes a calculation unit configured to make the calculation required to realize syndrome calculation of demodulated data for each frame obtained by removing the sync code from one sync frame.

Abstract: Described are a storage system and method for detecting an intermittent loss of synchronization in communication signals received by an enclosure connected to a Fibre Channel loop. A control board produces a first signal representing a status of communication signals received by the control board. The first signal is in one of a plurality of logical states. A first logical state indicates that the status of the communication signals is invalid and a second logical state indicates that the status of the communication signals is valid. The control board includes a glitch-detection circuit that places a second signal in an asserted logical state when the first signal is in the first logical state during a time interval and holds the second signal at the asserted logical state when the first signal transitions from being in the first logical state to being in the second logical state during the time interval.

Abstract: A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.

Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.

Abstract: A bus device comprises a clock generator that is adapted to generate a clock signal for internal use by the bus device, data synchronizing logic that is adapted to synchronize source synchronous data that the bus device receives from the bus to the bus device's clock signal, and error detection and correction logic coupled to the data synchronizing logic. The error detection and correction logic is adapted to detect and correct errors associated with the data received from the bus concurrently while the data synchronizing logic synchronizes source synchronous data received from the bus to the clock signal.

Abstract: An error protection method for multimedia improves data recovery and channel throughput in channels which cause a random error and a burst error by using a rate compatible punctured convolutional code (RCPC) and an automatic retransmission on request (ARQ). In a process of decoding a plurality of packets of given information, the error protection method includes the steps of a) decoding one of the plurality of packets, b) decoding another packet when an error occurs during the decoding in step a), c) decoding a combination of the packets from steps a) and b) or a third packet when an error occurs in step b), and d) repeating step c) until the decoding error no longer occurs. The error protection method has the characteristics of both Type-1 and Type-2 ARQ methods. Therefore, one can obtain constant channel throughput in a channel containing burst errors, a channel containing random errors, and a channel in which the two types of error patterns coexist simultaneously.