Abstract: A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.

Abstract: Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency and/or the latency window of a memory device such that a data signal and a data strobe signal are received by the memory device within the latency window of the memory device.

Abstract: A method and/or apparatus are provided for protecting control information during broadcasts in a system where primary and second mobile broadcast control messages (PMBCM and SMBCM) are utilized. In order to protect the SMBCM, a first hash information instance is computed based on hashes for each a plurality of control data blocks for the SMBCM. The first hash information instance is appended to the PMBCM. Error-correcting code words are generated for the plurality of hashes for the plurality of control data blocks for the SMBCM. These error-correcting code words are appended to the control data blocks of the SMBCM. A receiver uses the first hash instance information in the PMBCM to determine if any control data blocks of the SMBCM are corrupt. If so, the error-correcting code words may be used to reconstruct the corrupted hash(es) for the control data block(s) in order to authenticate the remaining control data blocks.

Abstract: A receiver including a switch for switching output of a memory to one of paths according to content of the output. The memory stores information bits, first check bits and second check bits. The first check bits and second check bits are switched to one of the paths via a rate dematch apparatus to a decoder. The information bits are switched directly to the decoder.

Abstract: A method and device for indicating an uncorrectable data block. The method includes: if a forward error correction decoding fails, setting synchronization character of at least one of the corresponding data blocks to a first character; and performing line decoding on the data block with the set first character, and outputting decoded data. With the invention, indicating the uncorrectable data block Simple and effective to a line decoding module can be implemented in case of a failure of FEC decoding.

Abstract: A phase synchronization apparatus and corresponding method are disclosed. In one example the phase synchronization apparatus may include a sampling section, a phase-error detection section, a first computation section, a second computation section, and an interpolation section. The apparatus and method may also carry out phase synchronization that corrects the phases of received signals sampled at sampling periods asynchronous with symbol periods, by carrying out concurrent processing to generate a plurality of received symbols so that the phases can be synchronized at a higher speed.

Abstract: An FEC frame structuring device includes a multi-lane distributing unit that distributes a data frame to be transmitted to n lanes, FEC coding units each performs FEC coding of the distributed data frame independently for each of the n lanes to generate an FEC frame, a multiplexing unit that multiplexes the FEC frame from the FEC coding units by relating to m channels of an optical signal, a demultiplexing unit that demultiplexes the m channels of the received optical signal by relating to the n lanes, FEC decoding units each performs FEC decoding of the demultiplexed FEC frame independently for each of the n lanes, and a multi-lane synchronizing unit that synchronizes the n lanes with each other after the FEC decoding performed by the FEC decoding units to reconstruct the original data frame.

Abstract: A receiver includes a seed recovery module and a pseudo-random binary sequence generator. The seed recovery module is configured to receive a pseudo-random binary sequence and a signal including a seed value, recover the seed value from the signal using the pseudo-random binary sequence, and determine a likelihood that a bit of the seed value was recovered accurately. The pseudo-random binary sequence generator is configured to generate the pseudo-random binary sequence, and adjust the pseudo-random binary sequence based on the likelihood until the likelihood is greater than a threshold.

Abstract: FEC (Forward Error Correction) decoder with dynamic parameters. A novel means by which FEC parameters may be encoded into, and subsequently extracted from, a signal stream to allow for adaptive changing of any 1 or more operational parameters that govern communications across a communication channel. FEC parameters are encoded directly into a data frame such that the data frame is treated identical to all other data frames within the signal stream. When the data frame actually includes FEC parameters, it is characterized as a CP (Control Packet) type. For example, when decoding an MPEG stream, an MPEG block that includes FEC parameters, that MPEG block is characterized as a CP MPEG block. The means by which FEC parameters are encoded and extracted from the signal stream allows for much easier adaptive modification of the manner by which signal are encoded, modulated, and processed within a communication system.

Abstract: An automatic zero-crossing signal demodulation and classification device for rapidly identifying unknown modulation in a signal identifies unknown modulation in a signal, demodulates differential phase shift keying signals and automatically recognizes certain phase shift keying signals. This is accomplished by eliminating unknown term fc in differential phase estimation, introducing a symbol rate tracking mechanism, applying hysteresis nonlinearity to eliminate phase shaping effect and using weighted average to estimate phase difference. Better estimates are accomplished by using hysteretic nonlinear function to detect zero-crossing points in eliminating false detecting of zero-crossing points caused by additive noise, and calculating differential phase without directly using center frequency to simplify estimation process.

Abstract: A single frame format is employed by a millimeter wave communication system for single-carrier and OFDM signaling. A Golay-coded sequence in the start frame delimiter (SFD) field identifies the data transmission as single carrier or OFDM. Complementary Golay codes are employed in a channel estimation field to allow a perfect estimate of the multipath channel to be made. Marker codes generated from Golay codes are inserted periodically between slots for tracking and/or for reacquiring timing, frequency, and multipath channel estimates. The length of the marker codes may be adapted relative to the multipath delay spread.

Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.

Abstract: Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples.

Abstract: A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.

Abstract: A cache device is disposed on a connection path between a user computer executing a software application and a network. The application exchanges data with a further computer via the network. The cache device includes a cache memory and a processor. The cache device is configured to measure, by the processor, a first latency between the user computer and the further computer. The cache device is further configured to determine an acceptable latency range based on the latency and a requirement of the software application. The cache device is further configured to measure a second latency between the user computer and the further computer. The cache device is further configured to store, in the cache memory, a set of data transmitted from the user computer to the further computer, if the second latency is not within the acceptable latency range.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: The embodiments of the present invention provide a data coding method. In this data coding method, a synchronization header is added to the data that has undergone line coding and FEC coding, and then the data is framed and sent out. The embodiments of the present invention also provide the corresponding data decoding method, data coding apparatus, and data decoding apparatus. Because the redundant information for synchronization is added, the synchronization performance of the transmission system is ensured effectively even if the algorithm selected in the line coding provides low redundancy; moreover, the added synchronization header does not participate in the FEC coding calculation, thus preventing impact on the FEC coding gain.

Abstract: A lighting system controller is provided that is configured to automatically synchronize a lighting controller with a centralized configuration. In a particular example, this automatic synchronization activity may include modifying the configuration of the lighting controller to match configuration information stored locally on the lighting system controller. Conversely, this automatic synchronization activity may include modifying the locally stored configuration information to match the current configuration of the lighting controller. In some examples, the lighting system controller is configured to use cyclic redundancy checks when determining whether to modify configuration information.

Abstract: Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.

Abstract: A method for performing a Hybrid Automatic Repeat reQuest (HARQ) operation in a wireless mobile communication system that uses Frequency Division Duplex (FDD) or Time Division Duplex (TDD) frames each having a plurality of subframes for communication are provided, in which an HARQ timing including a transmission time of a data burst and a transmission time of an HARQ feedback, for DL HARQ is determined according to data burst assignment information transmitted in a #l DownLink (DL) subframe of a #i frame, and an HARQ operation is performed according to the determined HARQ timing. At least one frame index and at least one subframe index that represent the HARQ timing are determined by using l and i.

Abstract: In a mobile communication system, when a receiving condition is deteriorated to the extent that reception does not succeed even by means of combination after retransmission to the maximum number of retransmissions, a transmission rate is restricted by reducing radio frames assignable to new data, and by setting dedicated retransmission frames, to which retransmission data are assignable, over the maximum number of retransmissions for the reduced transmission rate, thereby enabling a greater number of retransmissions than the maximum number of retransmissions without an increase of a buffer size. By this, a combination gain through retransmission is improved and a retransmission failure rate is decreased.

Abstract: A method for transmitting data between first and second nodes in a network comprises (a) the first node sending a start packet to the second node, (b) the first node starting a first counter concurrently with sending the start packet, wherein the first counter starts counting, (c) the second node starting a timer in response to the start packet, (d) the second node starting a second counter in response to the timer running for a predetermined delay time, wherein the second counter starts counting, (e) the first node stopping the first counter and sending a stop packet in response to the first node determining that the number of accumulated first counts corresponds to the data (thereby transmitting the data solely as a time interval between the start and stop packets), the second node stopping the second counter in response to the stop packet (and receiving the transmitted data).

Abstract: An RDS compatible receiver has a demodulator which demodulates RDS data, a register which converts the demodulated RDS data to block data and outputs the block data, an offset generating unit which predicts and outputs an offset word of the block data based on values of a pattern match flag signal and a synchronization flag signal, an error correction processing unit which performs error correction of the block data using the predicted offset word, compares the number of error corrections with a predetermined correction threshold, determines whether the predicted offset word is right or not based on the comparison result, and outputs the pattern match flag signal based on the determination result, and a synchronization determining unit which detects whether or not the predicted offset word determined to be right matches a predetermined offset sequence pattern, determines whether RDS block synchronization is established or not, and outputs the synchronization flag signal based on the determination result.

Abstract: Transmission techniques are provided that improve service continuity and reduce interruptions in delivery of content that can be caused by transitions that occur when the User Equipment (UE) moves from one cell to the other, or when the delivery of content changes from a Point-to-Point (PTP) connection to a Point-to-Multipoint (PTM) connection in the same serving cell, and vice-versa. Such transmission techniques enable seamless delivery of content across cell borders and/or between different transmission schemes such as Point-to-Multipoint (PTM) and Point-to-Point (PIP). Mechanisms for adjusting different streams and for recovering content from each data block during such transitions are also provided so that data is not lost during a transition. In addition, mechanisms for realigning data during decoding at a receiving terminal are also provided.

Abstract: In operation, a transmitting device selects a synchronization pattern associated with the desired timeslot that is at least mutually exclusive from synchronization patterns associated with other timeslots on the same frequency in the system. Once selected, the transmitting device transmits a burst embedding the synchronization pattern that was selected, where appropriate. If the receiving device detects the synchronization pattern, it immediately synchronizes with the timeslot with confidence that it is synchronizing to the desired timeslot by using sets of synchronization patterns associated with the desired timeslot that are at least mutually exclusive from synchronization patterns associated with the other timeslots on the same frequency.

Abstract: A system and method for recovering the seed of a pseudo-random binary sequence (PRBS) using soft decisions is disclosed. In some implementations, a log-likelihood ratio is calculated to determine the certainty with which each bit in the seed has been recovered, and in some implementations, the value of the PRBS is used in the calculation of the log-likelihood ratio. In some implementations, a linear feedback shift register stores the log-likelihood ratio for each bit in the sequence.

Abstract: A method of recovering data in a line signal which is predicted to be subjected to repetitive noise impulses, the line signal comprising a series of data frames, the method comprising the steps of: predicting a group comprising one or more frames in said line signal which are expected to be corrupted by a noise signal; blanking said group of one or more frames which are predicted to be corrupted; determining the preceding and succeeding frames adjacent to said group; and including in each said group of one or more frames one or more parity blocks wherein if said noise signal deviates from its predicted timing interval or duration and corrupts the data carried in one or more of said frames adjacent to said group, the corrupted data is recovered using one or more of said parity blocks of said group of blanked frames and the other one of said adjacent frames.

Abstract: Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock.

Abstract: Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors.

Abstract: Various techniques are provided for synchronizing serial data signals received by electronic systems or devices such as programmable logic devices (PLDs). In one example, a method of synchronizing data includes receiving a serial data signal at a device. The serial data signal operates independently of the device. The method also includes oversampling the serial data signal to provide a plurality of samples distributed over bit periods of the serial data signal. The method further includes filtering the samples to correct errors in the samples. In addition, the method includes extracting a plurality of data bit values from the samples under the control of a clock signal associated with the device without adjusting a frequency of the clock signal. Each data bit value is associated with one of the bit periods of the serial data signal.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits including a pattern detection circuit having at least two data detector circuits each operable to receive the same series of data samples and to provide a first detected data output and a second detected data output, respectively. In addition, the data pattern detection circuit includes a result combining circuit that is operable to assert a pattern found output based at least in part on the first detected data output and the second detected data output.

Abstract: Provided is an optical disk reproduction apparatus capable of preventing information that is different from the original sub information from being subjected to error correction erroneously, and of stably reproducing the sub information. The optical disk reproduction apparatus (1) has an optical head (301) for reading a reproduction signal including main information and sub information based on a recording mark formed on an optical disk (300), a main information extraction unit (4) for extracting the main information from the reproduction signal, and a sub information extraction unit (2) for extracting the sub information from the reproduction signal.

Abstract: Methods and apparatuses for including synchronization data to be used for parallel processing in a block of data having error correcting code symbols. The block of data is encoded using an error correcting code. The resulting encoding includes three check symbols per 32 data symbols. At least one synchronization symbol corresponding to the data symbols is generated. The data symbols, the check symbols and the at least one synchronization symbol are combined. The combined data symbols, the check symbols and the at least one synchronization symbol are transmitted.

Abstract: A code encoding apparatus includes a delay circuit and a code generator. The delay circuit generates delayed information based on p-bit input information received in parallel. The delayed information is generated according to a clock. The code generator generates n·p-bit code based on at least one of the input information and the delayed information, where n is a rational number.

Abstract: A signal error determination and correction system is provided which comprises an error correction value calculation means which processes a predetermined segment of a signal to calculate an error correction value, and a signal correction means and prediction which applies the error correction value to at least part of the signal to correct the part of the signal. The invention further provides a method of signal error determination and correction.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.

Abstract: An advanced clock synchronization technique is adapted for use with a replication service in a data backup and recovery storage environment. The storage environment includes a plurality of source storage systems and target storage systems, wherein the source storage systems are illustratively embodied as source replication nodes. The advanced clock synchronization technique establishes a software-only, loosely-accurate global clock based on a timestamp and an associated error boundary. Notably, the timestamp and its error boundary are used as global clock information to enable synchronization (i.e., ordering of storage requests) among the source replication nodes and/or the target storage systems, thereby ensuring consistent replication of the storage requests on the target storage systems.

Abstract: An automatic zero-crossing signal demodulation and classification device for rapidly identifying an unknown modulation in a signal identifies an unknown modulation in a signal, demodulates differential phase shift keying signals and automatically recognizes certain phase shift keying signals. This is accomplished by eliminating the unknown term fc in differential phase estimation, introducing a symbol rate tracking mechanism, applying hysteresis nonlinearity to eliminate the phase shaping effect and using a weighted average to estimate the phase difference. Better estimates are accomplished by using the hysteretic nonlinear function to detect the zero-crossing points in eliminating the false detecting of the zero-crossing points caused by the additive noise, and calculating differential phase without directly using the center frequency to simplify the estimation process.

Abstract: A network component comprising a processor configured to implement a method that comprises applying a forward error correction (FEC) algorithm to a plurality of data blocks to generate a plurality of redundancy data, encapsulating an integer number of the data blocks and the redundancy data in an FEC codeword, and transmitting the FEC codeword, wherein the codeword is about evenly aligned with a transmission clock time quanta to have a transmission rate. A method comprising selecting an FEC algorithm that generates a plurality of redundancy data from a plurality of data blocks, selecting an EEC codeword that encapsulates an integer number of the data blocks, and selecting a synchronization pattern to add to the FEC codeword such that an integer number of the FEC codewords are evenly aligned with an integer number of transmission clock time quanta.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: A system and method for soft error recovery (SER) within a flip-flop. A first stage of the flip-flop receives an ungated input clock signal. A second stage of the flip-flop receives a gated input clock signal. The second stage may also store a prebuffered data output and one or more feedback storage values on separate nodes. The flip-flop has SER circuitry used to recover the prebuffered data output and any feedback storage value without requiring a transition of a clock signal.

Abstract: A PLI n-bit correction circuit extracts a core header (PLI) from a GFP frame with a fixed payload length; compares it with a predetermined expectation value for each bit; calculates the number of inconsistent bits therebetween; and outputs the predetermined expectation value, instead of the core header, when the number of inconsistent bits is equal to or less than n (n is a natural number); or directly outputs the core header when the number of inconsistent bits is greater than n. A decision on establishment of GFP Layer 2 synchronization is made based on the output of the PLI n-bit correction circuit, wherein predetermined processing is executed on a payload of a GFP frame dropping its core header when GFP Layer 2 synchronization is established, whilst the payload is not subjected to predetermined processing and discarded in the event of GFP Layer 2 desynchronization.

Abstract: A phase synchronization apparatus includes: a sampling section; a phase-error detection section; a first computation section; a second computation section; and an interpolation section.

Abstract: A MIMO system with Diversity processing is provided having Turbo Codes Decoders for computing orthogonal signals from multiple separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, trees or hills. The Turbo Codes Decoder with Diversity processing increases the signal to noise ratio (SNR) more than 6 dB which enables the Wireless system to deliver data rates from up to 200 Mbit/s. The invention provides several improved Turbo Codes Decoder methods and devices that provide a more suitable, practical and simpler method for implementation a Turbo Codes Decoder in ASIC (Application Specific Integrated Circuits) or DSP codes. A Turbo Codes Decoder block is provided to compute baseband signals from multiple different receiver paths. Several pipelined max-Log-MAP decoders are used for iterative decoding of received data. A Sliding Window of Block N data is used for pipeline operations.

Abstract: There is provided an apparatus for enabling recovery of missing information in a digital communication system. The apparatus includes a Forward Erasure Correction (FXC) encoder for computing FXC parity superpackets across information superpackets for subsequent recovery of any entire ones of the information superpackets that have been at least partially comprised due to synchronization loss.

Abstract: A receiving apparatus that can prevent beforehand that a portable recording medium is erroneously ejected during examination, and can prevent body cavity image data from being lost and the portable recording medium from being damaged is provided. When an ejection operation of the portable recording medium is detected (step S103: Yes) during a recording operation (step S101: Yes), a warning unit is operated before the portable recording medium is ejected to give a warning to a user so as not to perform the ejection operation (step S105). Accordingly, the portable recording medium can be prevented beforehand from being ejected during the recording operation, thereby preventing body cavity image data from being lost and the portable recording medium from being damaged.

Abstract: An apparatus and a method for synchronization in a channel card in a mobile communication system are provided. A channel card for synchronizing a Digital Signal Processing (DSP) modem and a system clock in a mobile communication system includes the DSP modem for sending a reference signal, informing of a start of a transmission, to a Field-Programmable Gate Array (FPGA) modem, and the FPGA modem for comparing a reception time of the reference signal with a Global Positioning System (GPS) timer, for recording a GPS timer value corresponding to a start point based on the comparison, and for sending to the DSP modem the recorded GPS timer value corresponding to the start point at a preset GPS timer reference time.

Abstract: Serial data communication methods and apparatus using a single line are provided. The data communication methods may include: setting a rising edge of a serial pulse signal so that a cycle of the serial pulse signal begins therefrom; setting a falling edge of the serial pulse signal within the cycle of the serial pulse signal according to a data value recorded within the cycle of the serial pulse signal; and transmitting a packet formed by combining at least one cycle of the serial pulse signal in series via a single line.

Abstract: A receiver including a switch for switching output of a memory to one of paths according to content of the output. The memory stores information bits, first check bits and second check bits. The first check bits and second check bits are switched to one of the paths via a rate dematch apparatus to a decoder. The information bits are switched directly to the decoder.