Abstract: In one embodiment, a reconfigurable adder has first and second five-bit non-reconfigurable adders and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first non-reconfigurable adder adds first and second messages to generate a first sum, and the second non-reconfigurable adder adds third and fourth messages to generate a second sum. In ten-bit mode, the first non-reconfigurable adder adds a first half of a first ten-bit message and a first half of a second ten-bit message to generate a first partial sum and a carry-over bit. The second non-reconfigurable adder adds a second half of the first ten-bit message, a second half of the second ten-bit message, and the carry-over bit to generate a second partial sum. A ten-bit sum is then generated by combining the first and second partial sums.

Abstract: Partial-parallel implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a selected number of cycles is performed during each of bit node processing and check node processing when performing error correction decoding of an LDPC coded signal. The number of cycles of each of bit node processing and check node processing need not be the same. At least one functional block, component, portion of hardware, or calculation can be used during both of the bit node processing and check node processing thereby conserving space with an efficient use of processing resources. At a minimum, a semi-parallel approach can be performed where 2 cycles are performed during each of bit node processing and check node processing. Alternatively, more than 2 cycles can be performed for each of bit node processing and check node processing.

Abstract: True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.

Abstract: This invention provides an iterative PCZZ data decoder that includes circuitry for utilizing all extrinsic information during iterative decoding by updating likelihood information for parity bits LPi, i=1, . . . , M during iterations. The extrinsic information for the parity bits is included in iterations by re-calculating soft values for parity bits LPi(k) for each iteration k. In one embodiment the parity bit soft values are re-calculated in a plurality of circuit blocks following Max-Log-APP (MLA) decoder blocks, based on soft values for data bits LDi(k). In another embodiment the parity bit soft values are re-calculated recursively within the plurality of MLA decoders. The decoder operates to control the convergence of the decoder by monitoring a soft value of one parity check symbol, e.g., L(k?1)[p(IM)], where p(IM) represents the last parity check bit in an I×M parity check array.

Abstract: A MAP detector system operates in a parallel mode for on-the-fly operations and in a serial mode for error recovery operations. In the parallel mode, a plurality of Viterbi operators process a block of input sampled data in parallel. In the serial mode a selected forward Viterbi operator and two associated reverse Viterbi operators process the entire block of data, in order, to produce soft decision data.

Abstract: A receiving method and apparatus for combining Hybrid Automatic Repeat Request (HARQ) data in a wireless communication system are provided. More particularly, a method and apparatus for increasing HARQ combining capability while effectively using a limited-sized memory are provided. The receiving method for combining the HARQ data includes predicting a maximum size of currently receivable data, converting HARQ data received from a transmitting end into Log Likelihood Ratio (LLR) information, determining whether the received HARQ data is retransmitted data, if the determination result shows that the HARQ data is not the retransmitted data, determining whether the converted LLR information is compressed according to the predicted maximum data size, and storing the converted LLR information in a memory according to the determination result on whether compression is necessary.

Abstract: According to an embodiment of the present invention provides the signal processing system. In the signal processing device that estimates information data from a reception signal by performing iterative processing between a demodulator that demodulates data of n(>m) bits obtained by modulating data of m bits into m bits and an ECC decoder and carrying out maximum a posteriori probability decoding, the device has a module that calculates an a posteriori value after demodulation by performing calculation of modulation data having a pattern estimated to have a high probability alone as modulation data to be decoded from all patterns of the modulation data to be decoded when effecting calculation of the a posteriori value after demodulation based on an a priori value fed back from the ECC decoder at the time of effecting modulation for a second or subsequent time.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first stage of decoding again using a second component code, and executing a second stage of decoding using the first component code. The first and second stages of decoding are used to generate the bit stream. Another method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of N stages for decoding the bits, the first stage using a first of M component codes, and simultaneously executing a plurality of the N stages of decoding, each of the plurality of N stages using a different one of the M component codes.

Abstract: Efficient methods for encoding and decoding Half-Weight codes are disclosed and similar high density codes are disclosed. The efficient methods require at most 3·(k?1)+h/2+1 XORs of symbols to calculate h Half-Weight symbols from k source symbols, where h is of the order of log(k).

Abstract: Apparatus and systems, as well as methods and articles, may operate to buffer a state of an iterative decoder operating on a codeword associated with a partially decoded forward error correction-encoded data block, and to restore the state to perform additional decoding iterations on the block during a period when the decoder is idle.

Abstract: A decoding circuit, is provided, comprising: a turbo decoder configured to receive a input systematic bit soft information values and input parity bit information values, and to generate output systematic bit soft information values and hard decoded bits according to a turbo decoding operation; and a parity bit soft information generation circuit configured to receive the input systematic bit soft information values, the input parity bit soft information values, and the output systematic bit soft information values; to determine initial forward metrics, initial backward metrics, and branch metrics as a function of the input parity bit soft information values and the output systematic bit soft information values; to determine output parity bit soft information values based on the branch metrics, the initial forward metrics, and the initial backward metrics; and to provide the output parity bit soft information values as a signal output.

Abstract: Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L? symbols, where L? is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.

Abstract: Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L? symbols, where L? is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.

Abstract: This invention generally relates to methods, apparatus and computer program code for decoding signals, and more particularly to trellis-based decoding using a variant of a BCJR procedure.

Abstract: A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.

Abstract: A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P.

Abstract: In order to create a highly-secured common key while a data error on a transmission path is corrected by an error correction code having remarkably high characteristics, in a quantum key distribution method of the invention, at first a communication apparatus on a reception side corrects the data error of reception data by a deterministic, stable-characteristics parity check matrix for a “Irregular-LDPC code.” The communication apparatus on the reception side and a communication apparatus on a transmission side discard a part of pieces of the common information according to public error correction information.

Abstract: A system corrects errors in a codeword. The system includes a channel that sorts reliability numbers of symbols in the codeword to create an ordered list of candidate erasure locations. The system also includes a generalized minimum distance decoder that iteratively processes the ordered list of candidate erasure locations and at least two syndromes of the codeword using a single-shot key equation solver to generate an error locator polynomial and an error evaluator polynomial. The generalized minimum distance decoder processes the least reliable candidate erasure locations first within the ordered list of candidate erasure locations.

Abstract: A method for decoding forward error correction (FEC) encoded data. A stream of units of FEC encoded bits are received, where the units are derived from a transmitted signal, where each unit represents a one-bit data value, and where each unit includes correctness bits. Preferably, the stream of units of FEC encoded bits are decoded by using the quality level of bits to perform soft-decision convolution decoding on the stream of units of FEC bits, where the soft-decision convolution decoding produces, for block decoding, a stream of symbols made up of bits. Subsequences of units that are prone to erroneous soft-decision convolution decoding are detected by determining, for the sub-sequences whether the distribution of quality bits indicate the units are below a threshold level of correctness, and by comparing characteristics of that distribution to a given set of characteristics predetermined to be prone to result in incorrect decoding.

Abstract: An apparatus and method for storing log likelihood ratios in an interleaved form comprising receiving a plurality of interleaved codewords; obtaining at least one log likelihood ratio (LLR) for the plurality of interleaved codewords; storing the at least one LLR in a memory; deinterleaving the plurality of interleaved codewords after the at least one LLR has been stored in the memory; and performing a bit decision of the deinterleaved codewords using the stored at least one LLR.

Abstract: A method for packet retransmission employing feedback information is disclosed. The method for packet retransmission employing feedback information comprises receiving reception acknowledgement information from a receiver after a transmitter transmits packets, the reception acknowledgement information representing channel status information and decoding success/failure of the packets; and changing a retransmission mode in accordance with the channel status information if the reception acknowledgement information represents decoding failure, and transmitting retransmission packets of the packets in accordance with the changed retransmission mode. Thus, it is possible to improve decoding probability of the receiver and increase efficiency of retransmission.

Abstract: Provided is an apparatus and method for receiving a signal in communication system. The apparatus and method includes generating a particular log-likelihood ratio (LLR) value by demapping an input signal according to a particular demapping scheme among a plurality of demapping schemes; performing a control operation of buffering the particular LLR value in a particular LLR sub-buffer for buffering an LLR value generated according to the particular demapping scheme among the plurality of LLR sub-buffers for buffering an LLR value generated according to each of the plurality of demapping schemes; and performing a control operation of reading an LLR value buffered in an LLR buffer including the plurality of LLR sub-buffers.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived form a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.

Abstract: Systems and methods are provided for implementing error identification and evaluation for a Reed-Solomon (RS) error-correction code (ECC) system. The BMA algorithm and/or list decoding may produce one or more error locator polynomials that are related to a decision-codeword. An accelerated Chien search can be used to more quickly evaluate the one or more error locator polynomial. If the accelerated Chien search identifies a valid error locator polynomial, a normal Chien search can be used to identify error locations, and Forney's algorithm or an equivalent technique can be used to evaluate the error values. A RS ECC decoder can include a computation circuit that evaluates an error locator polynomial or an error evaluator polynomial. The computation circuit can include computation components that receive the coefficients of the polynomials.

Abstract: A method includes estimating quadrature amplitude modulated QAM symbols in an LDPC encoded OFDM signal for transmission, performing channel estimation by training sequence to determine channel coefficients in reception of the LDPC encoded OFDM signal; and obtaining channel information detection and decoding of the LDPC encoded signal.

Abstract: An error of reception data is corrected using check matrixes for an “Irregular-LDPC code” that are definite and have stable characteristics and a part of shared information is discarded according to error correction information opened to the public. A parity check matrix corresponding to a specific coding rate is extracted from parity check matrix optimized at a coding rate in a desired range while a coding rate is lowered until the error of the reception data is completely corrected, an additional syndrome is generated, and error correction processing is repeatedly executed using the additional syndrome.

Abstract: Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L? symbols, where L? is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.

Abstract: Methods, apparatus, and systems are provided for error correction of a communication signal. A generalized multiple threshold scheme for iteratively decoding a received codeword may include generating a bit reliability based on a channel output reliability and an updated bit reliability from a previous decoding iteration, where the bit reliability is updated using a scaling factor and a comparison with a threshold. The threshold may have a plurality of threshold values during the iterative decoding.

Abstract: In accordance with one or more embodiments, a decoder may determine whether a lowest reliability value of a plurality of codeword bits that correspond to a particular output reliability value for a particular constraint node of a parity-check matrix is greater than a threshold value (e.g., an offset), and if so, selectively applies a modified min-sum approximation constraint node update with a reliability value modification (e.g., an offset or normalized min-sum approximation).

Abstract: The communication method includes the use of CRC codes for additional error correction in addition to the error detection capability. The method is for error detection and correction in a received message that includes N message bits and M Cyclic Redundancy Check (CRC) bits appended thereto. It is determined whether at least one bit error has occurred in the N message bits and M CRC bits of the received message based upon the M CRC bits, and when at least one bit error is determined, then K bits with a lowest quality metric are selected from the N message bits and M CRC bits. The bit error is corrected based upon possible bit error patterns and the selected K bits. Multiple bit errors may also be corrected.

Abstract: A transmitting device including an encoder for receiving an information bit stream in a frame and outputting an information symbol, a first parity symbol, and a second parity symbol by encoding each information bit. An interleaver sequentially arranges the information symbols and the first and second parity symbols by rows in an array with an integer number of rows and an integer number of columns. The interleaver further outputs a plurality of radio frames in a stream, by reading the symbols by going down each column, starting at the leftmost column and proceeding right. Each radio frame has a predetermined size. A demultiplexer demultiplexes the radio frames received from the interleaver into streams of information, first parity symbols, and second parity symbols. A rate matcher bypasses the stream of information symbols and punctures the streams of the first and second parity symbols for rate matching.

Abstract: Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.

Abstract: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2t states. In a representative embodiment, the Non-ISI Meta-Viterbi detector performs ?+2t2t add, compare, and select operations.

Abstract: A decoding device for a linear code on a ring R, the decoding device including: a plurality of storage media; and a processing section; wherein the processing section uses a part of reliability of all symbols at a previous time to update reliability of each symbol in a process of iterative decoding for increasing the reliability of each symbol, and further retains a part used to update retained reliability information and a part unused to update the retained reliability information on two separate storage media.

Abstract: Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding.

Abstract: A method for decoding forward error correction (FEC) encoded data. A stream of units of FEC encoded bits are received, where the units are derived from a transmitted signal, where each unit represents a one-bit data value, and where each unit includes correctness bits. Preferably, the stream of units of FEC encoded bits are decoded by using the quality level of bits to perform soft-decision convolution decoding on the stream of units of FEC bits, where the soft-decision convolution decoding produces, for block decoding, a stream of symbols made up of bits. Subsequences of units that are prone to erroneous soft-decision convolution decoding are detected by determining, for the sub-sequences whether the distribution of quality bits indicate the units are below a threshold level of correctness, and by comparing characteristics of that distribution to a given set of characteristics predetermined to be prone to result in incorrect decoding.

Abstract: A receiving device in a communication system that separates one frame of information bits into plural blocks, performs turbo encoding of the information bits of each block and transmits the result, and decodes the encoded information bits, where the receiving device includes plural decoders number of which is less than the number of blocks per frame. Each decoder performs a decoding process on encoded information bits of each block that have been expressed by likelihood, when a condition for stopping decoding is met, executes the decoding process of encoded information bits of another block for which decoding has not yet been performed. When the condition for stopping decoding has been met for all block before the number of times decoding has been performed for each decoder reaches a preset maximum number of repetitions, the decoding results of all the blocks are serially combined, an error detection process is executed, and when no error is detected, the decoding results are output.

Abstract: A communications channel is provided that includes an encoder that receives user data and generates corresponding encoded symbols for transmission through a channel medium. A channel detector has an input coupled to receive an output signal from the channel medium and a reliability information output which produces reliability information regarding logic states of detected bits in the output signal. A binary reliability value is provide for each of the detected bits. The channel further includes a decoder having a reliability information input coupled to the reliability information output of the channel detector to generate corresponding user data words as a function of the binary reliability value.

Abstract: The present invention provides a decoding apparatus for carrying out a decoding process on a ring-R linear code. The decoding apparatus includes coded-word holding means for acquiring a coded word with a code length reduced by omission of some symbols from the coded word and for holding the coded word; known-information addition means for attaching a reliability level of each of the symbols omitted from the coded word to reduce its code length as known symbols each having a known value to the coded word held by the coded-word holding means as known information; and repetitive decoding means for repeatedly carrying out a decoding process using belief propagation on the coded word including the known information attached to the coded word by the known-information addition means.

Abstract: A data decoder for decoding an asynchronous incoming data stream includes a bit engine receiving information describing the incoming data stream and generating a decoded data stream. In one embodiment, the bit engine includes a best-fit bit analysis block performing a pattern match operation for each data bit of the incoming data stream using the information describing the incoming data stream. The best-fit bit analysis block is operative to find a pattern of data bits that best matches the data bits in the incoming data stream. The bit engine further includes a missing bit insertion block to insert a dummy bit for each data bit where the best-fit bit analysis block cannot find a pattern match. An error correction block performs forward error correction on the decoded data stream, including the dummy bits, to generate a corrected outgoing data stream.

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract: In the field of coding/decoding in telecommunications networks, an error correcting decoder and associated decoding method are adapted to a mesh network. In particular, the system for the decoding of a plurality of coded copies of a data word includes at least a first decoding stage with: a plurality of soft decision decoders, each decoder being arranged for decoding a coded copy received as decoder input, and a graph-based decoder comprising a plurality of nodes, each node of said graph-based decoder receiving the soft output value from a corresponding decoder and the graph-based decoder determining a decoding value of said data word on the basis of said soft output values.

Abstract: A channel encoding apparatus using a parallel concatenated low density parity check (LDPC) code. A first LDPC encoder generates a first component LDPC code according to information bits received. An interleaver interleaves the information bits according to a predetermined interleaving rule. A second LDPC encoder generates a second component LDPC code according to the interleaved information bits. A controller performs a control operation such that the information bits, the first component LDPC code which is first parity bits corresponding to the information bits, and the second component LDPC code which is second parity bits corresponding to the information bits are combined according to a predetermined code rate.

Abstract: A baseband processor is provided having Turbo Codes Decoders with Diversity processing for computing baseband signals from multiple separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, trees or hills. The Turbo Codes Decoder with Diversity processing increases the signal to noise ratio (SNR) more than 6 dB which enables the 3rd Generation Wireless system to deliver data rates from up to 2 Mbit/s. The invention provides several improved Turbo Codes Decoder methods and devices that provide a more suitable, practical and simpler method for implementation a Turbo Codes Decoder in ASIC (Application Specific Integrated Circuits) or DSP codes. A plurality of parallel Turbo Codes Decoder blocks is provided to compute baseband signals from multiple different receiver paths. Several pipelined max-Log-MAP decoders are used for iterative decoding of received data.

Abstract: AMP (Accelerated Message Passing) decoder adapted for LDPC (Low Density Parity Check) codes. A novel approach is presented by which the LDPC coded signals may be decoded in a more efficient, faster, and less computationally intensive manner. Soft bit information, generated from decoding a higher layer square sub-matrix of a parity check matrix of the LDPC code, is employed to assist in the decoding of other square sub-matrices in subsequent layers. This approach allows the decoding of an LDPC code whose parity check matrix has column weight more than 1 (e.g., 2 or more), thereby allowing a much broader selection of LDPC codes to be employed in various communication systems. This approach also provides much improvement in terms of BER/BLER as a function of Eb/No (or SNR), and it can provide comparable (if not better) performance when performing significantly fewer (e.g., up to 50% fewer) decoding iterations that other approaches.

Abstract: A method is provided for combining two or more input sequences in a communications system to increase a repetition period of the input sequences in a resource-efficient manner. The method includes a receiving step, a mapping step, and a generating step. The receiving step involves receiving a first number sequence and a second number sequence, each expressed in a Galois field GF[pk]. The mapping step involves mapping the first and second number sequences to a Galois extension field GF[pk+1]. The generating step involves generating an output sequence by combining the first number sequence with the second number sequence utilizing a Galois field multiplication operation in the Galois extension field GF[pk+1]. p is a prime number. k is an integer. pk+1 defines a finite field size of the Galois extension field GF[pk+1].

Abstract: Systems and methods are disclosed for denoising for a finite input, general output channel. In one aspect, a system is provided for processing a noisy signal formed by a noise-introducing channel in response to an error correction coded input signal, the noisy signal having symbols of a general alphabet. The system comprises a denoiser and an error correction decoder. The denoiser generates reliability information corresponding to metasymbols in the noisy signal based on an estimate of the distribution of metasymbols in the input signal and upon symbol transition probabilities of symbols in the input signal being altered in a quantized signal. A portion of each metasymbol provides a context for a symbol of the metasymbol. The quantized signal includes symbols of a finite alphabet and is formed by quantizing the noisy signal. The error correction decoder performs error correction decoding on noisy signal using the reliability information generated by the denoiser.

Abstract: A sub-optimal method is disclosed for calculating the reliability values (soft values) for the bits of a multilevel signal. The log-likelihood values are approximated using only the dominant terms, so called max-log approximation, that is for each bit position only the two closest signal symbols of opposite bit value (S8, S6) are considered in the sum. The used modulation scheme is 16-QAM together with Gray-labelling. Two versions of approximation are proposed: one version consists of using the two distances between the received value and the two closest symbols of opposite bit value (?1 ?2 ). In order to simplify and speed up the calculation, the second version consists of using the distance between the two closest symbols (?3 ) to approximate the distance between the second closest symbol and the received value. Furthermore, precalculated results are stored in look-up tables to speed up the calculation.

Abstract: A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.

Abstract: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2t states. In a representative embodiment, the Non-ISI Meta-Viterbi detector performs ?+2t2t add, compare, and select operations.