Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

Abstract: To provide a receiving apparatus which is capable of demodulating information data from a multi-level modulated signal, which is generated by using a Y-00 protocol, without using high-performance component parts. In the receiving apparatus, the soft decision section 211 performs soft decision on the multi-level signal 22, in which a fixed decision level is used. A converted data identification section 214 performs logical decision on a value of the converted information data 25 in accordance with a highest-order bit of a multi-level code sequence 23 and a decision result 24 of the soft decision. A data reproduction section 215 performs an XOR operation between the converted information data 25 and a lowest-order bit of the multi-level code sequence 23, and outputs a resultant thereof as information data 23.

Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

Abstract: Systems, methods, and other embodiments associated with soft decoding for a quantized channel are described. According to one embodiment, an apparatus includes a soft decoder configured to decode a signal received from a quantized channel based, at least in part, on one or more log likelihood ratios (LLRs). The apparatus may also include a reliability memory configured to store one or more known LLRs, and a controller configured to repetitively and selectively provide the soft decoder with known LLRs chosen from the reliability memory, to control the soft decoder to decode the signal, and to selectively update the reliability memory upon determining that the soft decoder successfully decoded the signal.

Abstract: An encoding device and decoding device for improving an error floor while taking advantage of the features of a convolutional code capable of encoding/decoding an information sequence with an arbitrary length are disclosed. An error correction encoding section (110) is provided with an LDPC-CC encoder (111) and an LDPC-BC encoder (112). The LDPC-CC encoder (111) acquires an LDPC-CC code word sequence by applying LDPC-CC encoding to a transmission information sequence. The LDPC-BC encoder (112) acquires a parity sequence by applying LDPC-BC encoding to the LDPC-CC code word sequence. The LDPC-CC encoder (111) further applies the LDPC-CC encoding to the parity sequence.

Abstract: The invention relates to a method for transmitting a data block (104) via a message channel (130), said method having the following steps of: -subdividing the data block into at least one first sub-block (108) and one second sub-block (110), -generating first check data (114) for the first sub-block (108) and second check data (116) for the second sub-block (110), wherein a first transmission sub-block (118) is formed by the first sub-block and the first check data, and wherein a second transmission sub-block (120) is formed by the second sub-block and the second check data, -transmitting the first and second transmission sub-blocks in a transmission block (124) via the message channel, wherein the order of the bits to be transmitted in the transmission block is determined by a predefined scheme, wherein the scheme is designed in such a manner that one or more bits of the first transmission sub-block and one or more bits of the second transmission sub-block alternately follow one another.

Abstract: A method is proposed for determining an erasures vector associated with a data block to be decoded built out of received copies, and using levels of reliability of transmission associated with symbols contained in different copies of a same block of received pieces of data. Such a method advantageously makes reduces the error rate at output of a decoder by minimizing the operations to be performed to determine the erasures vector, marking the erasures and preventing the generation of an excessively large number of erasures (even when the transmission of certain received copies is unreliable) to have a number of erasures that does not exceed the correction capacity of the decoder.

Abstract: In a method of detecting an error pattern in a codeword transmitted across a noisy communication channel, a codeword is detected. A syndrome is then generated by applying a generator polynomial to the codeword. The generator polynomial is adapted to produce a distinct syndrome set for each of “L” (L>1) different error patterns potentially introduced in the codeword during transmission across the communication channel. A type of an error pattern within the codeword is detected based on the syndrome or a shifted version of the syndrome, and then a start position of the error pattern within the codeword.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: A method of decoding channel outputs using an iterative decoder to provide hard decisions on information bits includes activating each SISO decoder of the iterative decoder to provide soft-decisions associated with the information bits. The method also includes computing a fidelity estimate and stopping decoding based on the fidelity estimate.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: A decoding device for decoding LDPC (Low Density Parity Check) codes includes a message calculation unit for performing a variable node calculation for decoding the LPDC codes using a message to be supplied, or performing a check node calculation, and outputting the message to be obtained as a result of the calculation, a storing unit for storing the message, and a control unit for performing writing control for writing the message that the message calculation unit outputs in the storing unit, and readout control for reading out the same message to be employed for the calculation of the message calculation unit from the storing unit twice, and supplying these to the message calculation unit.

Abstract: A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected, if the bit error is an erroneous “0” value, the memory location containing the erroneous “0” value is reprogrammed to a “1” value. If the bit error is an erroneous “1,” value, the memory block data is saved in a non-volatile memory block, the configuration memory block containing the error is erased and reprogrammed using the corrected bit. If there is more than one error, an error flag is set. The user reads the status of the error flag through the JTAG port. If the error flag is set then a full reprogramming cycle is initiated.

Abstract: A method and system using the principle of generalized maximum likelihood estimation to resolve sample timing uncertainties that are associated with the decoding of communication signals. By using generalized maximum likelihood estimation, sample timing uncertainty can be resolved by taking multiple samples of the received signal within a symbol period and determining which sample best corresponds to the optimal sample timing. The sample which best corresponds to the optimal sample timing can be determined from a timing index which can be calculated from ambiguity indicators that are based on the samples of the received signal.

Abstract: A nonvolatile memory device comprises a memory cell array configured to store one or more bits per memory cell, a read and write circuit configured to access the memory cell array, a control logic component configured to control the read and write circuit to sequentially execute read operations of a selected memory cell at least twice to output a read data symbol, and an error correcting unit configured to correct an error in the read data symbol based on a pattern of the read data symbol to output an error-corrected symbol.

Abstract: Provided are a detector for a multi-level modulated signal and a detection method using the same, and an iterative receiver for a multi-level modulated signal and an iteratively receiving method using the same. The detector includes: a channel estimator estimating a channel response of each of a plurality of bits included in at least one received signal based on multi-level modulation; a hard decision unit, for each bit, selecting at least one of a plurality of bits remaining by excluding the bit and performing a hard decision based on a pre-probability of the selected bit; and a reliability calculator calculating reliability of each of all the bits in the received signal based on the received signal from which the hard-decided bit component is cancelled and the estimated channel response. Accordingly, the computation amount according to detection can be reduced without the degradation of performance.

Abstract: A receiver for use in performing open loop MIMO performs parallel interference cancellation to reduce interference caused by other spatial streams. Residual interference within an interference-cancelled signal is mitigated using MMSE filtering. The receiver processes received signals in multiple iterations. On each successive iteration, an MMSE filter assumes a lower interference power level than a previous iteration.

Abstract: In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.

Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. In another approach, the initial reliability metrics are based on multiple reads. Tables which store the reliability metrics and adjustments based on the sensed states can be prepared before decoding occurs.

Abstract: Techniques for generating soft values for parity bits in a convolutional decoding process are disclosed. An exemplary method comprises, for each of at least one iteration in at least one soft-input soft-output decoder, calculating intermediate probability values for each possible transition between a first plurality of candidate decoder states at a first time and a second plurality of candidate decoder states at a second time. Two or more partial sums are then computed from the intermediate probability values, wherein the partial sums correspond to possible combinations of two or more systematic bits, two or more parity bits, or at least one systematic bit and at least one parity bit. Soft values, such as log-likelihood values, are then estimated for each of at least one systematic bit and at least one parity bit of the received communications data corresponding to the interval between the first and second times, based on the partial sums.

Abstract: Certain aspects of the present disclosure relate to a method and an apparatus for unified iterative demodulation-decoding that can be employed in both multiple-input multiple-output (MIMO) and non-MIMO wireless systems.

Abstract: An error correction method for a memory device is disclosed. A base reading of a memory device is performed, and an error correction code (ECC) decoding is performed on the data read out of the memory device. The memory device is further read when the result of the ECC decoding is not strongly determined, wherein extra information acquired in the further reading of the memory device is used in the ECC decoding.

Abstract: Disclosed is a new solution to maximize throughput in wireless networks even when unpredictable and time-varying error exist. The present invention adapts to take an advantage of a network coding at a symbol level in multi-channel wireless networks. By operating the network coding at the symbol level and using soft decision values, the present invention is able to exploit both time and cooperative diversity in realistic multi-channel wireless networks, to adapt to time-varying and bursty channel errors, and to efficiently collect as many correct symbols as possible at the receiver.

Abstract: An RSSI detection unit detects a level of a received signal. An error detection unit performs error detection of the received signal. An error correction control unit causes an error correction unit to perform error correction of the received signal only when the error detection unit detects an error and the level of the received signal detected by the RSSI detection unit is not lower than a predetermined value.

Abstract: In an error correction method, a codeword is transmitted through a noisy communication channel and detected by a receiving device. An error detection code is then applied to the detected codeword to generate a syndrome. Where the syndrome is not all zero, the codeword is determined to contain some error. Accordingly, the method computes a set of potential error start positions for a plurality of error events based on a syndrome value corresponding to the syndrome. Next, a confidence value is computed for each of the plurality of error events at each of the potential error start positions in the refined set, and finally, a most likely error event in the detected codeword is corrected based on an error event and corresponding potential error start position having the highest confidence value.

Abstract: Multiple channels of received data are processed by a multiple channel demodulation and error correction decoding engine. The statistical uncertainty of processing channels with an iterative decoder are averaged across all the channels to reduce the total processing power required of the decoding engine compared to processing each channel with a separate engine. A set of input buffers holds blocks of data for each channel needing decoding. A quality measure is computed on each input block to set the priority and iteration allocation of decoding in the common decoder. The input RF signal is digitized by a broadband tuner that processes some or all of the channels to feed the multiple channel demodulator and decoder. Multiple decoded video data streams are output.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output.

Abstract: A system and method for achieving higher data rates in physical layer devices. Costs imposed by large data rate increases represented by generational increases in Ethernet standards activities are avoided through physical layer device modifications that enable marginal increases in data bandwidth. Building-block reuse can be promoted through the selective use of clocking rate increase, increase in coding efficiency, and bit reuse.

Abstract: A data receiving circuit includes: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-processed; a memory configured to be shared by the first de-interleave circuit and the second de-interleave circuit and store respective hard decision information and respective soft decision information of the first data and the second data; and a memory control circuit configured to vary a first through fourth number of bits stored in the memory, the first number corresponding to the hard decision information of the first data, the second number corresponding to the soft decision information of the first data, the third number corresponding to the hard decision information of the second data, the fourth number corresponding to the soft decision information of the second data.

Abstract: A method and system of receiving data with enhanced error correction is disclosed. One or more reliability bits associated with each received data bit are generated, for example, by a soft-decision slicer. Subsequently, one or more errors of the data bits may be corrected according to the associated reliability bit(s).

Abstract: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2t states. In a representative embodiment, the overall implementation complexity of the Non-ISI Meta-Viterbi detector is bounded by no more than ?+(?)2t2t operations, wherein t represents the number of parity bits used in a codeword and ? represents codeword length in bits.

Abstract: Various embodiments of the present invention provide systems and methods for out of order memory management. For example, a method for out of order data processing is disclosed. The method includes providing an out of order codeword memory circuit that includes a number of codeword memory locations in a codeword memory area and the same number of index values in an index area. Each of the index values corresponds to a respective one of the codeword memory locations. The methods further include receiving a data set; storing the data set to one of the codeword memory locations; receiving an indication that the data set stored in the one of the codeword memory locations has completed processing; and grouping an index value corresponding to the one of the codeword memory locations with one or more other index values corresponding to unused codeword memory locations.

Abstract: An apparatus and method are provided for normalizing input soft metric to a channel decoder in a wireless communication system. A demapper generates soft metric using an in-phase component (Xk) and a quadrature component (Yk) of a received modulated symbol (Rk), a channel fading coefficient (gk) and a constant value (c) defined by a modulation order of the received modulated symbol. A normalizer receives the soft metric, computes a normalized log likelihood ratio (LLR) by multiplying the soft metric by a ratio of the constant value to a noise variance value, transforms the normalized LLR into a desired range and a desired number of bits, and outputs an input LLR of the channel decoder.

Abstract: A decoding circuit and method for improving error correction capability using a stuffing byte, in which in the decoding method, an input data packet is decoded. When it is determined that error correction is impossible based on a decoding result, a stuffing byte section is detected in the input data packet. A level value of data in the stuffing byte section is converted into a stuffing byte level value. A data packet having the converted level value is decoded and output. The decoding circuit includes a decoder decoding an input data packet and a control block detecting a stuffing byte section in the input data packet, converting the input data packet, and decoding a converted data packet when the decoder fails in error correction of the input data packet.

Abstract: A network for channel coding permutation and de-permutation comprises: a first side and a second side, each of which has at least one terminal. The network further comprises: two or more columns of nodes located between the first and second sides. A first column of the columns interfaces the first side, and a second column of the columns interfaces the second side. Each of the columns comprises at least one node. Each node of the columns is connected to a first number of nodes of each of adjacent columns next to the columns. The first number is identical for all the nodes in the network. The nodes which are selected as switches are concurrently controlled to perform switching operations.

Abstract: A method for signal reception in a Multiple-Input-Multiple-Output (MIMO) communication system is provided. The method enhances the efficiency of signal reception in the MIMO system and simplifies the algorithms of signal reception and soft decoding metrics generation. In other words, soft decisions are generated according to correlations between metrics corresponding to least reliable bits based on MMSE linear estimation and noise variance estimation is provided to improve performance when an error is generated in channel matrix H estimation.

Abstract: A method and apparatus is provided for receiving data in a receiver of a communication system. In the receiver, a first calculator calculates a Log Likelihood Ratio (LLR) value of data transmitted from a transmitter, a decoder performs iterative decoding on the transmitted data using the LLR value calculated by the first calculator. A second calculator determines whether there is an error in the decoded data by calculating an error of the data decoded by the decoder. A storage stores an LLR value of the decoded data according to the determination result of the second calculator. An adder adds up the LLR value calculated by the first calculator and the LLR value stored in the storage.

Abstract: An embodiment of a decoder comprises processing elements operating on associative processing. The processing elements may comprise a logic and memory element. Each row of the decoder comprises one or more associative processing elements controlled by a row control element to determine the two minimum values. Each column comprises one or more associative processing elements, an input processing element, and a column control element to determine hard decision bits. The usage of processing elements to construct a decoder may reduce the gate count and decrease the interconnects used to couple the elements.

Abstract: An optical receiving apparatus includes: an A/D converting circuit; a received-signal demodulating circuit that demodulates a received digital signal from the A/D converting circuit into an m-bit received signal; a soft-decision-data generating circuit that generates n-bit (n?m) soft-decision data based on the m-bit received signal; and an error correcting circuit that performs error correction based on the n-bit soft-decision data and outputs an error-corrected received signal. The soft-decision-data generating circuit generates soft-decision data of n bits (n=p+1) that corresponds to a determination result according to 2n?1 soft-decision thresholds, by using an MSB of the m-bit received signal as hard-decision data, and by using, as reliability information, a result of comparison between a plurality of bits (k bits, where k?m) on an MSB side of the m-bit received signal and a fixed threshold, or p bits (p?m?k) selected from (m?k) bits on an LSB side of the m-bit received signal.

Abstract: An error correcting device in an optical communication system that transmits a transmission frame formed by adding an overhead and an error correction code to information data uses a concatenated code or an iterated code of at least two error correction codes as an outer code and an error correction code for soft-decision decoding as an inner code.

Abstract: Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.

Abstract: In a method for error handling in transmission of a datum over a communications system, at least two data words consisting of bits are generated for the datum in accordance with a predefined coding rule, and one of the generated data words is selected taking into consideration a running digital sum formed over the corresponding data word, and the running digital sum of the selected data word is used for the formation of a first running digital sum. The selected data word is converted into a code data word, and a bit of the data word is in each case assigned a two-bit string with two different single-bit values. The code data word and the first running digital sum are transmitted. The received code data word is examined to ascertain whether an erroneous two-bit string exists, in which case the error is corrected using the first running digital sum.

Abstract: An exemplary storage controller for controlling data access of a storage device includes a control circuit and a soft decoder. The control circuit is utilized for reading data from the storage device to obtain readout data. The soft decoder is coupled to the control circuit, and utilized for performing a soft decoding operation upon the readout data to generate decoded data. The soft decoder may be a low density parity check (LDPC) decoder, a block turbo code (BTC) decoder, or a convolutional turbo code (CTC) decoder. The storage device may be a flash memory device.

Abstract: A decoder architecture and method for processing codewords are provided. In one implementation, the decoder architecture includes an input buffer configured to receive and store one or more codewords to be processed, and a decoder configured to receive codewords one at a time from the input buffer. The decoder processes each codeword only for a minimum amount of time for the codeword to become error free. The decoder architecture further includes an input buffer monitor and supply regulator configured to change a voltage supply to the decoder responsive to an average amount of time or each codeword to become error free.

Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.

Abstract: A distortion compensation system and method may be used to compensate for data pattern dependent signal distortion in a signal received in a coherent optical signal receiver. In general, the distortion compensation system and method compares a received signal field with stored distorted signal waveforms associated with known data patterns and selects a compensation value associated with the distorted signal waveform that corresponds most closely with the received signal field. The distortion compensation system and method compensates the received signal using the selected compensation value and thus mitigates the effects of data pattern dependent signal distortion.

Abstract: According to an embodiment of the invention, a method and system is disclosed for determining log-likelihood ratios for a coded set of individual bits (40) of a quadrature amplitude modulation (QAM) codeword. In the method at most two constant values (33,35) may be determined to perform a set of predetermined functions, the output of each of function is based on the constant values and at least one received component corresponding to the codeword, to determine log-likelihood ratios (37) for each individual bit of the set of individual bits of the codeword. The QAM codeword may correspond to at least a portion of a signal of a wireless device, such as a mobile third-generation device operating according to a Wideband Code-Division Multiple Access (WCDMA) standard.

Abstract: An iterative error correcting decoder is provided. In one implementation, the iterative error correcting decoder includes an equality constraint node and a parity check node, the parity check node. The parity check node includes parity logic configured to receive input data bits from the equality constraint node and determine a first minimum value and a second minimum value associated with the input data bits using a MinSum algorithm. An enhancement function is performed on the first minimum value and the second minimum value. The enhancement function compares each of the first minimum value and the second minimum value with a first pre-determined constant value, and responsive to the first minimum value and the second minimum value being smaller than the first pre-determined constant value, the enhancement function passes the first minimum value and the second minimum value without any changes as output of the MinSum algorithm.

Abstract: Method and a receiver in a communication system for receiving a transport block. The transport block comprises code blocks, each of the code blocks includes an error detection code and an error correction code. Reliability metrics are determined using an input generated during processing of the code blocks after the transport block is received. Each of the reliability metrics corresponds to each of the code blocks. A code block reorderer reorders the code blocks in an order based on the reliability metrics and a selection criterion. A decoder decodes each of the code blocks using the error correction code in the order. A verifier verifies each of the decoded code blocks using the error detection code.

Abstract: A method and device for performing forward error (FEC) correction avoidance based upon predicted block code reliability in a communications device is provided. An avoidance unit comprising a metric computation unit and a decision unit generates a reliability metric based upon a received code block. The reliability metric is compared to a reliability threshold, and the forward error correction decoder in the communications device is disabled if the metric is below or equal to the threshold.