Abstract: A receiver comprises multiple receiving antennas configured to receive bitstreams transmitted from multiple transmission antennas; a bitstream candidate estimator configured to estimate a prescribed number of bitstream candidates among possible combinations of the received bitstreams and to calculate reliability information for each of the candidates; a bit-based estimator configured to produce a bit-based estimation result for each bit of the transmitted bitstreams based on the estimated candidates and the associated reliability information, the bit-based estimation result being adjusted by an adjusting criterion determined by the reliability information; and a decoder configured to decode the transmitted bitstreams based on the adjusted bit-based estimation result.

Abstract: An apparatus and method for transmitting and receiving symbols in a mobile communication system, in which a multiplexer and burst mapper divides each of first and second group data blocks into a plurality of sub-blocks, the symbols including the first group data block and the second group data block, the second group data block having a different priority level from the first group data block, and maps a combination of one of the first group data sub-blocks and one of the second group data sub-blocks to each burst. A modulator maps a bit of the first group data sub-block and a bit of the second group data sub-block to a symbol according to a bit reliability pattern of modulation symbols in each burst.

Abstract: A satellite communications system comprises a transmitting ground station, including a transmitter and a receiver, a satellite transponder and a receiving ground station. The transmitter transmits an uplink signal to the satellite transponder, which broadcasts the received uplink signal as a downlink signal to the receiving ground station. The transmitting ground station monitors the downlink signal through the receiver and calculates log-likelihood ratios (LLRs) as a function of the monitored downlink signal. These LLRs are illustratively stored in a look-up table, which are then transmitted to the receiving ground station for use in recovering data from a received data signal.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first stage of decoding again using a second component code, and executing a second stage of decoding using the first component code. The first and second stages of decoding are used to generate the bit stream.

Abstract: A method of encoding information symbols comprises a step in which a word v, orthogonal to a matrix H, the element H?? of which is equal to the value taken by some monomial h?=YjXi at the point P? of some locating set, is associated with every block of k information symbols belonging to a Galois field Fq. The method chooses the set of monomials h? so as to define codes which can be decoded with an algorithm by aggregates of low complexity, and which provides a very good error correction capability, in particular for channels in which the errors tend to occur in bursts. Devices and apparatuses adapted to implement this method are also disclosed.

Abstract: A method of distributing a quantum key through a quantum communication path includes: a transmitting device and a receiving device generating a parity check matrix separately; the transmitting device notifying the receiving device of error correction information generated based on the parity check matrix and transmission data, through a public communication path; the receiving device correcting an error in reception data based on the error correction information. The above processing is repeatedly executed until the error is successfully corrected.

Abstract: According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value.

Abstract: Disclosed is an apparatus and method for erasure detection and soft-decision decoding in a cellular system receiver. In the present invention, a complex channel gain and a noise variance of a received symbol from a cellular system transmitter are estimated, and an erasure symbol (a symbol with high power interference) is detected by comparing a threshold value according to the estimated complex channel gain or noise variance with power of the received symbol. Log-likelihood ratios corresponding to constituent bits of the detected erasure symbols are allowed to be 0, and the log-likelihood ratios of the constituent bits of the other received symbols are calculated. A soft-decision decoding operation of received bits is performed with the calculated log-likelihood ratios.

Abstract: Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

Abstract: Performing soft error correction includes receiving a word at a soft correction engine (310a, 310b) capable of operating in more than one correction mode, identifying soft bit positions within the word, and automatically generating a number of possible results (370) for the received word using combinations of the soft bit positions and more than one correction mode. The soft correction engine (310a, 310b) may include a Golay engine.

Abstract: Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. In another approach, the initial reliability metrics are based on multiple reads. Tables which store the reliability metrics and adjustments based on the sensed states can be prepared before decoding occurs.

Abstract: When received data is decoded, a CPU stores a value “1”, which is included in a vector obtained by multiplying the received data by a parity check matrix, as the number of parity errors and also stores hard-decision result information corresponding to the number of parity errors in an output candidate information storage area. If the CPU determines that the received data is uncorrectable after the received data is decoded a given number of times, it reads hard-decision result information corresponding to the smallest number of parity errors, which are included in the number of parity errors stored in the output candidate information storage area and outputs it as a decoding result.

Abstract: Systems and methods are disclosed for denoising for a finite input, general output channel. In one aspect, a system is provided for processing a noisy signal formed by a noise-introducing channel in response to an error correction coded input signal, the noisy signal having symbols of a general alphabet. The system comprises a denoiser and an error correction decoder. The denoiser generates reliability information corresponding to metasymbols in the noisy signal based on an estimate of the distribution of metasymbols in the input signal and upon symbol transition probabilities of symbols in the input signal being altered in a quantized signal. A portion of each metasymbol provides a context for a symbol of the metasymbol. The quantized signal includes symbols of a finite alphabet and is formed by quantizing the noisy signal. The error correction decoder performs error correction decoding on noisy signal using the reliability information generated by the denoiser.

Abstract: Data communication over a block-coherent channel in a communication system is described. Low-complexity demodulation techniques that allow good performance are described. A dwell, e.g., a set of block coherent symbols transmitted including a known symbol, e.g., a pseudo pilot symbol, are received, demodulated and decoded by a joint decoder/demodulator employing soft inputs, soft outputs, and interleaving of messages. Low-complexity SISO demodulator is suitable for processing pseudo-pilot modulated information corresponding to each of one or more dwells. The low-complexity method achieves good performance when turbo equalization is used. Some decoding and demodulation embodiments include independent phase estimates and updated independent phase estimates following the extrinsic principle to generate soft symbol values and soft bits.

Abstract: A data recording and reproducing system adds a first error correcting code to input data to generate a first code block, encodes the first code block with a second error correcting code to generate a second code block, interleaves the second code block to generate a recording block, and records and reproduces the recording block via a partial response channel including a recording medium. An output signal from the partial response channel, and thus the second code block, is decoded; the decoded data and the reliability of the decoded data is determined, based on likelihood information obtained during iterative decoding; and the first error correcting code is decoded. The decoded data and the reliability information are supplied to the first error correcting code decoder.

Abstract: A modulation and coding scheme for a communication system is based on use of nonsystematic repeat-accumulate codes for encoding channel information for transmission, and for employing a combined detection and decoding arrangement to decode the coded channel information. The nonsystematic repeat-accumulate codes may be generated by an encoder at a transmitter and decoded by a composite detector/decoder arrangement at a receiver.

Abstract: A multi-rate encoder and decoder system is disclosed. The multi-rate encoder and decoder system is capable of operating with a mother code or a subset code of the mother code and includes a trellis encoder having a set of inputs and a set of outputs corresponding to the mother code and a select unit capable of removing the set of inputs into the trellis encoder that correspond to the mother code but not the subset code prior to encoding. The multi-rate encoder and decoder system further includes a decoder having a set of decoder inputs and a set of decoder outputs corresponding to the mother code and a decoder select unit capable of ignoring transitions in the trellis code produced by the encoder that belong to the mother code but not to the subset code.

Abstract: The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratio's in a single operation, as opposed to the two pass traditionally associated with the Tanner Graph's. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISO's. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.

Abstract: A method and apparatus for soft output decoding of multi-input multi-output (MIMO) channels in order to improve throughput performance is provided. In particular, a low-cost alternative to exhaustive brute-force maximum-likelihood search by using a variant of list decoding that exploits pre-coder linearity to reduce the computational complexity in generating a list of candidate codewords for decoding is disclosed.

Abstract: A system and method for Reverse Error Correction Coding. The system includes a Constraint encoder, an Error Correction Code encoder, and a uniform interleaver. The Constraint encoder receives a source data stream and generates a first intermediate encoded data stream satisfying a first predetermined timing data constraint. The Error Correction Code encoder receives the first intermediate encoded data stream and generates a second intermediate encoded data stream having one or more Error Correction Code based elements. The uniform interleaver receives the second intermediate encoded data stream and generates a channel data stream having the one or more Error Correction Code based elements and satisfying a second predetermined timing data constraint.

Abstract: Efficient design to implement LDPC decoder. The efficient design presented herein provides for a solution that is much easier, smaller, and has less complexity than other possible solutions. The use of a ping-pong memory structure (or pseudo-dual port memory structure) in conjunction with a metric generator near the decoder's front end allows parallel bit/check node processing. An intelligently operating barrel shifter operates with a message passing memory that is operable to store updated edges messages with respect to check nodes as well as updated edges messages with respect to bit nodes. Using an efficient addressing scheme allows the same memory structure to store the two types of edges messages with respect to bit nodes: (1) corresponding to information bits and (2) corresponding to parity bits. In addition, an intelligently designed hardware macro block may be instantiated a number of times into the decoder design to support ever greater design efficiency.

Abstract: Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. The decoding can be performed on signals whose various symbols have been mapped to multiple modulations (constellations and mappings) according to a rate control sequence. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding to generate the signal that is subsequently decoded. Either one or both of an encoder that generates the signal and a decoder that decodes the signal may adaptively select a new rate control sequence based on operating conditions of the communication system, such as a change in signal to noise ratio (SNR).

Abstract: In a communication system a transmission-end input data flow with serially successive data is transmitted via a time-variant transmission channel. The transmission-end input data flow is divided into individual words. An a-priori reliability value is determined for each position of a transmittal data block by transmission-end modulation methods and coding methods, and the words of the input data flow are associated with corresponding positions of the transmittal data block according to the a-priori reliability values, and transmitted. An a-posteriori reliability value is formed on the receiving end for each word of the transmittal data block. The words having an a-posteriori reliability value falling below a pre-determined minimum value are re-requested and re-transmitted by acknowledgement of the corresponding positions.

Abstract: A system for processing data packets comprising a plurality of data processing blocks and a controller, which allows the configuration parameters used in processing the data blocks to be updated in each data processing blocks at the data packet boundary. The present invention involves a system that utilizes a handshaking method for synchronously exchanging data between data processing blocks, wherein the data processing blocks update configuration parameters based on the type of networking standard used. Each data processing block identifies a first data block in the data packet and transmits a first data signal along with a first output data block of the data packet, wherein the block updates the configuration parameters from the controller only when the first data signal is present. In this manner, the first data signal, which is indicative of the data packet boundary, is propagated along the sequence of data processing blocks.

Abstract: A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.

Abstract: Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.

Abstract: Performing soft error correction includes receiving a word at a soft correction engine capable of operating in more than one correction mode, identifying soft bit positions within the word, and automatically generating a number of possible results for the received word using combinations of the soft bit positions and the more than one correction modes. The soft correction engine may include a Golay engine.

Abstract: A low-density parity-check (LDPC) decoder (304) has a memory (308), and a processor (306). The processor is programmed to initialize (202) the LDPC decoder, calculate (204) a probability for each check node, calculate (206) a probability for each bit node, calculate soft decisions, update the bit nodes according to the calculated soft decisions, calculate (208) values from the calculated soft decisions, perform (210) a parity check on the calculated values, update (218) log-likelihood ratios (LLRs) if a bit error is detected in the calculated values, update the bit nodes according to the updated LLRs, and repeat the foregoing post initialization steps.

Abstract: An approach is provided for transmitting messages using low density parity check (LDPC) codes. Input messages are encoded according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The LDPC codes are transmitted over a radio communication system (e.g., satellite network), wherein a receiver communicating over the radio communication system is configured to iteratively decode the received LDPC codes according to a signal constellation associated with the LDPC codes. The receiver is configured to iteratively regenerating signal constellation bit metrics after one or more decoding iterations.

Abstract: A system and method for soft decision forward error correction (FEC) decoding may be used to determine a possible error in a differential detection signal, for example, in a DPSK system. The system and method uses the constructive and destructive signals from a demodulator to provide an error locating signal. Using the error locating signal, the system and method converts the differential detection signal into a soft decision signal including multi-level soft values.

Abstract: A decoding device for decoding a product code and a decoding method using the same are provided. The decoding device comprises an erasure flag processor, a decoder and a confidence flag processor. The erasure flag processor determines to set a particular value or a non-particular value for each erasure flag according to a plurality of the confidence flags, wherein each symbol has a confidence flag and an erasure flag correspondingly and each confidence flag has a confidence flag value. The decoder is coupled to the erasure flag processor to correct the symbols according to the erasure flags and outputs the corrected symbols. The confidence flag processor is coupled to both the erasure flag processor and the decoder to reset the confidence flag values of the confidence flags according to the erasure flags and the corrected symbols.

Abstract: One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway. The system also receives a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet. As the data packet is received, the system performs an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet. Finally, the system compares the generated per-bit error-information with the corresponding per-bit error information in the time signature t to determine if there exists an error.

Abstract: A method of decoding is provided comprising processing iterations. In each processing iteration, there is a first Max-Log-MAP decoding operation giving rise to a systematic error due to the Max-Log approximation, and a first weighting operation to weight extrinsic information from the first decoding operation to be applied as a priori information to the second Max-Log-MAP decoding operation. This is followed by a second Max-Log-MAP decoding operation, also giving rise to a systematic error due to the Max-Log approximation, and a second weighting operation to weight extrinsic information from the second decoding to be applied as a priori information to the first Max-Log-MAP decoding of the next iteration. The weights are applied to compensate for the systematic error due to the Max-Log approximation made in the last Max-Log-MAP decoding operation.

Abstract: At the receiver in a wireless communications system, the likelihood of a false CRC pass that can occur when a weak received signal produces an all ZERO output from a convolutional or a turbo decoder is minimized. To prevent an all ZERO output, a convolutional decoder selects from among those determined equally most likely transmitted sequences of bits in a data block one that has a weight greater than the one having the minimum weight. A turbo decoder selects a ONE rather than a ZERO as the value of a transmitted bit in a data block when for that bit a bit value of a ZERO and a ONE are determined to be equally likely.

Abstract: A codeword is decoded by receiving a codeword representation that includes a plurality of soft bits and iteratively updating the soft bits. Whether each soft bit participates in at least some iterations is determined according to a selection criterion, e.g., probabilistically, or according to iteration number, or according to the soft bit's iteration history. For example, each soft bit might participate in some or all iterations with a probability that is a function of both the iteration number and a reliability measure of that soft bit. Preferably, the iterations are LDPC iterations in which variable nodes are addressed sequentially for exchanging messages with corresponding check nodes.

Abstract: A technique to reduce false error detection in microprocessors by tracking instructions neutral to errors. As an instruction is decoded, an anti-pi bit is tagged to the decoded instruction. When a parity error is detected, an instruction queue first checks if the anti-pi bit is set. If the anti-pi bit is set, then instruction is neutral to errors, and the pi bit need not be set. Prefetch, branch predict hint and NOP are types of instructions that are neutral to errors.

Abstract: Fast min*? (min-star-minus) or max*? (max-star-minus) circuit in LDPC (Low Density Parity Check) decoder. A novel and efficient approach by which certain of the calculations required to perform check node processing within various types of decoders is presented. The functionality and architectures presented herein are applicable to LDPC decoders and may also be employed within other types of decoders that are operable to decode other types of coded signals as well. The parallel and sometimes simultaneous calculation and determination of certain parts of the overall resultant of the max*? and/or min*? processing allows for very fast operation when compared to prior art approaches.

Abstract: A method of decoding a turbo product code (TPC) code word comprises performing a cyclic redundancy check (CRC) on each of a plurality of code blocks of the TPC code word. The bits of code blocks of the TPC code word which pass the CRC are assigned an artificially high probability confidence measure, such as an artificially high log-likelihood ratio. Assigning these bits an artificially high probability confidence measure allows an iterative process, between a soft decision algorithm and a TPC decoder, to be less complex and to converge on a correct decoding solution more quickly. Apparatus for implementing the method are also provided.

Abstract: A soft decision value correction method can detect interference occurring in a desired wave and correct a soft decision value where a received power difference between the desired wave and an interference wave is small. A receiver and a program capable of performing the soft decision value correction method are provided. In the receiver an EVM calculator sets a detection distance for a primary modulation symbol of the first subcarrier in the first OFDM symbol as a reference, and calculates an evaluation value ?El,m that is an index of a distance between the primary modulation symbol of the reception signal and the reference. When the evaluation value ?El,m is greater than or equal to a normal threshold, a weighting controller infers that interference occurred, and multiplies a soft decision value Wl,m,n by a weighting factor to calculate a corrected soft decision value Vl,m,n.

Abstract: A reception apparatus, method and a program using the reception method are provided to prevent degradation of reception quality due to interference. In a reception apparatus, an ADC samples data rIq[k] and rQq[k]. Based on the sampled data, a level detector finds an interference evaluation value Cc[l] for each OFDM symbol by counting the number of times one of the data rIq[k]q and rQq[kq] is clipped to the maximum output range of the ADC. When the interference evaluation value Cc[l] is greater than or equal to an interference decision value thc, a weighting control section corrects a soft-decision value wl,m,n by multiplying it by a weighting factor ?c so as to decrease contribution of an error correction code to decoding.

Abstract: A signal correcting and compensating system including a signal transceiver, a personal computer, a signal database, and a signal correction component. A signal sent by a remote control may be subjected to a distortion causing nuisance before it is received by a transceiver, possibly preventing the signal from being identified. A signal correction component may correct and/or compensate for errors by evaluating the signal and determining a margin of error for identifying information within the signal.

Abstract: Methods and apparatus that do not require a memory between the combiner and decision boundary estimator in a digital communications receiver and that enjoy unaltered performance are described. The methods and apparatus include new ways of estimating bit decision boundaries and may also include new ways of estimating soft bit values.

Abstract: The soft decision thresholds in a soft decision forward error correction (FEC) system may be adjusted based on mutual information of a detected signal. In one embodiment, a recursive algorithm may be used to optimize threshold values by maximizing the mutual information. In another embodiment, an adaptive scheme may be used to optimize threshold values based on a pre-knowledge of the noise in the channel. In a further embodiment, an adaptive scheme may be used to optimize threshold values by without pre-knowledge of the noise in the channel.

Abstract: The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratios in a single operation, as opposed to the two pass traditionally associated with the Tanner Graphs. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISOs. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.

Abstract: A reduced complexity turbo decoding scheme combines elements from two MAP (Maximum a posteriori) algorithms, namely a LogMAP algorithm and a max-LogMAP algorithm. Forward and backward recursive metrics are computed in accordance with the max-LogMAP algorithm, while output extrinsic LLR (Log Likelihood Ratio) values are computed in accordance with the LogMAP algorithm.

Abstract: A processor on which a software-based interleaver is run performs interleaver generation, which is split into two parts to reduce the overhead time of interleaver changing. First, preprocessing prepares seed variables, requiring a small memory. Second, on-the-fly address generation generates interleaved addresses through simple adding and subtracting operations using the seed variables.

Abstract: New and improved a-posteriori decoding probabilities, decisioning metrics, and implementation algorithms for turbo and convolutional decoding to replace the probabilities and decisioning metrics currently used in the maximum likelihood ML and maximum a-posteriori MAP algorithms. A-posteriori probabilities p(x}y) replace the current ML probabilities p(y}x) wherein y is the received symbol and x is the transmitted data and the MAP a-posteriori probability p(s?,s|y) replaces the current MAP joint probability p(s?,s,y) wherein s?,s are the trellis decoding states at k?1, k and y is the observed data set y(k),k=1, 2, . . . , N. This yields a-posteriori probabilities and decisioning metrics to improve decisioning and bit error rate BER performance and to provide a new mathematical decoding framework. Complexity is the same as current implementations.

Abstract: Systems and methods are provided to correct errors occurring in a decision-codeword that is generated by a detector. A decoder determines whether errors in the decision-codeword are of a degree that exceeds the correction capability of a Reed-Solomon error-correction code. If they are, the decoder iteratively modifies the decision-codeword to reduce the number of errors therein. In each iteration, the decoder generates an error indicator using one or more error indicators from a previous iteration and uses the error indicator to perform error detection and correction operations.

Abstract: A method and structure of processing soft information in a block code decoder, includes a soft-input soft-output decoder receiving a length n soft input vector, creating a binary vector Y corresponding to the soft input vector, hard decoding each linear function Xi of Y and a test pattern Zi of one or more test patterns, wherein if the hard decoding is successful a codeword produced by the hard decoding of Xi is added to a set S, removing redundant codewords in S to form a reduced set S? based on processing a number of errors found during the hard decoding and a guaranteed error correcting capability of the block code decode, and an extrinsic value estimator generating n soft outputs based on c estimated soft output values and (n-c) non-estimated soft output values wherein the c estimated soft output values are computed from one or more positions of soft input vector and one or more codewords in S?.