Abstract: In an error detection correction method of an embodiment, in decoding processing using a sum-product algorithm, which repeats processing of propagating reliability ? from a check node set to correspond to a Tanner graph of a check matrix of a low density parity check code to a plurality of bit nodes connected to the check node, and processing of propagating reliability ? from a bit node to a plurality of check nodes connected to the bit node, the check node includes a parity of two bits or more.

Abstract: The present invention is related to a circuit for encoding at least two input symbols by means of a space-time block code, comprising a plurality of multiplexers, each arranged to receive the input symbols and to output a selected symbol, storing means for storing information on which input symbol is to be selected in each multiplexer of the plurality of multiplexers and for storing gain factor information to multiply the multiplexer outputs with, calculation means, coupled with the storing means, for determining an encoded version of the input symbols based on the multiplexer outputs and corresponding gain factors stored in the storing means. The invention further discloses a corresponding circuit for space-time block decoding.

Abstract: A QC-LDPC decoding system employing a trapping set look-up table is provided. The QC-LDPC decoding system includes an iterative decoder that utilizes a message-passing algorithm to decode a received codeword. If the iterative decoder fails to produce a valid codeword, additional processing is performed to decode the received codeword. The additional processing includes the steps of computing the syndrome pattern of the received codeword, searching the look-up table for a trapping set class that is responsible for the iterative decoder's failure, retrieving from the look-up table a syndrome pattern and an error pattern of a member of the responsible trapping set class, and calculating the error pattern of the received codeword based on its syndrome pattern and the information retrieved from the look-up table. The received codeword is then corrected based on its error pattern.

Abstract: A method and apparatus for processing symbols of a block code is presented. A sequence of symbols is received, e.g., from an inter-symbol interference (ISI) channel. A soft value is determined for each symbol using a binary trellis.

Abstract: A system comprising a plurality of channel detectors (CDs) receiving quantized and equalized ISI channel information indicative of an LDPC codeword. The channel information is split for input to the CDs, such that each CD receives channel information indicative of a portion of the LDPC codeword. Each CD outputs at least first soft information for bits of the codeword portion of that CD. The first soft information for the codeword is received by an LDPC decoder, which uses the soft information to produce a user bit sequence and second soft information about the user bit sequence. The system can cause the second soft information to be input to the plurality of CDs, such that iterative processing can occur for the codeword. Other aspects include a system providing clocking of one or more CDs at a frequency selected to balance codeword throughput of the CDs with codeword throughput of an LDPC decoder clocked by a second clock, and methods according to each system.

Abstract: An apparatus for providing improved gray mapping may include a processor. The processor may be configured to divide gray value byte data into high priority portions and low priority portions distributed as constellation points in a constellation matrix and to provide separation between each of the constellation points by assigning a unique mapping code to a plurality of the constellation points.

Abstract: A method for physically laying out data on tape is disclosed herein. In one embodiment, such a method includes receiving a data set, wherein the data set includes S sub data sets (SDSs) of fixed size and each SDS includes N codeword interleaves (CWIs). The method further distributes the CWIs for the S SDSs across T tracks on a physical tape medium such that the distances between CWIs of the same SDS are substantially maximized on the physical tape medium. To maximize the distances, the method periodically rotates the tracks within the data set by a track rotation value R, wherein the number of tracks T is equal to 2k, and the track rotation value R is equal to 2k?1?1. A corresponding apparatus is also disclosed herein.

Abstract: A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code.

Abstract: The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital bits. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the LDPC code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information bits. If an equality node is in a hold state a chosen bit is provided from a corresponding edge memory which is updated by storing output bits from the equality node when the same is in a state other than a hold state.

Abstract: An arrangement and method for channel mapping in a UTRA TDD HSDPA wireless communication system by applying interleaving functions in first (530) and second (540) interleaving means to a bit sequence to produce symbols for mapping to physical channels, the first and second interleaving means being arranged to map symbols from respectively systematic and parity bits in a predetermined scheme, e.g., mapping symbols in a forward direction when a channel has an even index number, and in a reverse direction when a channel has an odd index number. The symbols may comprise bit-pairs, each of a systematic bit and parity bit. Systematic bits are preferably mapped to high reliability bit positions in TDD HSDPA, achieving a performance gain of between 0.2 dB and 0.5 dB. The forwards/reverse mapping allows a degree of interleaving that improves system performance in fading channels or channels disturbed by short time period noise or interference.

Abstract: Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.

Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived form a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.

Abstract: A system and method is provided for decoding a set of bits using a plurality of hypotheses, for example, each independently tested on-the-fly. Initial bit states and associated reliability metrics may be received for the set of bits. A current hypothesis may be decoded for correcting the set of bits, wherein the current hypothesis defines different bit states and associated reliability metrics for the set of bits. If decoding the current hypothesis is not successful, a subsequently ordered hypothesis may be decoded, wherein the hypotheses are ordered such that their associated reliability metric is a monotonically non-decreasing sequence. Decoding may proceed iteratively until the current hypothesis is successful.

Abstract: Symbol by symbol MAP detection for signals corrupted by colored and/or signal dependent noise. A novel means is presented for recursive calculation of forward metrics (?), backward metrics (?), and corresponding soft information (e.g., which can be provided as LLRs (log likelihood ratios)) within communication systems in which a trellis can be employed to perform demodulation of a received signal sequence. For signals that have been corrupted by colored and/or signal dependent noise, this means provides for the ability to perform novel soft information calculation for subsequent use in iterative decoding processing. Many types of communication channels can benefit from this novel means of detection including communication channels within hard disk drives (HDDs).

Abstract: A method is for generating, for each check node related to a parity check equation of a LDPC code, signals representing a first output table of corrected values of symbols of a word received through a communication channel and transmitted according to the LDPC code, and signals representing a second output table of the logarithm of the ratio between the respective probability of correctness of the values of same coordinates in the first output table and their corresponding maximum probability of correctness. The method is implemented by processing the components of a first input table of values of a Galois Field of symbols that may have been transmitted and of a second input table of corresponding probability of correctness of each value.

Abstract: A decoding apparatus and method are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the result of the first computation process in a decoding intermediate result storage memory. A computation section carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the decoding intermediate result in the decoding intermediate result storage memory.

Abstract: Systems and methods are provided for encoding a stream of datawords based on a tensor product code to provide a stream of codewords, and detecting and decoding a stream of received data based on a tensor product code to provide a decoded stream of data. In one aspect, the tensor product code is based on two codes including an inner code and an outer parity hiding code, where the outer parity hiding code is an iterative code. In certain embodiments, the outer parity hiding code is a Turbo code or a low density parity check (LDPC) code.

Abstract: Methods and apparatus are provided for reduced complexity Soft-Output Viterbi detection. A Soft-Output Viterbi algorithm processes a signal by determining branch metrics using a branch metrics unit; determining survivor paths for sequence detection using a first add-compare select unit; and determining survivor paths for generating one or more bit reliability values using a second add-compare select unit, wherein the first and second add-compare select units process the branch metrics determined by the branch metrics unit. The first and second add-compare select units can optionally process branch metrics having a different number of bits.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of turbo decoding. For example, a device may include a turbo decoder to decode a turbo-encoded input according to a turbo code, the turbo-encoded input including a plurality of soft-decision information-bit values and a plurality of soft-decision parity-bit values corresponding to the soft-decision information bit values, wherein the turbo decoder is to output a plurality of extrinsic soft-decision parity-bit values corresponding to the plurality soft-decision parity-bit values. Other embodiments are described and claimed.

Abstract: A method is provided for decoding and/or detecting data containing user information which is received by a communication network in order to provide a way to suppress error concealment and to provide improved error correction. The present invention is characterized in that a receiver of a communication terminal and a CTM-receiver exchange at least additional information relating to the reliability of the correct reception of the data thus received and that error processing of the data thus received is adjusted in a receiver.

Abstract: The present invention provides a distributed clustering method to allow multiple active instances of consistency management processes that apply the same encoding scheme to be cooperative and function collectively. The techniques described herein facilitate an efficient method to apply an erasure encoding and decoding scheme across dispersed data stores that receive constant updates. The technique can be applied on many forms of distributed persistent data stores to provide failure resiliency and to maintain data consistency and correctness.

Abstract: An interleaving method (1) and a frequency interleaver (EF) of data symbols. The data symbols are for allocation to carriers of a set of NFFT carriers of a module for multiplexing and modulation by orthogonal functions in a multicarrier transmitter device (EM). The method includes selecting in time-varying manner from the set of carriers, carriers that are dedicated to transmitting data symbols and in dynamically interleaving a block of carriers constituted by the selected carriers and by null carriers.

Abstract: Systems and methods are provided for correcting absorb sets and near absorb sets in the (2048, 1723) LDPC code used in 10GBase-T transmission systems. Absorb sets and near absorb sets correspond to error patterns that, due to the structure and imperfections of the LDPC code, cannot easily be corrected using standard correction methods. To correct these error patterns, a set of failed syndrome checks associated with the error pattern can be identified, and the 4, 8, 12, or 16 error patterns associated with the failed syndrome checks can be determined. The codeword may then be corrected based on the error pattern that most likely occurred.

Abstract: Provided are an apparatus for estimating a phase error and a phase error correcting system using the phase error estimating apparatus. The apparatus includes: a probability value estimating unit for estimating a negative log probability value for each transmission symbol by transforming a soft output information transferred from the outside to a log A posterior probability ratio (LAPPR) value; an APP value calculating unit for calculating a posterior probability (APP) value by applying a negative exponential function to the transmission symbol; an average value deciding unit for deciding an average value for each transmission symbol using the probability information entirely, partially, or selectively according to a probability information type; and a symbol phase estimating unit for estimating a phase of a symbol based on the decided average value.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: A method for communication includes allocating, in a multiple-access communication system (20) that uses multiple subcarriers, first subcarriers to a first communication terminal for transmitting first data, and second subcarriers to a second communication terminal for transmitting second data. The first communication terminal is assigned to modulate the first data onto at least some of the first subcarriers using a first multi-carrier modulation scheme, to produce a first signal. The second communication terminal is assigned to modulate the second data onto at least some of the second subcarriers using a second multi-carrier modulation scheme, which has a reduced peak-to-average power ratio (PAPR) relative to the first multi-carrier modulation scheme, to produce a second signal. Simultaneous communication is carried out with the first and second communication terminals by simultaneously receiving the first and second signals over the first and second subcarriers.

Abstract: According to a method and apparatus taught herein, a decoding circuit and method decode linear block codes based on determining joint probabilities for one or more related subsets of bits in received data blocks. The use of joint probabilities enables faster and more reliable determination of received bits, meaning that, for example, joint probability decoding requires fewer decoding iterations than a comparable decoding process based on single-bit probabilities. As a non-limiting example, the decoding circuit and method taught herein provide advantageous operation with Low Density Parity Check (LDPC) codes, and can be incorporated in a variety of communication systems and devices, such as those associated with wireless communication networks.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.

Abstract: Provided is an iterative residual frequency and phase compensation apparatus for an OFDM system and a method thereof. The apparatus includes: a first classifying unit for classifying symbol sequences by each subcarrier wave; a soft-decision calculating unit for calculating a soft-decision value of a data symbol using a soft-decision reliability obtained from iterative decoding performed by the iterative decoder; a classifying unit for classifying the soft-decision values by a carrier wave; a frequency estimating unit for estimating a residual frequency error of each carrier wave using the soft-decision value; a phase estimating unit for estimating an average residual phase error using the soft-decision value; a frequency and phase compensating unit for compensating frequencies and phases for input symbols of each carrier wave using the estimated frequency error and the estimated phase error; and a buffer for temporally storing the compensated symbols to provide it to the first classifying unit.

Abstract: Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.

Abstract: Methods and apparatus are provided for computing soft data or log likelihood ratios for received values in communication or storage systems. Soft data values or log likelihood ratios are computed for received values in a communication system or a memory device by obtaining at least one received value; identifying a segment of a function corresponding to the received value, wherein the function is defined over a plurality of segments, wherein each of the segments has an associated set of parameters; and calculating the soft data value or log likelihood ratio using the set of parameters associated with the identified segment. The computed soft data values or log likelihood ratios are optionally provided to a decoder.

Abstract: This memory device comprises a word-line control circuit applying a read voltage and a soft-value read voltage as a word line voltage to a word line to generate soft-values. The soft-value read voltage is between an upper limit and a lower limit of each of plural threshold voltage distributions. A likelihood calculation circuit calculates a likelihood value of data stored in a memory cell based on the soft-value. An error correction circuit executes data error correction for the data read from the memory cell based on the likelihood value. A refresh control circuit controls a timing of a refresh operation for the memory cell based on the soft-value or the likelihood value.

Abstract: According to one embodiment, an error correction decoding apparatus including a hard-decision decoding module which performs hard-decision decoding using a signal with 2 levels per bit as input data and runs a parity check on the input data, a soft-decision decoding module which performs soft-decision decoding using a signal with the number of multiple levels per bit larger than 2 as input data, a start-up control module which controls the start-up of each of the decoding modules, and an output selection module which selects one of the output signals of the decoding modules. The start-up control module causes the output selection module to select the decoding result of the hard-decision decoding module when the parity errors is a permitted value and causes the output selection module to select the decoding result of the soft-decision decoding module when the parity errors has exceeded the permitted value.

Abstract: A receiver and method for HARQ combining of a received codeword in a receiver with a FEC decoder, the method including computing Log Likelihood Ratios (LLRs) of demodulated soft symbols of the received codeword and outputting the LLRs as a-priori soft bits; performing iterative decoding of the a-priori soft bits in a Forward Error Correction (FEC) decoder; outputting a posteriori soft bits of the a priori soft bits of the received codeword from the FEC decoder; and HARQ combining the a posteriori soft bits with a retransmission of the received codeword.

Abstract: A channel quality indicator value is determined on a per transport block basis. A signal-to-interference ratio estimate of a control channel and a channel quality estimate of user-data channel are employed in the determination of the channel quality indicator. The channel quality estimate of the user-data channel can include information about Automatic Retransmission Request (ARQ) processing, and the number of iterations of a Turbo decoder. Additionally, information about the Cyclic Redundancy Check (CRC), which is determined on a per transport block basis, can be employed in the channel quality indicator determination. The determined channel quality indicator is reported to the radio communication system.

Abstract: An iterative message passing decoder, e.g., an LDPC decoder, operating in conjunction with a soft input-soft output signal processing unit, e.g., an ISI detector, has an error floor performance region influenced by the decoder's sub-optimal message passing nature. Error floor reduction is achieved by a simple message re-initialization mechanism. Decoder edge states, e.g., constraint to variable node messages in decoder memory, are reinitialized, e.g., for an iteration, during the decoding after soft values provided by signal processing unit have improved. During the message re-initialization and for some subsequent amount of iterative decoder processing, extrinsic information fed back from the decoder to the signal processing unit and/or soft values delivered to the decoder from the signal processing unit, in an outer communications loop, is temporarily frozen, e.g., using a switch and a buffer. Then, the outer communications loop is restored as the decoding continues, achieving improved decoding performance.

Abstract: According to one embodiment, a decoder device includes a decoder configured to decode a to-be-decoded sequence by performing an iterative decoding process and to perform a parity check of a decoding result using a check matrix, a detector configured to detect that the to-be-decoded sequence is a non-code word based on a parity check result for each row of the check matrix by the decoder, and a controller configured to control the decoder according to a detection result of the detector.

Abstract: A turbo equalizer includes a Bahl-Cocke-Jelinek-Raviv (BCJR) equalizer configured to receive a transmitted signal and partially cancel inter-symbol interference (ISI) due to polarization-mode dispersion (PMD). A low-density parity check (LDPC) decoder is coupled to the BCJR equalizer to receive channel bit reliabilities therefrom. The LDPC decoder iteratively provides extrinsic soft information feedback to the BCJR equalizer to compensate for PMD.

Abstract: A bit quality evaluator receives a sequence of bits. A quality measure is assigned to each bit within the sequence. The bit sequence and the quality measures are provided to a decoding device that performs soft decision convolutional decoding on the sequence of bits using the quality measure. An off-path detector detects an occurrence of a trellis decode path change during the convolutional decoding operation and identifies a first symbol proximate corresponding to the occurrence of the trellis decode path change. An erasure decision circuit identifies at least the first symbol for erasure. The output of the first decoder and the erasure decision circuit are received at a second decoder, which decoder decodes the output of the first decoder after erasing at least the first symbol. The erasure decision circuit may also identify additional symbols for erasure based on performance measures of the trellis decode path and the quality measure of the sequence of bits.

Abstract: A method for communication includes receiving first and second data frames over first and second communication links, respectively, the first and second data frames containing respective first and second replicas of data, which has been encoded with a Forward Error Correction (FEC) code. The FEC code in the received first and second data frames is decoded, and respective first and second soft quality ranks of the first and second data frames are computed based on the decoded FEC code. One of the first and second replicas of the data are selected based on the first and second soft quality ranks. The selected one of the first and second replicas of the data is provided as output.

Abstract: It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed using the decoder and the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed using the decoder and the data associated with the decoder.

Abstract: A wireless communications apparatus according to the present invention includes a scheduler which allocates, to a user apparatus, at least one resource block included in a system bandwidth; an interleaver which rearranges an order of bits within a bit sequence according to a specified pattern; a unit which creates a transmit symbol including the interleaved bit sequence; and an interleaving-pattern determining unit which determines a range of the bit sequence to be rearranged based on a number of the resource blocks, a data modulation scheme, and a channel encoding rate, determines a rearranging pattern according to the range, and communicates the determined pattern to the interleaver.

Abstract: According to one aspect of the teachings presented in this document, a wireless communication receiver implements a form of joint detection that is referred to as “fast joint detection” (FJD). A receiver that is specially adapted to carry out FJD processing provides an advantageous approach to joint detection processing wherein the number of computations needed to produce reliable soft bits, for subsequent turbo decoding and/or other processing, is significantly reduced. Further, the algorithms used in the implementation of FJD processing are particularly well suited for parallelization in dedicated signal processing hardware. Thus, while FJD processing is well implemented via programmable digital processors, it also suits applications where high-speed, dedicated signal processing hardware is needed or desired.

Abstract: A receiver system, which generates a soft decision signal from a hard decision signal, includes a hard output receiver for determining a received bit to generate a hard decision signal. A hard input soft output receiver determines an estimated probability of symbol data corresponding to the received bit based on the hard decision signal and generates a soft decision signal represented by a log-likelihood ratio from the estimated probability.

Abstract: Data in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data can be performed to. The simulated annealing can introduce randomness, as noise for example, into the decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

Abstract: A soft decision value correction method can detect interference occurring in a desired wave and correct a soft decision value where a received power difference between the desired wave and an interference wave is small. A receiver and a program capable of performing the soft decision value correction method are provided. In the receiver an EVM calculator sets a detection distance for a primary modulation symbol of the first subcarrier in the first OFDM symbol as a reference, and calculates an evaluation value ?El,m that is an index of a distance between the primary modulation symbol of the reception signal and the reference. When the evaluation value ?El,m is greater than or equal to a normal threshold, a weighting controller infers that interference occurred, and multiplies a soft decision value Wl,m,n by a weighting factor to calculate a corrected soft decision value Vl,m,n.

Abstract: Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.

Abstract: Data in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data can be performed. The simulated annealing can introduce randomness, as noise for example, into the decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.