Abstract: Multiple channels of received data are processed by a multiple channel demodulation and error correction decoding engine. The statistical uncertainty of processing channels with an iterative decoder are averaged across all the channels to reduce the total processing power required of the decoding engine compared to processing each channel with a separate engine. A set of input buffers holds blocks of data for each channel needing decoding. A quality measure is computed on each input block to set the priority and iteration allocation of decoding in the common decoder. The input RF signal is digitized by a broadband tuner that processes some or all of the channels to feed the multiple channel demodulator and decoder. Multiple decoded video data streams are output.

Abstract: A data detection and decoding system includes a SOVA channel detector that uses single parity (SOVASP) to improve the accuracy with which the detector estimates bits. Each column or row read back from the read channel constitutes a code word and each code word is encoded to satisfy single parity. Because the SOVASP channel detector detects whether each code word satisfies single parity, it is unnecessary to use both a column decoder and a row decoder in the channel decoder. Either the row decoder or the column decoder can be eliminated depending on whether bits are read back on a column-by-column basis or on a row-by-row basis. This reduction in components reduces hardware complexity and improves system performance. The output of the row or column decoder is received by a second detector that processes the output received from the decoder to recover the original information bits.

Abstract: A method for implementation of error correction decoding of quadrature layered modulation QLM communications. A bound on communications capacity derived using ideal QLM is approximated with QLM communications links which support data rates independent of the Shannon bound. Trellis symbol and bit demodulation algorithms recover QLM data symbols and bit algorithms offer computational efficiency at a cost of decisioning errors. Correlated bit decisioning error correction decoding and re-encoding can be implemented in a bit demodulation algorithm. Trellis demodulation and trellis decoding algorithms support parallel implementations, and concatenated implementations wherein the error correction decoding is implemented after the QLM demodulation. Concatenated implementation supports turbo decoding, MAP decoding, convolutional decoding, and block decoding by using the decisioning metrics available from QLM demodulation in place of generating the decisioning metrics directly from the detected symbol measurements.

Abstract: A method for decoding a plurality of flash memory cells which are error-correction-coded as a unit, the method comprising providing a hard-decoding success indication indicating whether or not hard-decoding is at least likely to be successful; and soft-decoding the plurality of flash memory cells at a first resolution only if the hard-decoding success indication indicates that the hard-decoding is not at least likely to be successful.

Abstract: Techniques for data compression are provided. A data compression technique may include selecting a symbol string, being one or more characters, that occurs within a data set, generating a symbol string code corresponding to respective positions of the symbol string within the data set, successively repeating the above procedure for any additional symbol strings that occur within the data set to produce any additional respective symbol string codes, and generating a compressed data code through combining the respective symbol string codes.

Abstract: An LDPC decoder, applicable to LDPC codes including codes where check nodes within the same group are connected to a common bit node, successively processes groups of check nodes in a particular iteration, including updating bit nodes in that same iteration responsive to messages generated in response to processing a group of check nodes. Within an iteration, the LDPC decoder may also track the number of unresolved parity check equations, and cease iterating or output to an outer block decoder if that number reaches a local minima or standard minimum, falls below a predetermined threshold, or its rate of change falls below a predetermined threshold, indicating a lack of convergence or false convergence condition. The LDPC decoder may also provide a feedback assist to a demodulator. Also, a novel memory configuration may store messages generated by the decoder in the course of check node processing.

Abstract: Embodiments of the invention provide a decoder arrangement (400), wherein a decoder (420) which is adapted to decode a bitstream which has been encoded with a non-recursive convolutional encoder is used to at least partially perform the decoding of a recursive convolutionally encoded bitstream, with pre- or post-processing (410) of the bitstream being performed to complete the decoding. More particularly, in one embodiment of the invention a recursively encoded bitstream is input into a. conventional decoder (420) which is adapted to decode a non-recursively encoded bitstream. The resulting intermediate output does not represent the correct decoded bitstream, but can then be subject to a post-processing step in the form of a non-recursive encoding operation (410), which effectively completes the decoding operation and provides as its output the correct decoded bitstream. Both hard decision or soft decision inputs can be used.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: A soft decision demapping method includes defining distance values between a received signal and coordinates of constellation dots, obtaining a difference between a maximum value of distance values when a first bit is 0 and a maximum value of distance values when the first bit is 1, during a soft decision of the first bit of N-bit received signal symbol, acquiring a difference between a maximum value of distance values when a second bit is 0 and a maximum value of distance values when the second bit is 1, during a soft decision of the second bit of the N-bit received signal symbol, and deriving a difference between a maximum value of distance values when an Nth bit is 0 and a maximum value of distance values when the Nth bit is 1, during a soft decision of the Nth bit of the N-bit received signal symbol.

Abstract: A turbo decoder iteratively decodes a received, encoded signal with one or more constituent decoders employing a simplified log-maximum a posteriori (SMAP) decoding algorithm. The SMAP decoding algorithm calculates reliability information as a log likelihood ratio for a log-MAP algorithm using a reduced set of path metrics recursively updated based on maximum likelihood recursion. Updated extrinsic information for a subsequent decoding may be derived from the LLR calculated by the SMAP decoding algorithm.

Abstract: Disclosed is a signal transmission method in a mobile communication system. Unequal error protection (UEP) ratios are determined so that the bits may have different received qualities according to the weights of the bits. The bits are repeated by a bit sequence repeater (210) according to the determined UEP ratios to generate a repeated bit sequence having a predetermined number of bits. The generated repeated bit, sequence is interleaved by an interleaver (220) and the interleaved bit sequence is symbol-mapped by a symbol-mapper (230) to generate a transmission symbol sequence, and the generated transmission symbol sequence is transmitted by the transmitter to a receiver. Furthermore, also a corresponding signal reception method, a corresponding signal transmitter and a corresponding signal receiver are disclosed.

Abstract: A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such a method may use an update module for receiving and manipulating the soft-decision data and iteratively change bits or groups of bits based upon an ordering of the reliability factors. Then a calculator module may determine the total number of errors still remaining after each iteration. Determining just the total number of errors instead of the actual locations is far less computationally intensive, and therefore, many combination of potential flip-bit combination may be analyzed quickly to determine if any combination might reduce the total number of errors enough to be handled by the conventional hard-decision ECC decoding method.

Abstract: The disclosed technology provides a less resource intensive way to decode a parity check code using a modified min-sum algorithm. For a particular parity check constraint that includes n variable nodes, an LDPC decoder can compute soft information for one of the variable nodes based on combinations of soft information from other variable nodes, wherein each combination includes soft information from at most a number d of other variable nodes. In one embodiment, soft information from one of the other variable nodes is used in a combination only if it corresponds to a non-most-likely value for the other variable node.

Abstract: A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such reliability information may be used to identify particular symbols with a higher likelihood of error such that these symbols may be changed in an attempt to reduce the total number of errors in the data. In an embodiment, a soft-decision ECC decoding path may include a reliability checker operable to receive bits of data read from a data store and operable to associate a reliability factor with each bit of data. Then, an update module may iteratively change bits or groups of bits based upon an ordering of the reliability factors.

Abstract: A soft output decoder capable of performing decoding with a small computational complexity necessary for likelihood calculation thereby to reduce the scale of the operation circuit and to shorten the processing delay time. The soft output decoder (100) comprises a &ggr;? calculating section (101), timing adjusters (102, 103), a &ggr;? calculation section (104), and a &Lgr; calculating unit (110). The &Lgr; calculating unit (110) is composed of a hard decision decoding section (111), a loss likelihood calculating section (112), a win likelihood storage section (113), and a subtractor (114). The likelihoods determined by a Max-log-MAP decoder are separated into win likelihoods and loss likelihoods, and only the loss likelihoods are calculated. A hard decision decoding section (111) for sequentially specifying the states through which the maximum likelihood path passes is used for a method for distinguishing the win and loss likelihoods.

Abstract: A soft decision device and method for obtaining a soft decision value as a value expressing a probability as near the actual probability as possible by simple processing. The soft decision device and method are used to output a soft decision value for each bit of each symbol used for decoding the each symbol as a value corresponding to the function value obtained by applying a predetermined function for each bit to the sampled value of the each symbol according to the demodulated signal such that the probability distribution of the sampled value in each symbol point is the Gauss distribution. The function for each bit is approximated to a curve expressing the probability that each bit is 1 or 0 for the sampled value of each symbol of the demodulated signal and defined by using a quadratic function.

Abstract: In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low.

Abstract: A method and system for determining low error rate behavior of a device are provided. In one implementation, the method includes obtaining a dominant trapping set of a code, the dominant trapping set containing a plurality of variable nodes, and biasing bits associated with a programmable transmitter that is in communication with the device. The biased bits correspond to the variable nodes of the dominant trapping set. The method further includes transmitting random data from the programmable transmitter to the device, in which the random data includes one or more of the biased bits; measuring a number of error events corresponding to biased bits received by the device that cannot be decoded; and determining a true bit error rate of the device based on the measured number of error events.

Abstract: A DTV transmitting system includes an encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizer randomizes the coded enhanced data, and the block processor codes the randomized data at an effective coding rate of 1/H. The group formatter forms a group of enhanced data having data regions, and inserts the coded enhanced data into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into corresponding data bytes.

Abstract: Apparatus and methods arc provided to decode signals from a communication channel to reconstruct transmitted information. Embodiments may include applying a plurality of decoders to a code, in which reliability values are provided to a decoder such that the decoder receives the reliability values determined by and provided from only one other decoder of the plurality of decoders. A valid codeword may be output from application of the plurality of decoders to the code.

Abstract: A method of processing a received concatenated code codeword is disclosed, the concatenated code codeword comprising a plurality of inner code codewords and one or more outer code codewords, each inner code codeword comprising symbols, from each outer code codeword comprising one or more information symbols and one or more parity symbols, the parity symbols in each outer code codeword corresponding to the parity check equations of the outer code. The method comprises (i) decoding the received concatenated code codeword; (ii) erasing a subset of the received inner code codewords; and (iii) determining a replacement inner code codeword to replace each of the erased inner code codewords to provide a candidate concatenated code codeword.

Abstract: A plurality of decoding metrics for a current frame may be generated based on a correlation set for a current frame and a correlation set for at least one previous frame. Whether a signal is present on a control channel may then be determined based on the generated decoding metrics.

Abstract: The present invention is directed to providing a spatial-multiplexed signal detection method that can improve the characteristics of spatial and temporal iterative decoding that is based on turbo principles. According to the method, when implementing factorization of conditional probability referred to as “likelihood” such that the conditional probability can be represented by the product of a plurality of conditional probabilities, the conditional probability being obtained for a received signal sequence in a spatial and temporal iterative decoding configuration based on turbo principles of soft-input soft-output detector 1 and soft-input soft-output decoder 2, the conditional probability for which factorization is possible is divided into a plurality of groups. When calculating this likelihood, the ordering among groups in which probabilities are calculated can be ordered such that groups that contain events that serve as the conditions of conditional probabilities in the groups are processed earlier.

Abstract: An interleaver for a turbo encoder and decoder comprising a first table populated with a first set of parameters to allow intra-row permutation of data within an array in accordance with a first wireless communication standard when operation in the first wireless communication standard is required and a second table populated with a second set of parameters to allow inter-row permutation of the data in accordance with the first wireless communication standard when operation in the first wireless communication standard is required wherein the first table is populated with a third set of parameters to allow intra-row permutation of data within an array in accordance with a second wireless communication standard when operation in the second wireless communication standard is required and to populate the second table with a fourth set of parameters to allow inter-row permutation of the data in accordance with the second wireless communication standard when operation in the second wireless communication standard i

Abstract: A wireless communication device employs a method for receiving a message stream on a control channel. According to one embodiment, the wireless communication device receives a message on the control channel. The wireless communication devices attempts to decode the message and, if the message is successfully decoded, adds bits of the successfully decoded message to a message attributes list. Some time thereafter, the wireless communication device attempts to decode a subsequent message received on the control channel and, if an error is detected during decoding of the subsequent message, replaces bits in the subsequent message with bits from the message attributes list to produce a modified message. The wireless device then attempts to decode the modified message.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: The invention provides circuits that are tolerant to soft errors, such as a single event upset (SEU). The circuits have a chain of permitted state changes. Redundant elements, including redundant literals and assignments, are designed and implemented in the circuit. The design is such that a disruption or change of state on a single element by an SEU will not change the state flow of a circuit or lead to impermissible state changes. In one embodiment, the invention is implemented in quasi-delay-insensitive (QDI) asynchronous circuits.

Abstract: A method and apparatus are provided for error correction of a communication signal. A multiple threshold scheme for iteratively decoding a received codeword includes using a comparison of an updated bit reliability with a threshold to generate a reconstructed version of the received codeword. At each iteration the bit reliability and the reconstructed codeword are updated based on a comparison using a threshold that has been updated for the given iteration. Embodiments include decoding and/or associated encoding methods and apparatus using a threshold having two of more values during the iterative decoding.

Abstract: A turbo-like code is formed by repeating the signal, coding it, and interleaving it. A serial concatenated coder is formed of an inner coder and an outer coder separated by an interleaver. The outer coder is a coder which has rate greater than one e.g. a repetition coder. The interleaver rearranges the bits. An outer coder is a rate one coder.

Abstract: Various systems and methods for error reduction in a digital information system are disclosed herein. As one example, a digital storage system is provided that includes a soft output Viterbi algorithm channel detector operable to receive an encoded data set, and to provide a hard and a soft output representing the encoded data set. The hard and the soft output from the soft output Viterbi algorithm channel detector are provided to a single parity row decoder that provides another hard output that is an error reduced representation of the encoded data set. The encoded data set is additionally provided from the buffer to another channel detector via a delay element. The hard output from the single parity row decoder and the time shifted encoded data set are provided to coincident with each other to another channel detector.

Abstract: An arrangement and method for channel mapping in a UTRA TDD HSDPA wireless communication system by applying interleaving functions in first (530) and second (540) interleaving means to a bit sequence to produce symbols for mapping to physical channels, the first and second interleaving means being arranged to map symbols from respectively systematic and parity bits in a predetermined scheme, e.g., mapping symbols in a forward direction when a channel has an even index number, and in a reverse direction when a channel has an odd index number. The symbols may comprise bit-pairs, each of a systematic bit and parity bit. Systematic bits are preferably mapped to high reliability bit positions in TDD HSDPA, achieving a performance gain of between 0.2 dB and 0.5 dB. The forwards/reverse mapping allows a degree of interleaving that improves system performance in fading channels or channels disturbed by short time period noise or interference.

Abstract: A method of decoding a received signal encoded with an LDPC code is provided. The method comprises initializing bits with an initial value of the received signal, obtaining posterior values of the bits by iteratively decoding the bits in a row direction and a column direction, determining on the basis of the posterior values whether an iterative decoding operation should be performed and comparing the posterior values with predetermined values and updating the initial value of the bits, when it is determined that the iterative decoding operation is be performed.

Abstract: In iterative-diversity (ID) transmission systems for signals with concatenated convolutional coding (CCC), paired iterative diversity signals each have ½ the code rate of the 8VSB DTV signals prescribed by the 1995 ATSC Digital Television Broadcast Standard. Known serial concatenated convolutional coding (SCCC) or novel parallel concatenated convolutional coding (PCCC) is used in such system. Pairs of CCC signals code data bits and ones' complemented data bits respectively, using similar coding algorithms. Receivers for this transmission system use respective turbo decoders for turbo decoding the earlier-transmitted and later-transmitted CCC signals. Turbo decoding of the earlier-transmitted portions of iterative diversity signals is delayed to be contemporaneous with turbo decoding of the later-transmitted portions of iterative diversity signals. This facilitates the turbo decoders exchanging information concerning confidence levels of data bits during the turbo decoding procedures.

Abstract: Various systems and methods for generating error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for generating an erasure pointer is disclosed that includes accumulating a number of error values into an overall error value, and comparing the overall error value to an error threshold. When the overall error value exceeds the error threshold, an erasure pointer is generated. In one particular case, the error values are derived from a look up table using thermometer codes generated by an analog to digital converter. In other cases, the error values are derived from comparing a soft output with a reliability threshold.

Abstract: The systematic and parity bits of a symbol are tightly coupled to each other based on the way in which the symbol is encoded. The relationship between the systematic and parity bits can be exploited to improve the accuracy of soft bit estimation for both the systematic bits and parity bits. In one embodiment, a received symbol is processed by demodulating the received symbol to determine an initial soft estimate of each systematic bit and corresponding one or more parity bits in the sequence. The systematic bit sequence is iteratively decoded to revise the soft estimate of the systematic bit. The initial soft estimate of the one or more parity bits associated with each systematic bit is revised based on the revised soft estimate of each systematic bit. The received symbol can be decoded or regenerated based on the revised soft estimate of each systematic bit and corresponding one or more parity bits.

Abstract: A method and apparatus for providing a read channel having combined parity and non-parity post processing is disclosed. A post-processor combines parity and non-parity post processing to make both parity and non-parity corrections so that error events that cannot be detected by parity may be corrected. Non-parity detectable error events are only kept for consideration if their likelihood is above a set threshold.

Abstract: A reception apparatus, method and a program using the reception method are provided to prevent degradation of reception quality due to interference. In a reception apparatus, an ADC samples data rIq[k] and rQq[k]. Based on the sampled data, a level detector finds an interference evaluation value Cc[l] for each OFDM symbol by counting the number of times one of the data rIq[k]q and rQq[kq] is clipped to the maximum output range of the ADC. When the interference evaluation value Cc[l] is greater than or equal to an interference decision value thc, a weighting control section corrects a soft-decision value wl,m,n by multiplying it by a weighting factor ?c so as to decrease contribution of an error correction code to decoding.

Abstract: Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment.

Abstract: Disclosed is a method and apparatus for fully-distributed packet scheduling in a wireless network. The decoding algorithm with low-density parity-check code is applied in a transmission wireless network to achieve the fully-distributed packet scheduling. In the packet scheduling, only one wireless network node is needed to exchange information and communicate with its neighboring network nodes. Therefore, it is not necessary to estimate the signal to noise ratio, while being eye to eye among the neighboring network nodes. If the network load exceeds the network capacity, the present invention automatically eliminates the most difficult user to reduce the overall network load and diverts the resources to the surviving users.

Abstract: True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.

Abstract: A receiving apparatus has two or more reception antennas, a data reproducer, and a likelihood information generator. The receiving apparatus operates selectively in a first reception mode and a second reception mode depending on the features of signals sent from a transmitting apparatus. In the first reception mode, the receiving apparatus reproduces data and generates likelihood information. In the second reception mode, the receiving apparatus reproduces data using the likelihood information generated in the first reception mode.

Abstract: A bit sequence (b, b?) from QPSK or QAM symbols is decoded, in which an associated receive probability (w, w?) is assigned to each receive bit (b, b?). The receive probability (w, w?) is adaptively determined taking into account the transfer properties of the channel.

Abstract: A decoding apparatus, decoding the LDPC code using a message passing algorithm, sets a message as a log likelihood ratio having, as a base, a real number “a” which is a power of 2, and includes a check node processing calculating unit for receiving a message from a bit node to calculate a message from a check node. The check node processing calculating unit includes a converter for converting an absolute value x of the message to output f (x) and a converting unit supplied as an input y with a sum of the absolute values x of the message from the totality of the bit nodes less one, converted by the converter, subdividing the input y in preset domains and for converting the number in the domain into g (y), and expresses the boundary values of the domains of the input y and f (x) by a power of 2.

Abstract: In a method of decoding data symbols into codewords, reliability information of the data symbols is provided. A first group of symbols from a first set of groups of symbols is selected, wherein the first set of groups of symbols is defined by at least a first parity-check of a parity-check matrix of a linear block code which has been used to encode the data symbols. The selection is based on the reliability information. A second group of symbols from a second set of groups of symbols is selected, wherein the second set of groups of symbols is defined by at least a second parity-check of the parity-check matrix. The selection is based on the selected first group of symbols and the reliability information. At least a part of the codeword is composed on the basis of the first group of symbols and the second group of symbols.

Abstract: Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ½ ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module, subtractor module and delay pipeline. The accumulator module generates an accumulated message sum. The accumulated message sum for a node is stored and then delayed input messages from the delay pipeline are subtracted there from to generate output messages.

Abstract: A low density parity check (LDPC) code for a belief propagation decoder circuit is disclosed. LDPC code is arranged as a macro matrix (H) representing block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix with a shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns are grouped, so that only one column in the group contributes to the parity check sum in a row. A parity check value estimate memory is arranged in banks logically connected in various data widths and depths. A parallel adder generates extrinsic estimates for generating new parity check value estimates that are forwarded to bit update circuits for updating of probability values. Parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.

Abstract: In one embodiment, an LDPC decoder attempts to recover an originally-encoded LDPC codeword based on a set of channel soft-output values. If the decoder observes a trapping set, then the decoder compares the observed trapping set to known trapping sets stored in a trapping-set database to determine whether or not the observed trapping set is a known trapping set. If the observed trapping set is not known, then the decoder selects a most-dominant trapping set from the trapping-set database and identifies the locations of erroneous bit nodes in the selected trapping set. Then, the decoder adjusts the channel soft-output values corresponding to the identified erroneous bit nodes. Adjustment is performed by inverting some or all of the hard-decision bits of the corresponding channel soft-output values and setting the confidence value of each corresponding channel soft-output value to maximum. Decoding is then restarted using the adjusted channel soft-output values.

Abstract: In one embodiment, a turbo equalizer has a channel detector that receives equalized samples and generates channel soft-output values. An LDPC decoder attempts to decode the channel soft-output values to recover an LDPC-encoded codeword. If the decoder converges on a trapping set, then an adjustment block selects one or more of the equalized samples based on one or more specified conditions and adjusts the selected equalized samples. Selection may be performed by identifying the locations of unsatisfied check nodes of the last local decoder iteration and selecting the equalized samples that correspond to bit nodes of the LDPC-encoded codeword that are connected to the unsatisfied check nodes. Adjustment of the equalized samples may be performed using any combination of scaling, offsetting, and saturation. Channel detection is then performed using the adjusted equalized samples to generate an updated set of channel soft-output values, which are subsequently decoded by the decoder.

Abstract: In one embodiment, a turbo equalizer has an LDPC decoder, a channel detector, and one or more adjustment blocks for recovering an LDPC codeword from a set of input samples. The decoder attempts to recover the codeword from an initial set of channel soft-output values and generates a set of extrinsic soft-output values, each corresponding to a bit of the codeword. If the decoder converges on a trapping set, then the channel detector performs detection on the set of input samples to generate a set of updated channel soft-output values, using the extrinsic soft-output values to improve the detection. The one or more adjustment blocks adjust at least one of (i) the extrinsic soft-output values before the channel detection and (ii) the updated channel soft-output values. Subsequent decoding is then performed on the updated and possibly-adjusted channel soft-output values to attempt to recover the codeword.

Abstract: In one embodiment, an LDPC decoder has one or more reconfigurable adders that generate variable-node messages and one or more reconfigurable check-node units (CNUs) that generate check-node messages. The LDPC decoder has a five-bit precision mode in which the reconfigurable adders and CNUs are configured to process five-bit variable-node and check-node messages, respectively. If the LDPC decoder is unable to properly decode codewords in five-bit precision mode, then the decoder can be reconfigured in real time into a ten-bit precision mode in which the reconfigurable adders and CNUs are configured to process ten-bit variable-node and check-node messages, respectively. By increasing the size of the variable-node and check-node messages from five bits to ten bits, the probability that the LDPC decoder will decode the codeword correctly may be increased.