Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values.

Abstract: A decoding method for low density generator matrix codes is disclosed, which decodes a bit information sequence that is transmitted after encoding with LDGC, the method comprises: S1: filling L?K known bits in a received code word sequence R and deleting code word symbols erased by a channel in R, and getting Re; S2: deleting rows corresponding to the code word symbols erased by a channel from a transposed matrix Gldgct of an LDGC generator matrix, and getting Ge; S3: obtaining It according to relation Ge×It=Re; S4: obtaining st according to relation Gldgct(0:L?1,0:L?1)×It=st, and getting an original information sequence of K bits by deleting the filled L?K known bits from st. The present disclosure can significantly reduce the storage overhead of a decoder, accelerate the decoding speed, and allow LDGC to be more smartly used in high speed communication systems.

Abstract: Systems, methods, and apparatus are provided for increasing decoding throughput in an LDPC decoder, such as in a wireless communications receiver or in a data retrieval unit. A checker-board parity check matrix and edge-based LDPC decoder structure are provided in which both vertical and horizontal processors are used simultaneously. Horizontal processors may be grouped into type-A and type-B horizontal processors, and similarly, vertical processors may be grouped into type-A and type-B vertical processors. Type-A processors may be used in different clock cycles than type-B processors to update memory locations in a decoding matrix without causing memory access conflicts.

Abstract: A method and apparatus for determining the reliability of decoded data in a communication system. The method includes calculating a total sum of absolute values corresponding to Log Likelihood Ratio (LLR) values of received data, generating a first value obtained by multiplying the total sum of the absolute values by a predetermined threshold value, performing iterative decoding with respect to the LLR values of the received data, generating a survived path metric value having a maximum value among all path metric values as a decoded result and generating decoded data, comparing the first value with the survived path metric value, and determining whether the decoded data has suitable reliability according to the compared result.

Abstract: A DTV transmitting system includes an encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizer randomizes the coded enhanced data, and the block processor codes the randomized data at an effective coding rate of 1/H. The group formatter forms a group of enhanced data having data regions, and inserts the coded enhanced data into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into corresponding data bytes.

Abstract: A decoding apparatus includes maximum decoding iteration count controller 52 which determines maximum decoding iteration counts of respective received code words based on modulation schemes and error-correcting coding ratios which are applied to the received code words and average error ratios of the received code words before the code words are decoded, and turbo decoding engine 53 which decodes each of the received code words according to a maximum decoding iteration count determined by maximum decoding iteration count controller 52.

Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.

Abstract: An execution decision apparatus decides whether to execute a detection process for a turbo equalization apparatus which detects data before coding, by repeating processes performed on transmission data coded by error correction coding, by an equalization unit for compensating distortion by a propagation path and a decoding unit for performing an error correction process, and includes an equalization unit I/O characteristic acquisition unit which acquires an I/O characteristic of the equalization unit; a decoding unit I/O characteristic acquisition unit which acquires an I/O characteristic of the decoding unit; and a decision unit which decides whether to execute the detection process in the turbo equalization apparatus based on the I/O characteristic acquired for each of the equalization unit and the decoding unit.

Abstract: Non-systematic (207, 187) Reed-Solomon codewords contain valuable information concerning the correctness of the outer convolutional coding of the serial concatenated convolutional coding (SCCC) used for transmitting digital television (DTV) data to mobile/handheld (M/H) receivers. M/H receivers are described that, before and during turbo decoding of the SCCC, decode (207, 187) Reed-Solomon (RS) coding of transport-stream packets encapsulating M/H DTV data. The results of the decoding the RS coding locate bytes in the outer convolutional coding of the SCCC very unlikely to be in error. The confidence levels of bits in those bytes are adjusted accordingly, so turbo decoding of the SCCC converges faster. In M/H receivers of preferred design, the results of decoding RS coded transport-stream packets are used to signal when such convergence is reached, to stop the iterative SCCC decoding procedures before a prescribed maximum number of iterations, thus to conserve operating power.

Abstract: Techniques for generating soft values for parity bits in a convolutional decoding process are disclosed. An exemplary method comprises, for each of at least one iteration in at least one soft-input soft-output decoder, calculating intermediate probability values for each possible transition between a first plurality of candidate decoder states at a first time and a second plurality of candidate decoder states at a second time. Two or more partial sums are then computed from the intermediate probability values, wherein the partial sums correspond to possible combinations of two or more systematic bits, two or more parity bits, or at least one systematic bit and at least one parity bit. Soft values, such as log-likelihood values, are then estimated for each of at least one systematic bit and at least one parity bit of the received communications data corresponding to the interval between the first and second times, based on the partial sums.

Abstract: An error detection unit performs erasure decoding for physical layer packets and an assembler assembles the received data into higher layer packets. Higher layer packets that are incomplete are not erased if the higher layer packets contain some data indicated as valid by the error detection unit. In the case of incomplete packets, the data is labeled by assigning a value to a reliability attribute for the data to enable the decoder to discriminate between valid and invalid data in the same packet. The decoder is modified to use “dimmed” data from the incomplete packets to perform decoding.

Abstract: A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such reliability information may be used to identify particular symbols with a higher likelihood of error such that these symbols may be changed in an attempt to reduce the total number of errors in the data. In an embodiment, a soft-decision ECC decoding path may include a reliability checker operable to receive bits of data read from a data store and operable to associate a reliability factor with each bit of data. Then, an update module may iteratively change bits or groups of bits based upon an ordering of the reliability factors.

Abstract: In one embodiment, a reconfigurable adder has first and second five-bit non-reconfigurable adders and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first non-reconfigurable adder adds first and second messages to generate a first sum, and the second non-reconfigurable adder adds third and fourth messages to generate a second sum. In ten-bit mode, the first non-reconfigurable adder adds a first half of a first ten-bit message and a first half of a second ten-bit message to generate a first partial sum and a carry-over bit. The second non-reconfigurable adder adds a second half of the first ten-bit message, a second half of the second ten-bit message, and the carry-over bit to generate a second partial sum. A ten-bit sum is then generated by combining the first and second partial sums.

Abstract: Aspects of a method and system for a method and system for a soft output Nordstrom-Robinson (NR) decoder may include one or more processors and/or circuits that are operable to more efficiently compute cross correlation values for a received soft output word based on a NR codebook in comparison to brute force computation approaches. Log likelihood ratios may be computed for each information bit corresponding to the received soft output word by determining corresponding maximum cross correlation values.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols.

Abstract: A chunk of branch metric computation bits is generated including bits that correspond to transition bits of a possible chunk of transition bits that could have been generated by a state transition of a convolutional encoder of a transmitter. The bits of the chunk of branch metric computation bits are scrambled. A branch metric for the received chunk of soft scrambled code bits is calculated as a function of the scrambled bits of the chunk of branch metric computation bits and the soft scrambled code bits of the received chunk of soft scrambled code bits. The branch metric is indicative of the probability that the received chunk of soft scrambled code bits was originally generated by the convolutional encoder as the chunk of transition bits corresponding to the generated chunk of branch metric computation bits.

Abstract: A device and method of determining candidates to decode by receiving a message, selecting m, identifying m voltages in message near zero volts, generating binary version of message, generating candidates that are variations of the binary message by varying the m positions, multiplying a modified binary message by the parity check matrix of the message, generating a matrix of the rows of the parity check matrix corresponding to the m positions, determining a rank v of the matrix, eliminating rows that are not linearly independent, determining if the sixth step result is in a span of the ninth step result, if so then there are 2m-1-2m-v(m?1) candidates, where the candidates can multiply the seventh step result to get the sixth step result and candidates with odd weights more than one Hamming distance from the candidates, otherwise there are 2m-1 candidates having odd weight.

Abstract: A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.

Abstract: A method of generating normalized bit log-likelihood ratio (LLR) values. A signal is received in a frequency band after transmission over a media, wherein the signal includes at least one complex data symbol having a plurality of information bits, and the complex data symbol is transmitted on at least one frequency channel. Initial LLR values are calculated for each of the plurality of information bits based on bit-to-symbol mapping of modulation and noise variance information from the complex data symbol. An average signal to noise ratio (SNR) of the frequency channel is calculated. Each initial LLR value is normalized by dividing by the average SNR to generate a plurality of normalized LLR values. The normalized LLR values may be quantized to provide a finite-bit representation.

Abstract: A method, apparatus and computer program product for providing partial packet recovery (PPR) for wireless networks is presented. PPR incorporates an expanded physical layer (PHY) interface that provides PHY-independent hints to higher layers about the PHY's confidence in each bit it decodes, and a technique to recover data even when a packet preamble is corrupted and not decodable at the receiver. Also described is an asynchronous link-layer automatic repeat request (ARQ) protocol built on PPR that allows a receiver to compactly encode a request for retransmission of only those bits in a packet that are likely in error.

Abstract: A soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reliability memory unit including at least four stages of logic units, each logic unit including a single buffer and at least four stages including a plurality of full stages comprising a separate logic unit corresponding to each of the plurality of states; and a plurality of compact stages including half or less than half the number of logic units than the number of the plurality of states, each logic unit corresponding to two of the plurality of states.

Abstract: In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low.

Abstract: Methods and systems are disclosed for decoding digital data received by a correspondent device over a communication channel. The data includes a component corresponding to a plurality of values unknown to the correspondent device and a component corresponding to one or more values known a priori by the correspondent device. To perform decoding, the correspondent device retrieves from memory at least one of the one or more known values. The correspondent device then applies a statistical measure using the known value(s) to estimate the location of the component corresponding to the one or more known values. The one or more known values and the estimated location of the component corresponding to the one or more known values are then used to assist in decoding the data.

Abstract: An apparatus for providing improved gray mapping may include a processor. The processor may be configured to divide gray value byte data into high priority portions and low priority portions distributed as constellation points in a constellation matrix and to provide separation between each of the constellation points by assigning a unique mapping code to a plurality of the constellation points.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of turbo decoding. For example, a device may include a turbo decoder to decode a turbo-encoded input according to a turbo code, the turbo-encoded input including a plurality of soft-decision information-bit values and a plurality of soft-decision parity-bit values corresponding to the soft-decision information bit values, wherein the turbo decoder is to output a plurality of extrinsic soft-decision parity-bit values corresponding to the plurality soft-decision parity-bit values. Other embodiments are described and claimed.

Abstract: An apparatus and method for transmitting and receiving symbols in a mobile communication system, in which a multiplexer and burst mapper divides each of first and second group data blocks into a plurality of sub-blocks, the symbols including the first group data block and the second group data block, the second group data block having a different priority level from the first group data block, and maps a combination of one of the first group data sub-blocks and one of the second group data sub-blocks to each burst. A modulator maps a bit of the first group data sub-block and a bit of the second group data sub-block to a symbol according to a bit reliability pattern of modulation symbols in each burst.

Abstract: A method for determining a contribution of burst noise to a bit error rate in a digital system for reception of an interleaved forward error correction-enabled digital symbol stream is described. The method is based on identifying errored symbols at a decoding stage, determining their positions in the interleaved stream, and performing a windowing operation such that the errored symbols located within the window in the interleaved stream are designated as burst errored symbols. A corresponding digital receiver and a digital transmission system are also disclosed.

Abstract: Various embodiments of the present invention provide systems and methods for out of order memory management. For example, a method for out of order data processing is disclosed. The method includes providing an out of order codeword memory circuit that includes a number of codeword memory locations in a codeword memory area and the same number of index values in an index area. Each of the index values corresponds to a respective one of the codeword memory locations. The methods further include receiving a data set; storing the data set to one of the codeword memory locations; receiving an indication that the data set stored in the one of the codeword memory locations has completed processing; and grouping an index value corresponding to the one of the codeword memory locations with one or more other index values corresponding to unused codeword memory locations.

Abstract: The invention relates to improving the performance of sequence-based soft-output decoders using event cleanup processing, wherein combinations of potential error events are evaluated using an error detection code (EDC) to select events that produce a modified set of decisions that has no EDC detectable errors. The event cleanup method and associated event cleanup decoder enable to significantly improve the error rate performance of sequence-based decoders and/or significantly improve decoding efficiency compared to other known error cleanup methods.

Abstract: Systems and methods are provided for enhancing the performance and throughput of a low-density parity check (LDPC) decoder. In some embodiments, the enhanced performance and throughput may be achieved by detecting and correcting near-codewords before the decoder iterates up to a predetermined number of iterations. In some embodiments, a corrector runs concurrently with the decoder to correct a near-codeword when the near-codeword is detected. In alternate embodiments, the corrector is active while the decoder is not active. Both embodiments allow for on-the-fly codeword error corrections that improve the performance (e.g., reducing the number of errors) without decreasing the throughput of the decoder.

Abstract: A method of decoding a received systematic code encoded block corresponding to an original block of information, wherein the received systematic code encoded block may include soft systematic values, may include detecting an error condition in the received systematic code encoded block. The method may also include decoding the received systematic code encoded block for retrieving the original block of information if the error condition in the received systematic code encoded block is detected and processing the soft systematic values to retrieve the original block of information instead of the decoding if the error condition in the received systematic code encoded block is not detected.

Abstract: Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information.

Abstract: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2t states. In a representative embodiment, the Non-ISI Meta-Viterbi detector performs ?+2t2t add, compare, and select operations.

Abstract: A method of decoding channel outputs using an iterative decoder to provide hard decisions on information bits includes activating each SISO decoder of the iterative decoder to provide soft-decisions associated with the information bits. The method also includes computing a fidelity estimate and stopping decoding based on the fidelity estimate.

Abstract: A soft decision device and method for obtaining a soft decision value as a value expressing a probability as near the actual probability as possible by simple processing. The soft decision device and method are used to output a soft decision value for each bit of each symbol used for decoding the each symbol as a value corresponding to the function value obtained by applying a predetermined function for each bit to the sampled value of the each symbol according to the demodulated signal such that the probability distribution of the sampled value in each symbol point is the Gauss distribution. The function for each bit is approximated to a curve expressing the probability that each bit is 1 or 0 for the sampled value of each symbol of the demodulated signal and defined by using a quadratic function.

Abstract: A method for controlling a message-passing algorithm (MPA) based decoding operation includes: gathering statistics data of syndromes obtained from executed iterations; and selectively adjusting a decoding operation in a next iteration to be executed according to the statistics data. A control apparatus for controlling an MPA based decoder includes an adjusting circuit and a detecting circuit. The detecting circuit is coupled to the adjusting circuit, and used for gathering statistics data of syndromes obtained from executed iterations, and selectively controlling the adjusting circuit to adjust a decoding operation in a next iteration to be executed according to the statistics data.

Abstract: A communication system that performs encoding and decoding for communication includes a transmitting apparatus and a receiving apparatus. The transmitting apparatus includes a turbo encoding unit including a first encoding unit that encodes an input signal and generates a first parity bit by bit-based encoding and n (n=1, 2, 3, . . . ) second encoding units that encode the input signal and generate second parity bits by bit-based encoding, and a symbol mapping unit that maps an output from the turbo encoding unit to a symbol by bit-based mapping operation and modulates the output. And the receiving apparatus includes a demodulating unit that demodulates a transmission signal, and a turbo decoding unit that performs turbo decoding on the demodulated signal by bit-based decoding.

Abstract: A method and apparatus of generating the soft value for a memory device is disclosed. Memory read-related parameters are set, and data are read out of the memory device according to the set parameters. The data reading is performed for pre-determined plural iterations, thereby obtaining the soft value according to the read-out data and the set parameters.

Abstract: Method and a receiver in a communication system for receiving a transport block. The transport block comprises code blocks, each of the code blocks includes an error detection code and an error correction code. Reliability metrics are determined using an input generated during processing of the code blocks after the transport block is received. Each of the reliability metrics corresponds to each of the code blocks. A code block reorderer reorders the code blocks in an order based on the reliability metrics and a selection criterion. A decoder decodes each of the code blocks using the error correction code in the order. A verifier verifies each of the decoded code blocks using the error detection code.

Abstract: In one embodiment, an LDPC decoder has one or more reconfigurable adders that generate variable-node messages and one or more reconfigurable check-node units (CNUs) that generate check-node messages. The LDPC decoder has a five-bit precision mode in which the reconfigurable adders and CNUs are configured to process five-bit variable-node and check-node messages, respectively. If the LDPC decoder is unable to properly decode codewords in five-bit precision mode, then the decoder can be reconfigured in real time into a ten-bit precision mode in which the reconfigurable adders and CNUs are configured to process ten-bit variable-node and check-node messages, respectively. By increasing the size of the variable-node and check-node messages from five bits to ten bits, the probability that the LDPC decoder will decode the codeword correctly may be increased.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: An embodiment is a method and apparatus to decode a signal using channel information. A channel state estimator generates a tone value representing channel information. A quantizer quantizes the tone value. A combiner combines de-interleaved symbols weighed by the quantized tone value. A comparator compares the combined de-interleaved symbols with a threshold to generate a decoding decision. Another embodiment is a method and apparatus to decode a signal using averaging. A channel estimator provides a channel estimate. A multiplier multiplies a quantized output of a demodulator with the channel estimate to produce N symbols of a signal corresponding to a carrier. A de-interleaver de-interleaves the N symbols. An averager averages the N de-interleaved symbols to generate a channel response at a carrier.

Abstract: In one embodiment, a reconfigurable minimum operator has two five-bit non-reconfigurable minimum operators and is selectively configurable to operate in a five- or ten-bit mode. In five-bit mode, the first non-reconfigurable minimum operator determines whether a first five-bit message is less than a second five-bit message, and the second non-reconfigurable minimum operator determines whether a third five-bit message is less than a fourth five-bit message. In ten-bit mode, the first non-reconfigurable minimum operator determines whether a first half of a first ten-bit message is less than a first half of a second ten-bit message, and the second non-reconfigurable minimum operator determines whether a second half of the first ten-bit message is less than a second half of the second ten-bit message. The reconfigurable minimum operator determines whether the first ten-bit message is less than the second ten-bit message based on the comparisons of the first and second non-reconfigurable minimum operators.

Abstract: A decoding device for a linear code on a ring R, the decoding device including: a plurality of storage media; and a processing section; wherein the processing section uses a part of reliability of all symbols at a previous time to update reliability of each symbol in a process of iterative decoding for increasing the reliability of each symbol, and further retains a part used to update retained reliability information and a part unused to update the retained reliability information on two separate storage media.

Abstract: Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode.

Abstract: In one embodiment, a reconfigurable two's-complement-to-sign-magnitude (2TSM) converter has two five-bit non-reconfigurable 2TSM converters and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second five-bit messages, respectively, from two's-complement-to-sign-magnitude format. In the ten-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second halves of a ten-bit message, respectively, from two's-complement-to-sign-magnitude format. The reconfigurable 2TSM converter then generates a ten-bit sign-magnitude message based on the conversions of the two non-reconfigurable 2TSM and a carry-over bit. In another embodiment, a reconfigurable sign-magnitude-to-two's-complement (SMT2) converter comprises the reconfigurable 2TSM described above.

Abstract: The invention provides a method of decoding a decided signal received from a decision circuit to supply a decoded signal, said method comprising: a step of detecting a word of N bits in said received decided signal to supply a detected word; a step of selecting an admissible word of N bits in a dictionary of the error correction code used for encoding in accordance with a criterion of the shortest distance between said detected word and said selected admissible word; and a step of decoding a word of L bits constituting said decoded signal from said selected admissible word. According to the invention, the distance used in the selection step takes account of the relative reliabilities of 2K sequences of K bits, 0<K<N.

Abstract: A sequence of data packets is received within an integrated circuit device and stored within a first memory thereof. Error descriptor values are updated within a second memory of the integrated circuit device based on error information associated with the sequence of data packets. The error descriptor values each include an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region. A sequence of multiple-bit error values are generated based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values. Concurrently with generation of at least one of the multiple-bit error values the state of one or more bits of the data values stored in the first memory based are changed based on a previously-generated one of the multiple-bit error values.

Abstract: Apparatus and methods are provided to decode signals from a communication channel to reconstruct transmitted information. Embodiments may include applying a plurality of decoders to a code, in which reliability values are provided to a decoder such that the decoder receives the reliability values determined by and provided from only one other decoder of the plurality of decoders. A valid codeword may be output from application of the plurality of decoders to the code.

Abstract: A system including a data detection module, a reconstruction filter module, a first correlation module, and a second correlation module, The data detection module detects data bits from input signals. The reconstruction filter module generates reconstructed signals using the data bits. The first correlation module correlates the input signals and the reconstructed signals and generates first correlation values. The second correlation module self-correlates the reconstructed signals and generates second correlation values. In response to at least one of the input signals and the reconstructed signals including a B-bit floating number having a sign bit, at least one of the first correlation module and the second correlation module generates the first correlation values and the second correlation values based on the sign bit and K most significant bits (MSBs) of the B-bit floating number, where 0 <K <(B-1), and B is an integer greater than 1.