Reed-solomon Code Patents (Class 714/784)
  • Patent number: 10387244
    Abstract: Error correction methods for arrays of resistive change elements are disclosed. An array of resistive change elements is organized into a plurality of subsections. Each subsection includes at least one flag bit and a plurality of data bits. At the start of a write operation, all bits in a subsection are initialized. If any data bits fail to initialize, the pattern of errors is compared to the input data pattern. The flag cells are then activated to indicate the appropriate encoding pattern to apply to the input data to match the errors. The input data is then encoded according to this encoding pattern before being written to the array. A second error correction algorithm can be used to correct remaining errors. During a read operation, the encoding pattern indicated by the flag bits is used to decode the read data and retrieve the original input data.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: August 20, 2019
    Assignee: Nantero, Inc.
    Inventor: Sheyang Ning
  • Patent number: 10382168
    Abstract: An error correction encoder (10) includes an interleaver circuit (31), encoding circuits (321, 322) and a deinterleaver circuit (33). The interleaver circuit (31) generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL1) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL1, IL2) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits (321, 322) apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL1) or the two series of yet-to-be-coded bit sequences (IL1, IL2).
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: August 13, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoshikuni Miyata, Kenya Sugihara, Hideo Yoshida
  • Patent number: 10341056
    Abstract: A decoding method in a mobile communication system using a non-binary LDPC code according to various embodiments of the present disclosure includes: selecting a message value having the highest reliability from each column and each row of an input vector message; generating a configuration set using the message value selected for each column and a GF element corresponding to the message value; and generating a check node output message using the generated configuration set and an extra output message value. According to various embodiments of the present disclosure, a decoding time period is reduced.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: July 2, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Min Kim, Woo-Myoung Park, Seok-Ki Ahn, Chi-Woo Lim
  • Patent number: 10326478
    Abstract: The disclosure relates to noiseless coding and, in particular, to the use of twisted polar code in data encoding and decoding. The disclosure increases the speed of encoding and/or decoding through the reduction in the number of iterations to be performed. The object is attained in method for encoding data, comprising the steps of: pre-coding, by a pre-coding module, data presented in the form of k-dimensional binary vector x, the pre-coding consists in computing u(0)=xW, where W is a matrix of dimension ?×2m, and m is a code parameter; performing, by the pre-coding module, m-layer twisted polarization transformation of vector u(0), wherein i-th transformation layer consists in partitioning vector u(i?1) into 2m?1 subvectors of length 2, multiplying the subvectors by matrix ( 1 0 1 1 ) , merging the resulting subvectors into one vector of dimension 2m.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Peter Vladimirovich Trifonov, Vera Dmitriyevna Miloslavskaya
  • Patent number: 10230399
    Abstract: Decoder circuitry for an input channel having a data rate, where a codeword on the input channel includes a plurality of symbols, includes options to provide a first output channel having that data rate, and a plurality of second output channels having slower data rates. The decoder circuitry includes syndrome calculation circuitry, polynomial calculation circuitry, and search-and-correct circuitry. The syndrome calculation circuitry includes finite-field multipliers for multiplying each symbol by a power of a root of the field. Each multiplier other than a first multiplier multiplies a symbol by a higher power of the root than an adjacent multiplier. First-level adders add outputs of a number of groups of multipliers. A second-level adder adds outputs of the first-level adders to be accumulated as syndromes of the first output channel. Another plurality of accumulators accumulates outputs of the first-level adders, which after scaling, are syndromes of the second output channels.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: March 12, 2019
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 10148426
    Abstract: Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256).
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Michael E. Kounavis, Shay Gueron, Ram Krishnamurthy, Sanu K. Mathew
  • Patent number: 10142419
    Abstract: In an illustrative example, a method includes receiving data that includes a set of data symbols. The method further includes generating a set of parity symbols based on the set of data symbols using an erasure correcting code. The set of parity symbols includes at least a first parity symbol that is generated based on a first proper subset of the set of data symbols. The first parity symbol enables recovery of a data symbol of the first proper subset independently of a second proper subset of the set of data symbols.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: November 27, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xinmiao Zhang, Steven Sprouse, Ishai Ilani
  • Patent number: 10120753
    Abstract: Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Chandra C. Varanasi
  • Patent number: 10051285
    Abstract: Methods and modules for spatial decorrelation and recorrelation are described. A block of data values can be spatially decorrelated in two dimensions efficiently by processing rows of the data values in a particular order such that if the results of spatially decorrelating a first row will be used for column-wise spatial decorrelation of a second row then the data values of the first row are processed in an earlier iteration to that in which the data values of the second row are processed. This allows for highly parallelised processing of the block of data values. Spatial recorrelation can be performed as an inverse process to the spatial decorrelation.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 14, 2018
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10050778
    Abstract: Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256).
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Michael E. Kounavis, Shay Gueron, Ram Krishnamurthy, Sanu K. Mathew
  • Patent number: 9996499
    Abstract: A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: June 12, 2018
    Assignee: Alcatel Lucent
    Inventors: Dusan Suvakovic, Adriaan J. de Lind van Wijngaarden, Man Fai Lau
  • Patent number: 9966972
    Abstract: Systems and methods described herein provides a method for dynamically allocating an iteration number for a decoder. The method includes receiving, at an input buffer, an input signal including at least one data packet. The method further includes calculating a first iteration number for decoding the at least one data packet. The method further includes monitoring at least one of available space of the input buffer and available decoding time for the at least one data packet. The method further includes dynamically adjusting the first iteration number to a second iteration number based on the available space or the available decoding time to continue decoding the at least one data packet.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: May 8, 2018
    Assignee: Marvell International Ltd.
    Inventors: Yan Zhong, Mao Yu
  • Patent number: 9924208
    Abstract: A method is described for transmitting broadcast signals. First encoding of first broadcast service data is performed. Second encoding of the first encoded first broadcast service data is performed. The broadcast signals having the second encoded first broadcast service data multiplexed with second broadcast service data are transmitted. Each of the second encoded first broadcast service data and the second broadcast service data is allocated in a different data unit. The second encoded first broadcast service data and the second broadcast service data are allocated in different data units, respectively. Different robustness are allocated to the first broadcast service data and the second broadcast service data.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: March 20, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Hyoung Gon Lee, In Hwan Choi, Kook Yeon Kwak, Jong Moon Kim, Won Gyu Song, Byoung Gill Kim, Jin Woo Kim
  • Patent number: 9912442
    Abstract: Data is received from a physical coding sublayer (PCS) of a physical layer, where the physical layer comprises a BASE-R physical layer. The data is used to generate a forward error correction (FEC) block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block. The FEC block is scrambled using a pseudo-noise sequence. The FEC block is sent to a physical medium attachment (PMA) sublayer of the physical layer.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Ilango S. Ganga, Luke Chang, Andrey Belogolovy, Andrei Ovchinnikov
  • Patent number: 9906842
    Abstract: Methods and apparatuses for enabling or disabling MTC mode operations for a plurality of CPE devices in a MAC domain are provided. A system operator can control enabling MTC mode operations for certain CPE devices capable of MTC mode operations in a MAC domain by setting a control attribute in a CMTS enabled for MTC mode operations for the MAC domain.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: February 27, 2018
    Assignee: ARRIS Enterprises LLC
    Inventors: Dwain E. Frieh, Ruth A. Cloonan, Dale Paney
  • Patent number: 9898392
    Abstract: A test automation tool detects a first set of parameters defining one or more software environments to be tested, where the first set of parameters includes at least a component to be tested. The test automation tool then identifies a general test plan, where the general test plan includes a first set of test cases, and where the first set of test cases are defined by the first set of parameters. The test automation tool detects a first set of test case relevancy rules for a first test case of the first set of test cases included in the general test plan. The test automation tool then creates an errata test plan based on the general test plan, where the errata test plan includes a second set of test cases.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 20, 2018
    Assignee: Red Hat, Inc.
    Inventors: Petr Splichal, Dalibor Pospisil, Milos Malik, Karel Srot, Ales Zelinka, Petr Muller
  • Patent number: 9860561
    Abstract: Methods and modules for spatial decorrelation and recorrelation are described. A block of data values can be spatially decorrelated in two dimensions efficiently by processing rows of the data values in a particular order such that if the results of spatially decorrelating a first row will be used for column-wise spatial decorrelation of a second row then the data values of the first row are processed in an earlier iteration to that in which the data values of the second row are processed. This allows for highly parallelised processing of the block of data values. Spatial recorrelation can be performed as an inverse process to the spatial decorrelation.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: January 2, 2018
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 9787327
    Abstract: A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: October 10, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xinmiao Zhang, Itai Dror
  • Patent number: 9787429
    Abstract: A device implementing a forward error correction data transmission system may include at least one processor circuit. The at least one processor circuit may be configured to perform line encoding on a data stream received from a media access control (MAC) module, and periodically insert alignment markers after every number of blocks of the data stream, where the alignment markers are determined based at least in part on a data rate of an associated port. The at least one processor circuit may be further configured to transcode the data stream, where each alignment marker remains contiguous in the transcoded data stream. The at least one processor circuit may be further configured to add parity information to the transcoded data stream. The at least one processor circuit may be further configured to transmit the transcoded data stream over at least one physical lane of the associated port.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: October 10, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Ankit Sajjan Kumar Bansal, Eric Allen Baden
  • Patent number: 9761325
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that performs programming and reading out with respect to the non -volatile memory, a code processor that generates a code word by encoding; and a controller that sets a threshold -voltage read level for determining whether a value of each bit in a received word read out from the non-volatile memory is “0” or “1”. A difference between the number of bits which have value equals “0” and the number of bits which have value equals “1” in the code word depends on a code rate of the encoding. The controller obtains the threshold-voltage read level based on the code rate.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: September 12, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Juan Shi, Hironori Uchikawa, Tokumasa Hara, Osamu Torii
  • Patent number: 9735845
    Abstract: The present document is for a wireless communication with reduced internal signaling burden in the distributed antenna system (DAS). In the proposed method, a user equipment (UE) receives a decoding unit, from the network, by multiple distributed unit (DUs) distributed within the UE, and decodes the decoding unit, at each of the multiple DUs. Each of the multiple DUs reports first information on the decoding result to a central unit (CU) controlling the multiple DUs, and the CU determines decoded bit values of the decoding unit based on the first information acquired from each of the multiple DUs.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: August 15, 2017
    Assignee: LG Electronics Inc.
    Inventors: Kyungmin Park, Jiwon Kang, Kitae Kim, Kilbom Lee, Heejin Kim
  • Patent number: 9729275
    Abstract: A method and apparatus are presented for transmitting broadcast signals. Service data is encoded by an encoder. A signaling encoder encodes signaling data based on a mode of the signaling data. The signaling data is categorized to one of plural modes based on a modulation order for the signaling data. A frame builder builds at least one signal frame including the encoded service data in at least one data symbol and the encoded signaling data in at least one signaling symbol. A modulator modulates data in the at least one signal frame by an Orthogonal Frequency Division Multiplex (OFDM) scheme. A transmitter transmits the broadcast signals carrying the modulated data in the at least one signal frame. The broadcast signals further carry a bootstrap. The bootstrap includes category information indicating the mode of the signaling data in the at least one signaling symbol in the at least one signal frame.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 8, 2017
    Assignee: LG Electronics Inc.
    Inventors: Jinwoo Kim, Jongwoong Shin, Woosuk Ko, Sungryong Hong
  • Patent number: 9564925
    Abstract: In one embodiment, a method includes loading first data into a first buffer of an interposer during a first time period and loading second data into a second buffer of the interposer and performing a first decoding operation on the first data using a first decoder during a second time period. The method includes loading third data into a third buffer of the interposer, performing the first decoding operation on the second data using the first decoder, and performing a second decoding operation on the first data using a second decoder during a third time period. Moreover, the method includes loading fourth data into a fourth buffer of the interposer, performing the first decoding operation on the third data using the first decoder, and performing the second decoding operation on the second data during a fourth time period. The first and second decoding operations are C1 or C2 decoding operations.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Bentley, Simeon Furrer, Robert A. Hutchins, Scott J. Schaffer, Keisuke Tanaka
  • Patent number: 9531405
    Abstract: A method and a system for estimating a parameter in a communication system are provided. The method includes estimating a parameter of a data channel model in a communication system, decoding a packet received through a determined noise channel to convert the packet into data indicating one of a success and failure of a reception of the packet, configuring a prototype channel having at least one unknown parameter, estimating the at least one unknown parameter using the data indicating the one of the success and the failure of the reception of the packet, and determining the size of a parity field of a forward error correction (FEC) symbol, using the estimated at least one unknown parameter.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: December 27, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Oleksandr Kanievskyi, Mykola Raievskyi, Oleg Kopysov, Roman Hush
  • Patent number: 9503127
    Abstract: Example apparatus and methods combine erasure coding with data deduplication to simultaneously reduce the overall redundancy in data while increasing the redundancy of unique data. In one embodiment, an efficient representation of a data set is produced by deduplication. The efficient representation reduces duplicate data in the data set. Redundancy is then added back into the data set using erasure coding. The redundancy that is added back in adds protection to the unique data associated with the efficient representation. How much redundancy is added back in and what type of redundancy is added back in may be controlled based on an attribute (e.g., value, reference count, symbol size, number of symbols) of the unique data. Decisions concerning how much and what type of redundancy to add back in may be adapted over time based, for example, on observations of the efficiency of the overall system.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: November 22, 2016
    Assignee: Quantum Corporation
    Inventors: Roderick B Wideman, Suayb Sefik Arslan, Jaewook Lee, Turguy Goker
  • Patent number: 9477540
    Abstract: A multi-stage codeword detector for detecting codewords from read signals received from a multi-level memory device, includes a first detection stage configured for a coarse detection of a first codeword from a received read signal; a second detection stage configured for a fine detection of a second codeword from the received read signal; and a deciding entity configured to decide on using the second detection stage for the received read signal in dependence on a reliability indicator indicating a certain reliability level of the received read signal.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Theodore Antonakopoulos, Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis
  • Patent number: 9448884
    Abstract: Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device. Coefficient data representing canonical coefficients can be pre-computed by an apparatus before the apparatus is provided with program data, for example. For example, coefficient data may be pre-computed external to the apparatus and stored before program data is provided to an apparatus.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: September 20, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Stephen P. Van Aken
  • Patent number: 9438274
    Abstract: A data processing block that includes a syndrome computation unit suitable for generating odd syndrome values in response to a received codeword, an ELP solver suitable for generating even syndrome values, based on the odd syndrome values in a first mode, and generating an error location polynomial, based on the odd syndrome values and the even syndrome values in a second mode, and a Chien search unit suitable for generating solutions of the error location polynomial.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: September 6, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sung Gun Cho
  • Patent number: 9438273
    Abstract: A method and apparatus for transmitting a Forward Error Correction (FEC) packet block including a plurality of FEC packets in a multimedia system are provided. The method includes generating a plurality of first FEC packet blocks by performing a first FEC encoding on a plurality of source symbols, each of the plurality of first FEC packet blocks including at least one source packet and at least one repair packet for repair of each of the at least one source packet, generating a second FEC packet block by performing a second FEC encoding on the plurality of first FEC packet blocks, the second FEC packet block including at least one repair packet for the plurality of first FEC packet blocks, and transmitting the second FEC packet block that includes, in header information of each of the at least one source packet and the at least one repair packet.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: September 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hee Hwang, Sung-Oh Hwang, Seho Myung, Hyun-Koo Yang, Kyung-Mo Park
  • Patent number: 9414110
    Abstract: The present invention concerns a system for transmitting a plurality of modes of digital television signals within the same transmission channel where one transmission mode is more robust than another mode. The present invention also concerns a system for receiving and decoding such signals. More specifically, an aspect of the present invention involves a method and an apparatus for utilizing a proper length of preamble data for the improvement of reception. Furthermore, another aspect of the present invention involves a method and an apparatus for inserting a preamble into a proper place in a transmitted data stream relative to the filed synchronization data. Another aspect of the present invention involves a method and an apparatus for decoding trellis-coded data, using the predetermined preamble data.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: August 9, 2016
    Assignee: THOMSON LICENSING
    Inventors: Richard W. Citta, David Emery Virag, Barth Alan Canfield, Scott Matthew Lopresto
  • Patent number: 9391641
    Abstract: A set of one or more component syndromes associated with a turbo product code (TPC) codeword is obtained from a component syndrome buffer. Component decoding is performed on the set of one or more component syndromes.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: July 12, 2016
    Assignee: SK Hynix Inc.
    Inventors: Arunkumar Subramanian, Naveen Kumar, Zheng Wu, Lingqi Zeng, Jason Bellorado
  • Patent number: 9337955
    Abstract: A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: May 10, 2016
    Assignee: Apple Inc.
    Inventors: Micha Anholt, Naftali Sommer
  • Patent number: 9331713
    Abstract: According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 3, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiki Saito, Shinichi Kanno, Toshikatsu Hida
  • Patent number: 9294830
    Abstract: A system that includes a bus, a battery, core processing circuitry, radio frequency (RF) processing circuitry, first power regulating circuitry, second power regulating circuitry, and control circuitry is provided. The bus can be coupled to receive power from a source external to the system. The core processing circuitry and RF processing circuitry can be selectively coupled to each other via a switch. The switch can be operative to turn ON and OFF based on a signal level received on the bus. The first power regulating circuitry can be electrically coupled to the bus, the core processing circuitry, and the switch. The second power regulating circuitry can be electrically coupled to the battery, the RF processing circuitry, and the switch. The control circuitry can be operative to selectively turn ON and OFF the first power regulating circuitry and the second power regulating circuitry based on a number of monitored conditions.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: March 22, 2016
    Assignee: Apple Inc.
    Inventor: Jeffrey J. Terlizzi
  • Patent number: 9244765
    Abstract: A memory device (e.g., a flash memory device) includes power efficient codeword error analysis circuitry. The circuitry analyzes codewords stored in the memory of the memory device to locate and correct errors in the codewords before the codewords are communicated to a host device that requests the codewords from the memory device. The circuitry includes a highly parallel configuration with reduced complexity (e.g., reduced gate count) that a controller may cause to perform the error analysis under most circumstances. The circuitry also includes an analysis section of greater complexity with a less parallel configuration that the controller may cause to perform the error analysis less frequently. Because the more complex analysis section runs less frequently, the error analysis circuitry may provide significant power consumption savings in comparison to prior designs for error analysis circuitry.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: January 26, 2016
    Assignee: SanDisk IL Ltd.
    Inventor: Itai Dror
  • Patent number: 9236976
    Abstract: A method of encoding data for transmission from a source to a destination over a communications channel is provided. A plurality of redundant symbols are generated from an ordered set of input symbols to be transmitted. A plurality of output symbols are generated from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much larger than the number of symbols in the combined set of symbols, wherein at least one output symbol is generated from more than one symbol in the combined set of symbols and from less than all of the symbols in the combined set of symbols, and such that the ordered set of input symbols can be regenerated to a desired degree of accuracy from any predetermined number, N, of the output symbols.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: January 12, 2016
    Assignee: Digital Fountain, Inc.
    Inventors: M. Amin Shokrollahi, Soren Lassen, Michael G. Luby
  • Patent number: 9235540
    Abstract: Systems, methods, apparatus, and techniques relating to a transmitter interface are disclosed. A soft-IP transmitter interface includes a Reed-Solomon encoder operating according to any one of multiple bus width and bandwidth parameter pairs, and a gearbox module that includes multiple gearboxes. The multiple gearboxes receive input data at a bus width and clock rate parameter pair specified by the soft-IP transmitter interface and convert the input data into output data according to a number of physical lanes and bandwidth parameter pair specified by a physical medium attachment (PMA) standard.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: January 12, 2016
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Haiyun Yang, Peng Li
  • Patent number: 9191060
    Abstract: Signal processing, data encoding and/or decoding techniques are applied in a dictionary system. A dictionary is generated as a function of time shift and phase shift distortion. Atoms of the dictionary can be determined. Further, parameters of the dictionary can be flexibly chosen. In one aspect, signals can be processed as a function of the dictionary.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: November 17, 2015
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventor: Maosheng Xiong
  • Patent number: 9178732
    Abstract: Systems and methodologies are described that facilitate transmitting beacon symbols of a beacon message such that a sequence of symbols can satisfy a linear constraint over a field where the field elements can be identified with carriers. In this regard, a coding scheme can be applied to a beacon message; the coding scheme can produce a plurality of beacon symbols to transmit on given subcarriers. A receiving device of the beacon symbols can decode a beacon message by receiving less than the total number of symbols in a beacon message and determining the remaining symbol subcarriers based on the linear constraint. Thus, more efficient decoding of beacons is facilitated as well as resolving beacon ambiguity by figuring out which symbols satisfy linear constraints for the symbols, and resolving time and frequency shift by detecting an offset that would result in satisfaction of the linear constraint.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: November 3, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Richardson, Husheng Li, Junyi Li, Alexander Leonidov, Rajiv Laroia, Ravi Palanki, Gavin Horn, Ashwin Sampath
  • Patent number: 9141478
    Abstract: In one embodiment, a method for assembling data from a medium includes reading a data set from the medium repeatedly using different settings until either: a reconstructed data set is obtained, or a maximum number of rereads has been reached, the data set including a plurality of sub data sets, each sub data set having a plurality of rows, and after each reread of the data set, good rows of data are stored to iteratively construct a good data set from a plurality of good rows as determined by C1 and/or C2 error correction code (ECC).
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: September 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Takashi Katagiri, Pamela R. Nylander-Hill, Keisuke Tanaka
  • Patent number: 9130592
    Abstract: The ECC circuit includes a Chien search unit configured to determine whether there is an error in each bit of a data sequence. The Chien search unit selects a coefficient of a nonlinear term from among terms of an error locator polynomial as a nonlinear coefficient, separates the error locator polynomial into a first location equation including only linear terms and a second location equation including only nonlinear terms, determines a third location equation by dividing the first location equation by the nonlinear coefficient, determines a fourth location equation by dividing the second location equation by the nonlinear coefficient, and determines whether there is an error for each of the bits by performing an XOR operation on a result of the third location equation using the substitution value and a result of the fourth location equation using an arbitrary element of the error locator polynomial as a substitution value.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: September 8, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Daisuke Fujiwara
  • Patent number: 9118349
    Abstract: Circuitry for, in p parallel streams, searching a codeword having n symbols for roots of a cyclic code polynomial having a number of terms includes a plurality of multipliers, a source of constants derived from roots of the polynomial, and at least one counter that supplies an index. For each received symbol of the codeword, the multipliers multiply respective terms of the polynomial for a previous received symbol by constants from the source of constants, the counter advances to select respective products of the constants and the respective terms for the previous received symbol.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: August 25, 2015
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 9116822
    Abstract: The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: August 25, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mustafa N. Kaynak, William H. Radke, Patrick R. Khayat, Sivagnanam Parthasarathy
  • Patent number: 9118964
    Abstract: A broadcast receiving apparatus is disclosed. The broadcast receiving apparatus includes a receiver configured to receive a broadcast signal which includes video data; a detector configured to detect error information for determining whether there is an error in a packet identifier information, regarding the video data and correction information for correcting the packet identifier information; and a controller configured to detect the packet identifier information using the correction information, and detect the video data using the corrected packet identifier information, when it is determined that the error occurs in the packet identifier information.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: August 25, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hwan-sung Park
  • Patent number: 9112757
    Abstract: An identification provider provides predetermined identification data to an input signal, and generates a first signal. A differential encoder performs a differential encoding of a data series that is an aggregate of data having a matching number of elements to that contained in the first signal, and generates a second signal. A modulator modulates each of the first and second signals using a primary modulation, and generates first and second modulated data. An IFFT calculator performs an inverse fast Fourier transformation on each of the first and second modulated data, and generates first and second inverse transformed data. A selector compares peak-to-average power ratios calculated by baseband signals associated with the first and second inverse transformed data, and selects a baseband signal having the lower peak-to-average power ratio. A transmitter generates a transmission signal based on the selected baseband signal, and transmits the transmission signal.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 18, 2015
    Assignee: ICOM INCORPORATED
    Inventor: Nobuyoshi Nishikawa
  • Patent number: 9106349
    Abstract: A digital broadcasting system which is robust against an error when mobile service data is transmitted and a method of processing data are disclosed. The mobile service data is subjected to an additional coding process and the coded mobile service data is transmitted. Accordingly, it is possible to cope with a serious channel variation while applying robustness to the mobile service data.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: August 11, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Hyen O Oh, In Hwan Choi, Kook Yeon Kwak, Byoung Gill Kim, Won Gyu Song, Jin Woo Kim, Hyoung Gon Lee
  • Patent number: 9094159
    Abstract: A broadcast transmitting system and method are provided. The method includes performing RS encoding and CRC encoding on mobile service data bytes to build an RS frame, dividing the RS frame into a plurality of portions, adding K bytes of dummy data to one of the portions, converting data bytes of the plurality of portions into data bits, encoding each of the data bits to output data symbols, interleaving the data symbols, converting the interleaved data symbols into data bytes, forming data groups, inserting a plurality of known data sequences in each data group, deinterleaving data of the data groups, RS encoding mobile service data packets to insert first RS parity data in the data packets, interleaving data of the RS-encoded data packets, trellis encoding the interleaved data, recalculating second RS parity data based on initialization data and replacing the first RS parity data with the second RS parity data.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: July 28, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: In Hwan Choi, Kook Yeon Kwak, Byoung Gill Kim, Jin Woo Kim, Hyoung Gon Lee, Won Gyu Song
  • Patent number: 9081752
    Abstract: A method is provided of encoding data within a RAID stripe, the RAID stripe being spread across k data disks and r redundancy disks of a RAID group, r?3, the RAID group having k+r disks, the k data disks and the r redundancy disks within the RAID stripe being distinct, such that, upon failure of any r disks of the k+r disks of the RAID group, the data can be fully recovered using the Forney algorithm. The method includes (a) partitioning the data into k data symbols, (b) storing each of the k data symbols to a respective data disk of the k data disks, (c) generating r Reed-Solomon redundancy symbols by applying the Forney algorithm to the k data symbols, and (d) storing each of the r Reed-Solomon redundancy symbols generated by the Forney algorithm to a respective redundancy disk of the r redundancy disks.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: July 14, 2015
    Assignee: EMC Corporation
    Inventors: Artem Alexandrovich Aliev, Peter Vladimirovich Trifonov
  • Patent number: 9069692
    Abstract: A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: June 30, 2015
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chia-Ching Chu, Yi-Min Lin, Chi-Heng Yang, Hsie-Chia Chang
  • Patent number: 9064028
    Abstract: Webpages configured for display on a full-sized screen such as a computer monitor (111) are reconfigured for use with a mobile device in accordance with a user's preferences. A custom rendering tool engages the user in customizing the webpage in order to render the webpage information suitable for display on a mobile device. A browser toolbar is used, by which the user may highlight a section of interest section (121) from a webpage and save the customization information. A proxy server receives the customization information and uses the information to accurately retrieve the sections of interest later, even after the webpage or the section has been updated.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: June 23, 2015
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Vincent Yun Shen Shen, Benfeng Chen, Dan Hong, Kwok Chu Lo, Yongzhen Zhuang