Abstract: A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

Abstract: Data may be distributed using data carousels. After a device receives the data, or a portion thereof, the device may make available a data carousel that allows others to receive the data. Each data carousel may contain a portion of the data. Data carousels may also contain error correction information that can be used to reconstruct missing portions of the data being distributed. A carousel directory may keep track of the carousel structure and direct the behavior of devices that are receiving data and/or distributing data.

Abstract: Data may be distributed using data carousels. After a device receives the data, or a portion thereof, the device may make available a data carousel that allows others to receive the data. Each data carousel may contain a portion of the data. Data carousels may also contain error correction information that can be used to reconstruct missing portions of the data being distributed. A carousel directory may keep track of the carousel structure and direct the behavior of devices that are receiving data and/or distributing data.

Abstract: A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction and expanding the FEC-coded enhanced data. The packet generator generates enhanced data packets including the pre-processed enhanced data and main data packets and multiplexes the enhanced and main data packets. Each enhanced data packet includes an adaptation field in which the pre-processed enhanced data are inserted. The RS encoder performs RS encoding on the multiplexed data packets for second forward error correction, and the trellis encoder performs trellis encoding on the RS-coded data packets.

Abstract: Systems and methods for protecting DSL systems against impulse noise are provided. Disclosed herein are example embodiments of a retransmission technique located above the gamma interface (i.e., in the network processing layer). Such a retransmission technique can be combined with standard RS coding with standard erasure-decoding & triangular interleaving at the PMS-TC layer. Example embodiments of the technique involve using the RS code to protect against REIN noise, and using ?-layer retransmission for protecting against error events not corrected by the RS code, e.g. a SHINE noise in the presence of REIN. Both techniques are used jointly in the case of combined REIN and SHINE noise.

Abstract: A system including a detection module, a reconstruction module, and a correlation module. The detection module receives first signals from a medium and detects data bits from the first signals. The reconstruction module reconstructs the data bits and generates second signals. The correlation module generates first correlation values by correlating the first and second signals and generates second correlation values by self-correlating the second signals. In response to at least one of the first and second signals including a floating number having a plurality of bits and a sign bit, the correlation module generates at least one of the first and second correlation values based on a plurality of most significant bits of the floating number and the sign bit of the floating number. The first and second correlation values indicate whether the data bits detected from the first signals include errors due to defects in the medium.

Abstract: Configurable permutators in an LDPC decoder are provided. A partially-parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multi-mode function. To overcome the difficulty in efficient implementation of a high-throughput decoder, the variable nodes are partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and, hence, increase the maximum operating frequency. In addition, shuffled message-passing decoding can be adopted in decoders according to the invention to increase the convergence speed, which reduces the number of iterations required to achieve a given bit-error-rate performance.

Abstract: A system and method for performing cryptographic functions in hardware using read-N keys comprising a cryptographic core, seed register, physically unclonable function (PUF), an error-correction core, a decryption register, and an encryption register. The PUF configured to receive a seed value as an input to generate a key as an output. The error-correction core configured to transmit the key to the cryptographic core. The encryption register and decryption register configured to receive the seed value and the output. The system, a PUF ROK, configured to generate keys that are used N times to perform cryptographic functions.

Abstract: A digital broadcasting system and method of processing data therein are disclosed. According to one embodiment, a digital broadcasting system includes an RS (Reed-Solomon) encoder configured to encode mobile service data for FEC (Forward Error Correction) to build RS frames including the mobile service data and a signaling information table, a signaling encoder configured to encode signaling information including fast information channel (FIC) data, and transmission parameter channel (TPC) data, a group formatter configured to form data groups, wherein at least one of the data groups includes encoded mobile service data, known data sequences, the FIC data and the TPC data, and a transmission unit configured to transmit the broadcast signal including a parade of the data groups.

Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmuted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract: A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: Systems and methods are provided for implementing error identification and evaluation for a Reed-Solomon (RS) error-correction code (ECC) system. The BMA algorithm and/or list decoding may produce one or more error locator polynomials that are related to a decision-codeword. An accelerated Chien search can be used to more quickly evaluate the one or more error locator polynomial. If the accelerated Chien search identifies a valid error locator polynomial, a normal Chien search can be used to identify error locations, and Forney's algorithm or an equivalent technique can be used to evaluate the error values. A RS ECC decoder can include a computation circuit that evaluates an error locator polynomial or an error evaluator polynomial. The computation circuit can include computation components that receive the coefficients of the polynomials.

Abstract: The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.—unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output.

Abstract: An error detection module includes a known-syndrome computing unit, an unknown-syndrome computing unit, and an error detection unit. The known-syndrome computing unit is operable to convert a received signal into a target signal, to obtain known syndromes based upon the target signal, and to generate an errata-locator polynomial based upon an erasure-locator polynomial and the known syndromes. The unknown-syndrome computing unit is operable to compute unknown syndromes based upon the errata-locator polynomial and the known syndromes. The error detection unit is operable to obtain a syndrome set that includes the known syndromes and the unknown syndromes, to obtain an error detection signal according to the syndrome set, and to provide an error correction module coupled thereto with the syndrome set and the error detection signal for enabling the error correction module to correct an error of the received signal.

Abstract: Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.

Abstract: Embodiments disclosed herein relate to preamble configuration in wireless communication systems (e.g., UHDR-DO type systems). Disclosed embodiments disclose receiving a plurality of information bits, generating a plurality of preamble codewords based on a determined a set of monitored MAC_IDs, correlating the information bits with each of the plurality of preamble codewords, determining if a maximum correlation value exceeds a threshold, and transmitting at least one of the preamble codewords if the threshold is exceeded.

Abstract: Embodiments of the invention describe a dynamic read reference voltage for use in reading data from non-volatile memory cells. In embodiments of the invention, the read reference voltage is calibrated as the non-volatile memory device is used. Embodiments of the invention may comprise of logic and or modules to read data from a plurality of non-volatile memory cells using a first read reference voltage level (e.g., an initial read reference voltage level whose value is determined by the non-volatile device manufacturer). An Error Checking and Correction (ECC) algorithm is performed to identify whether errors exist in the data as read using the first read reference voltage level. If errors in the data as read are identified, a pre-determined value is retrieved to adjust the first read reference voltage level to a second read reference voltage level.

Abstract: Methods include receiving data and an ECC code read from a memory array, generating an ECC code from the received data, and determining whether the received data is corrupted by evaluating the generated ECC code against the ECC code read from the memory array. If the received data is determined to be corrupted, a correction algorithm and a recorded likely state of a known bad/questionable bit of the received data may be used to correct error in the received data. Alternatively, if the received data is determined to be corrupted, the correction algorithm and a recorded location of a known bad/questionable bit of the received data may be used to correct error in the received data.

Abstract: Storing data includes encoding the data using an erasure encoding to provide encoded data, separating the encoded data into a number of components, and providing each of the components to separate data sites. The data may be encoded using a Reed/Solomon encoding. The data may be encoded using a 3-1 Reed/Solomon encoding and the encoded data may be separated into four components that are provided to four separate sites. The data may be encoded by a site that receives the data prior to encoding. The data may be encoded by a client that provides the data to a plurality of sites coupled thereto. Storing data may also include each of the separate data sites providing an additional encoding for the components. The data and the components may be encoded using a Reed/Solomon encoding.

Abstract: A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.

Abstract: A method of processing a digital broadcast signal is provided. Signaling data for signaling of mobile service data is encoded. Data groups are formed, the data groups including a first data group, a second data group and a third data group. The digital broadcast signal including the data groups is transmitted, the signaling data including first information indicating whether a segmented known data sequence of the second data group is concatenated to a segmented known data sequence of the first data group to form a known data sequence, and/or second information indicating whether a segmented known data sequence of the second data group is concatenated to a segmented known data sequence of the third data group to form a known data sequence.

Abstract: A transmitter is capable of performing both Galois Field (GF) (16) and GF (256) encoding in a visual light communication system. The transmitter includes a GF (256) encoder. The transmitter also includes a first bit mapper configured to map a first number of bits to a second number of bits. The Galois Field (256) encoder is configured to receive and encode the second number of bits. The transmitter also includes a second bit mapper configured to map the second number of bits to the first number of bits. The transmitter also includes an interleaver unit that can pad bits based on a frame size and puncture the bits after interleaving and prior to transmission.

Abstract: Systems, methods and computer program products for facilitating the recovery of lost real-time media packets within a computer network real-time application implementing Forward Error Control (FEC), such that server performance is not affected from a CPU and memory perspective, are disclosed. In an embodiment, a conference server that is part of a communication network compliant with the Real Time Transport Protocol (RTP) is able to avoid regenerating FEC packets by not performing any FEC coding operation on the packets unless it is flagged to indicate regeneration via an FEC (e.g., Reed-Solomon) coding is necessary. Absent the flag, the conference server updates the received FEC packet as per the RTP and transmits the packet to its ultimate destination. Such disclosed systems, methods and computer program products are independent of the nature of the media being protected and flexible enough to support a wide variety of FEC techniques.

Abstract: A method for integrating data and header protection in tape drives includes receiving an array of data organized into rows and columns. The array is extended to include one or more headers for each row of data in the array. The method provides two dimensions of error correction code (ECC) protection for the data in the array and a single dimension of ECC protection for the headers in the array. A corresponding apparatus is also disclosed herein.

Abstract: Header encoding for SC and/or OFDM signaling using shortening, puncturing, and/or repetition in accordance with encoding header information within a frame to be transmitted via a communication channel employs different respective puncturing patterns as applied to different portions thereof. For example, a first puncturing pattern is applied to a first portion of the frame, and a second puncturing pattern is applied to a second portion of the frame (the second portion may be a repeated version of the first portion). Shortening (e.g., by padding 0-valued bits thereto) may be made to header information bits before they undergo encoding (e.g., in an LDPC encoder). One or both of the information bits and parity/redundancy bits output from the encoder undergo selective puncturing. Moreover, one or both of the information bits and parity/redundancy bits output from the encoder may be repeated/spread before undergoing selective puncturing to generate a header.

Abstract: An apparatus and a method for packet error correction in packet-switched networks is provided. Message packets to be transmitted on a network are subdivided into k symbols over GF(q), and the symbols are then encoded by a symbol-level encoder into a codeword of n>k symbols over GF(q). The codeword is transmitted on the network in a plurality of network packets to a symbol-level decoder, which recovers any symbols lost or corrupted in transmission. Encoding at the symbol level increases the amount of data that can be recovered in any single correction operation. The efficiency of the decoding is also enhanced because the location of symbol errors can be determined prior to decoding.

Abstract: A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

Abstract: Embodiments in accordance with the invention utilize Reed Solomon (RS) forward error correction (FEC) coding in conjunction with M-ary Bandwidth Efficient Modulation (BEM) schemes and soft decision decoding to improve the robustness of high spectral efficiency communications links. In one embodiment, information symbols in communication data blocks are encoded utilizing Reed Solomon (RS) forward error correction (FEC) coding and transmitted with either M-ary phase shift keying (MPSK) or M-ary quadrature amplitude modulation (MQAM). Using standard Reed Solomon (RS) hard decision decoding, a receiver either correctly decodes the received block or returns a decoding failure. In the event of a decoding failure, soft decision reliability information is used to identify received code symbols with a low probability of being correctly received and to generate new code symbol estimates that are used in the traditional Reed Solomon decoding algorithm.

Abstract: An error detection and correction system in accordance with an embodiment comprises: an encoding unit; a syndrome calculating unit; a syndrome element calculating unit; an error search unit; and an error correction unit, read and write of a memory cell array being assumed to be performed concurrently for m bits, and error detection and correction being assumed to be performed in data units of M bits (where M is an integer multiple of m), and an encoding unit and a syndrome calculating unit sharing a time-division decoder for performing data bit selection according to respective tables of check bit generation and syndrome generation, the time-division decoder being operative to repeat multiple cycles of m bit concurrent data input.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for optimizing the size of memory devices used for error correction code storage. An apparatus (such as a memory module) may include a number of memory devices to store data and a memory device to store error correction (ECC) bits. In some embodiments, the memory devices to store data may have a density of N and the memory device to store ECC bits has a density of ½ N.

Abstract: The invention provides a method for encoding and decoding an error correction code. First, raw data is received and then divided into a plurality of data segments. A plurality of short parities corresponding to the data segments is then generated according to a first generator polynomial. The short parities are then appended to the data segments to obtain a plurality of short codewords. The short codewords are then concatenated to obtain a code data. A long parity corresponding to the code data is then generated according to a second generator polynomial, wherein the first generator polynomial is a function of at least one minimum polynomial of the second generator polynomial. Finally, the long parity is then appended to the code data to obtain a long codeword as an error correction code corresponding to the raw data.

Abstract: The invention discloses a data transfer protection apparatus for a flash memory controller, placed between Bose-Chaudhuri-Hocquenghem (BCH) and NAND Flash Chip. In encode path the hardware module selects a sequence of constant values, exclusive-or the original parity with that constant value. In decode path the hardware module detects the parity period, exclusive-or the parity which is read out from NAND Flash Chip with the same constant value sequence.

Abstract: An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p?k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude or error value are determined. The error is corrected by the processor.

Abstract: A transport stream generating apparatus, a turbo packet demultiplexing apparatus, and methods thereof, the transport stream generating apparatus including: a Reed Solomon (RS) encoder to RS-encode turbo data, an interleaver to interleave the RS-encoded turbo data, a duplicator to add a parity insertion area to the interleaved turbo data, and a multiplexer to multiplex normal data and the turbo data processed by the duplicator to generate a transport stream. Accordingly, reception performance can be improved in an advanced vestigial sideband (AVSB) system.

Abstract: A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

Abstract: A method and an apparatus that has Chien search capabilities, the apparatus includes a first hardware circuit and a second hardware circuit. The first hardware circuit evaluates an error locator polynomial for a first element of a finite field over which the error locator polynomial is defined to provide a first set of intermediate results and a first Chien search result and provides the first set of intermediate results to the second hardware circuit; the second hardware circuit evaluates the error locator polynomial for a second element of the finite field to provide a second Chien search result in response to the first set of intermediate results. The first hardware circuit may be substantially bigger than the second hardware circuit and the first element may differ from the second element.

Abstract: Embodiments of the present invention provide a read channel including a front end to receive an optical image, convert the optical image into multi-bit soft information, and to serially transmit the multi-bit soft information to other components of the read channel. Other embodiments may be described and claimed.

Abstract: Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additionally, various methods, apparatus, systems, and data structures may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.

Abstract: A DTV transmitting system includes a first pre-processor for coding first enhanced data having a high priority for forward error correction (FEC) at a first coding rate and expanding the first enhanced data at a first expansion rate, and a second pre-processor for coding second enhanced data having a low priority for FEC at a second coding rate and expanding the second enhanced data at a second expansion rate. The receiving system further includes a data formatter for generating enhanced data packets, a multiplexer for multiplexing the enhanced data packets with main data packets, an RS encoder for RS-coding the multiplexed data packets, and a data interleaver for interleaving the RS-coded data packets and outputting a group of interleaved data packets having a head, a body, and a tail.

Abstract: Methods and apparatuses for Bose-Chaudhuri-Hocquenghem (BCH) decoding utilizing Berlekamp-Massey Algorithm (BMA) and Chien Search. The BMA may utilize one or more of a scalable semi-parallel shared multiplier array, a conditional q-ary inversionless BMA and/or a conditional binary Inversionless BMA. The Chien Search may be accomplished utilizing a non-rectangular multiplier array.

Abstract: A DTV transmitting system includes an encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizer randomizes the coded enhanced data, and the block processor codes the randomized data at an effective coding rate of 1/H. The group formatter forms a group of enhanced data having data regions, and inserts the coded enhanced data into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into corresponding data bytes.

Abstract: One or more methods and systems of effectively retrieving data stored in a media of a storage device are presented. The one or more methods and systems are implemented by way of correcting and detecting errors using a multi-stage decoding process. In one embodiment, the storage device comprises a magnetic hard drive. In one embodiment, the system and method applies an encoding/decoding technique that allows error correction and detection to be performed over a number of successive decode stages or processing stages. Use of the system and method increases the maximum number of symbol errors that may be corrected in an encoded codeword, providing an improvement in data recovery.

Abstract: Various embodiments of the present invention provide systems and methods for decoding data in a non-binary LDPC decoder with targeted symbol flipping. For example, a non-binary low density parity check data decoder is disclosed that comprises a variable node processor operable to update variable node symbol values according to a plurality of elements in a non-binary Galois Field, a check node processor connected to the variable node processor and operable to perform parity check calculations, and a controller operable to perform symbol flipping and to control decoding iterations in the variable node processor and the check node processor.

Abstract: Low latency and computationally efficient techniques may be employed to account for errors in data such as low bit-width, oversampled data. In some aspects these techniques may be employed to mitigate audio artifacts associated with sigma-delta modulated audio data. In some aspects an error may be detected in a set of encoded data based on an outcome of a channel decoding process. Upon determining that a set of data may contain at least one error, the set of data may be replaced with another set of data that is based on one or more neighboring data sets. For example, in some aspects a set of data including at least one bit in error may be replaced with data that is generated by applying a cross-fading operation to neighboring data sets. In some aspects a given data bit may be flipped as a result of a linear prediction operation that is applied to PCM equivalent data that is associated with the given data bit and its neighboring data bits.

Abstract: Provided is a terrestrial digital broadcasting transmitter. The terrestrial digital broadcasting transmitter may include a Reed-Solomon (RS) encoder to RS-encode an inputted broadcast signal, a forward error correction (FEC) encoder to channel-encode an inputted additional signal associated with the broadcast signal, a selector to select the RS-encoded broadcast signal or the channel-encoded additional signal, and a vestigial side band (VSB) transmitting part to transmit, to a receiver via a transmitting antenna, the selected signal, the selected signal being the RS-encoded broadcast signal or the channel-encoded additional signal selected by the selector.

Abstract: A decoding method of an MPE-FEC (MultiProtocol Encapsulation-Forward Error Correction) RS (Reed-Solomon) decoder, includes: substituting a value corresponding to an erasure error position with 0 in a reception signal; calculating a syndrome by using the reception signal; calculating an erasure position polynomial by using erasure information; calculating a modified syndrome by using the syndrome and the erasure position polynomial; calculating an erasure error size polynomial by using the modified syndrome; calculating an error position by using the erasure position polynomial; calculating an error size by using a modified Forney's algorithm; and correcting an error through the error position and the error size.

Abstract: Non-systematic (207, 187) Reed-Solomon codewords contain valuable information concerning the correctness of the outer convolutional coding of the serial concatenated convolutional coding (SCCC) used for transmitting digital television (DTV) data to mobile/handheld (M/H) receivers. M/H receivers are described that, before and during turbo decoding of the SCCC, decode (207, 187) Reed-Solomon (RS) coding of transport-stream packets encapsulating M/H DTV data. The results of the decoding the RS coding locate bytes in the outer convolutional coding of the SCCC very unlikely to be in error. The confidence levels of bits in those bytes are adjusted accordingly, so turbo decoding of the SCCC converges faster. In M/H receivers of preferred design, the results of decoding RS coded transport-stream packets are used to signal when such convergence is reached, to stop the iterative SCCC decoding procedures before a prescribed maximum number of iterations, thus to conserve operating power.

Abstract: A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction.

Abstract: A system and method for encoding information is disclosed. In one embodiment, information is encoded using a high protection code for the least significant bit and a low protection code for the next three most significant bits. The remaining bits are uncoded. The high protection code may be a turbo code and the low protection code may be a trellis coded modulation code. In this embodiment, the collection of bits is then mapped according to a diagonally shifted QAM constellation technique.