Abstract: Methods and apparatus are presented to allow one receiver architecture to be used for the reception of two different SDARS signals. Common receiver functions can be utilized to process each signal, thereby obviating the need to duplicate hardware elements. For example, it can be assumed that both signals will not be received at the same time, thus allowing for considerable hardware reuse and lowering the cost of an interoperable receiver.

Abstract: Data may be distributed using data carousels. After a device receives the data, or a portion thereof, the device may make available a data carousel that allows others to receive the data. Each data carousel may contain a portion of the data. Data carousels may also contain error correction information that can be used to reconstruct missing portions of the data being distributed. A carousel directory may keep track of the carousel structure and direct the behavior of devices that are receiving data and/or distributing data.

Abstract: Systems, methods, apparatus, and techniques are presented for processing a codeword. A Reed-Solomon mother codeword n symbols in length and having k check symbols is received, and the n symbols of the received Reed-Solomon mother codeword are separated into v Reed-Solomon daughter codewords, where v is a decomposition factor associated with the Reed-Solomon mother codeword. The v Reed-Solomon daughter codewords are processed in a respective set of v parallel processes to output v decoded codewords.

Abstract: According to an embodiment, a memory controller includes: a coding unit that performs an error correction coding process for user data to generate first to n-th parities and performs the error correction coding process for each of the first to n-th parities to generate first to n-th external parities; and a decoding unit that performs an error correction decoding process using the user data, the first to n-th parities, and the first to n-th external parities. A generator polynomial used to generate an i-th parity is selected on the basis of a generator polynomial used to generate the first to (i?1)-th parities.

Abstract: A broadcast transmitter and a method of processing broadcast data in the broadcast transmitter are disclosed. The method includes randomizing broadcast service data, first encoding the randomized broadcast service data to add parity data, second encoding the first-encoded broadcast service data at a code rate of D/E, first interleaving the second-encoded broadcast service data, encoding signaling data for signaling the broadcast service data, modulating the first-interleaved broadcast service data and the encoded signaling data, and transmitting the modulated data.

Abstract: A handheld digital camera device including: a digital camera unit having a first image sensor for capturing images and a color display for displaying captured images to a user; an integral processor configured for: controlling operation of the first image sensor and color display; decoding an imaged coding pattern printed on a substrate, the printed coding pattern employing Reed-Solomon encoding; and performing an action in the handheld digital camera device based on the decoded coding pattern. The decoding includes the steps of: detecting target structures defining an extent of a data area; determining the data area using the detected target structures; and Reed-Solomon decoding the coding pattern contained in the determined data area.

Abstract: An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

Abstract: In one embodiment, a method for communicating a sequence of data bits is provided. FEC coding is performed on a received sequence of data bits to produce an FEC coded sequence formatted for a first set of N data lanes. The FEC coded sequence includes FEC data blocks, in which each FEC data block has a plurality of data symbols. Alignment markers are added to the FEC coded sequence and the FEC coded sequence is multiplexed to produce a multiplexed sequence formatted for a second set of M data lanes. The multiplexing is performed only at boundaries between the data symbols or the alignment markers. The multiplexed sequence is transmitted on M data lanes.

Abstract: A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.

Abstract: Apparatuses and methods for encoding, transmitting, receiving and decoding signal frames are provided. A transmitting apparatus includes: a frame encoder configured to perform Reed Solomon (RS) encoding on a plurality of frames in a vertical direction, wherein the frame encoder divides the plurality of frames into a plurality of groups, performs RS encoding for each group so that parties are added after the last frame of each group, and generates the RS-encoded frames. A receiver includes: a frame decoder configured to perform RS decoding on a plurality of received frames in a vertical direction, wherein the frame decoder divides the plurality of received frames into a plurality of groups, and performs RS decoding for each group to obtain information words without the parities.

Abstract: According to one embodiment, a memory controller including a syndrome calculation unit which calculates syndrome based on code word which have the ability to correct t bits, an error locator polynomial calculation unit, and a Chien search unit, wherein the Chien search unit includes a root shift block which shifts all roots, a division block which divides the output from the root shift block by a predetermined polynomial, of which the order is smaller than t, and substitution block which substitutes elements into the remainder polynomial to examine if they are the roots of the remainder, and wherein the predetermined polynomial has at least one root which value is the same as one of the substituted elements.

Abstract: One or more locations in a plurality of data bit sequences that do not satisfy parity and are associated with data bit sequences that are unable to be successfully error correction decoded are determined. Soft information associated with the determined locations is modified and error correction decoding using the modified soft information is performed.

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Abstract: A method for uplink (UL) wireless backhaul communication at a wireless backhaul remote unit in a radio access network comprising receiving a configuration for radio frames and a transmission schedule through a downlink (DL) physical layer broadcast channel, wherein the transmission schedule comprises a transmission allocation for the remote unit, generating a UL data frame, wherein generating the UL data frame comprises performing forward error correction (FEC) encoding on a data bit stream to generate a plurality of FEC codewords, wherein performing the FEC encoding comprises performing Reed Solomon (RS) encoding on the data bit stream to generate a plurality of RS codewords, performing byte interleaving on the RS codewords, and performing Turbo encoding on the byte interleaved RS codewords to generate one or more Turbo codewords, wherein each Turbo codeword is encoded from more than one RS codeword, and transmitting the UL data frame according to the transmission allocation.

Abstract: Systems and methods are provided for recovering data stored in memory. A group of data is encoded using a first layer of code to form a first encoded group of data. Individual portions of the first encoded group of data are then encoded using a second layer of code to form a second encoded group of data. A processor may request access to an individual portion of the group of data. The encoded version of the requested individual portion is retrieved from memory and decoded using the second layer of code to recover the requested individual portion. If the recovery of the requested individual portion fails, the remaining encoded portions of the group are retrieved from memory and decoded using the first layer of code to recover the requested individual portion.

Abstract: A communication link analyzer is disclosed for analyzing a communication link. The communication link analyzer may analyze bitstreams that have been FEC encoded and are transmitted according to one or more 10 Gigabit Ethernet standards, 40 Gigabit Ethernet standards, and other such standards. The communication link analyzer may maintain a running count of the errors detected for the bit positions of a 2112-bit FEC-encoded datablock. These errors may include, but are not limited to, baseline wander, deterministic jitter, and predictive-interval errors. When a given error threshold is met or exceeded for one or more received bitstreams, the communication link analyzer may then attempt a diagnosis of the communication link. Using previously provided empirical data, the communication link analyzer may provide a diagnosis of the communication link based on the error type threshold that was met or exceeded and the bit position associated with the error type threshold.

Abstract: In an arrangement of the disclosed systems, devices, and methods, a matrix representation of a block code comprising m bit-planes is obtained, a generator matrix corresponding to each of the m bit-planes from the matrix representation is extracted, a transformed generator matrix and a transformed data symbol vector for the first bit-plane of the block code are determined, a reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code are determined, and instructions for the encoder architecture based on the transformed generator matrix for the first bit-plane and the reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code are generated.

Abstract: An encoder and decoder using LDPC-CC (Low Density Parity Check-Convolutional Codes) is disclosed. In the encoder (200), an encoding rate setting unit (250) sets an encoding rate (s?1)/s (s=z), and an information creating unit (210) sets information including from information Xs,i to information Xz?1,i to zero. A first information computing unit (220-1) receives information X1,i at time point i to compute the X1(D) term of formula (1). A second information computing unit (220-2) receives information X2,i at time point i to compute the X2(D) term of formula (1). A third information computing unit (220-3) receives information X3,i at time point i to compute the X3(D) term of formula (1). A parity computing unit (230) receives parity Pi?1 at time point i?1 to compute the P(D) of formula (1). The exclusive OR of the results of the computation is obtained as parity Pi at time i. Ax.

Abstract: A difference signal calculating unit of a noise detecting device calculates a difference between the amplitudes of a residual signal at each sample timing and a residual signal at the preceding sample timing. A difference signal comparing unit determines whether or not an impulsive noise is present on the basis of the difference signal at the current sample timing, and the difference signal at each sample timing within a predetermined duration from the current sample timing.

Abstract: According to one embodiment, a digital broadcasting system includes an RS (Reed-Solomon) encoder configured to encode mobile service data for FEC (Forward Error Correction) to build RS frames including the mobile service data and a signaling information table, a signaling encoder configured to encode signaling information including fast information channel (FIC) data, and transmission parameter channel (TPC) data, a group formatter configured to form data groups, wherein at least one of the data groups includes encoded mobile service data, known data sequences, the FIC data and the TPC data, and a transmission unit configured to transmit the broadcast signal including a parade of the data groups.

Abstract: A signal detector/decoder is implemented in multiple stages. The beginning stage is configured to input channel data bits and to output hard data bits based on the channel bits and a maximum likelihood (ML) path. The next stage includes a postcoder coupled to receive channel domain information from the first stage and to convert the channel domain information to user domain information. The final stage includes a reliability unit coupled to receive the user domain information from the postcoder and to output user domain soft information for the hard data bits based on the ML path estimation and the user domain information.

Abstract: According to one embodiment, a method of processing broadcast data in a broadcast transmitter includes: encoding the broadcast data for broadcast service; encoding signaling information for signaling the broadcast data; assigning the encoded broadcast data and the encoded signaling information into a signal frame; and transmitting a broadcast signal including the signal frame. The broadcast signal further includes a signaling table having access information of the broadcast data. The signaling table includes service id information for identifying the broadcast service and component information for indicating a number of components in the broadcast service.

Abstract: A system and method for expeditious transfer of data from a source device to a destination device in error corrected manner are provided. The system and method avoid the substantial delay in utilizing an intermediate buffer, determining error, and remediating the detected errors before even initializing a transfer of an input data from the source device to the destination device. Upon completion of error correction, only those portions corrected are retransmitted to the destination memory rather than the complete corrected input data. A by-pass section is provided for copying input data to the destination memory with at least a degree of parallelism with the error detection of the input data delivered to a parallel buffer coupled with the correction section by a splitter section.

Abstract: Aspects of the present disclosure are directed towards communications over current-carrying power distribution lines. In accordance with one or more embodiments, respective sets of utility-based data indicative of a reading of utility usage taken at different times are communicated. First sets of the data corresponding to readings taken during a first time period are communicated and, thereafter, second sets of the data corresponding to readings taken during a second time period are communicated and interleaved with portions of error correction code (ECC) data. Prior to receiving at least some of the ECC data, the first sets of data are interpreted and access is provided to the interpreted data. After all of the ECC data has been received, the ECC data is used to verify the first sets of data, correct the first sets of data, and access to is provided to the verified first sets of data.

Abstract: In one embodiment, a Chien search circuit includes a plurality of evaluation circuits, each configured to sequentially evaluate possible roots ?i in a respective subset of possible roots of an error location polynomial (?(x)). Each evaluation circuit includes a respective sub-circuit for each of a plurality of coefficients ?i (0?i?T) of the error location polynomial ?(x) having T+1 coefficients. Each sub-circuit is configured to calculate one term of the error location polynomial for each possible root ?i in the respective subset of possible roots. Each evaluation circuit is configured to evaluate the error location polynomial for each possible root in the respective subset of possible roots, as a sum of the terms calculated by the plurality of sub-circuits.

Abstract: In one embodiment, a method includes receiving a headerized SDS protected by unequal error protection; decoding a header from the headerized SDS and removing an impact of the header from C1 row parity to obtain a SDS; for a number of iterations: performing C2 column decoding, for no more than a number of interleaves in each row of the SDS: overwriting a number of columns with successfully decoded C2 codewords, erasing a number of C2 codewords, and maintaining remaining columns as uncorrected, performing C1 row decoding; for no more than a number of interleaves in each row of the SDS: overwriting a number of rows with successfully decoded C1 codewords, erasing a number of C1 codewords, and maintaining remaining rows as uncorrected; and outputting the SDS when all rows include only C1 codewords and all columns include only C2 codewords; otherwise, outputting indication that the SDS cannot be decoded properly.

Abstract: A method includes storing data that is encoded with an Error Correction Code (ECC) in a group of analog memory cells. The memory cells in the group are read using multiple sets of read thresholds. The memory cells in the group are divided into two or more subsets. N partial syndromes of the ECC are computed, each partial syndrome computed over readout results that were read using a respective set of the read thresholds from a respective subset of the memory cells. For each possible N-bit combination of N bit values at corresponding bit positions in the N partial syndromes, a respective count of the bit positions in which the combination occurs is determined, so as to produce a plurality of counts. An optimal set of read thresholds is calculated based on the counts, and data recovery is performed using the optimal read thresholds.

Abstract: Systems and methods are provided for correcting erasures in received codewords. In certain implementations of the system and methods, a codeword transmitted over a channel is processed to identify and/or mark a set of locations in the codeword corresponding to erased codeword symbols. A decoder selects a subset of locations from the set of locations in the codeword and selects a sequence of symbol values from a plurality of symbol value sequences. The decoder replaces each of the erased symbols in the subset of locations with a corresponding symbol value from the sequence of symbols values to produce a modified codeword and attempts to decode the modified codeword.

Abstract: Provided is a receiver for processing VSB signal. The receiver includes a first equalizer/decoder unit and a second equalizer/decoder unit. The first equalizer/decoder unit performs a first equalizing operation, first TCM decoding and first RS decoding on a received symbol to output a first dibit. The second equalizer/decoder unit performs a second equalizing operation, second TCM decoding and second RS decoding on the received symbol to output a transport stream. The first dibit is provided as a priori information for a soft-decision operation of the second TCM decoding.

Abstract: In one embodiment, an encoder circuit is provided. The encoder includes an input circuit having a plurality of finite field subtraction circuits, each configured to receive a respective one of the sequence of symbols and subtract the symbol from a respective symbol of an intermediate polynomial to produce a respective feedback symbol. For each coefficient of a code generation polynomial, a first circuit is configured to multiply each feedback symbol by a respective constant corresponding to the coefficient to produce a first set of intermediate results. Each first set of intermediate results is summed to produce a second intermediate result. A buffer circuit of the encoder is configured and arranged to store the second intermediate results produced by the first circuit as the intermediate polynomial.

Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.

Abstract: A data communication method using forward error correction (FEC) includes: receiving at least one of symbols that constitute one encoding block unit; extracting information related to parameters that adjust an FEC encoding rate from the at least one symbol; determining whether an error may be corrected based on the extracted information related to the parameters and a number of symbols with errors from among the symbols that constitute the encoding block unit; and transmitting feedback information related to the symbols prior to the symbols that constitute the encoding block unit being completely received based on the determination of whether an error may be corrected.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate (i) a plurality of symbols and (ii) a plurality of decision values both in response to detecting an encoded codeword. The second circuit may be configured to (i) generate a plurality of probabilities to flip one or more of the symbols based on the decision values, (ii) generate a modified probability by merging two or more of the probabilities of an unreliable position in the symbols and (iii) generate a decoded codeword by decoding the symbols using an algebraic soft-decision technique in response to the modified probability.

Abstract: Embodiments of apparatus and methods for decoding errors and erasures are described. A codeword may have errors and erasures. In embodiments, an apparatus may include a syndrome calculator configured to generate partial syndromes of the codeword, an erasure locator configured to generate an erasure locator polynomial, and a syndrome modifier configured to generate modified partial syndromes based at least in part on the partial syndromes and the erasure locator polynomial. The apparatus may further include an error locator configured to generate an error locator polynomial using the modified partial syndromes, for error and erasure decoding of the codeword. Other embodiments may be described and/or claimed.

Abstract: Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.

Abstract: A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.

Abstract: A method and apparatus are described including receiving channel condition feedback from a device over a wireless channel, determining response to the channel condition feedback if a forward error correction coding rate is sufficient for the device to recover lost data, adjusting the forward error correction coding rate responsive to the second determining act and generating forward error correction packets using the adjusted forward error correction coding rate from source data.

Abstract: A system including a reconstruction module and a correlation module. The reconstruction module is configured to reconstruct data bits detected from first signals, and to generate second signals based on the reconstruction of the data bits detected from the first signals. The correlation module is configured to generate first correlation values by correlating (i) the first signals and (ii) the second signals, and to generate second correlation values by self-correlating the second signals. In response to one or more of (i) the first signals and (ii) the second signals including a floating number having (i) a plurality of bits and (ii) a sign bit, the correlation module is configured to generate one or more of (i) the first correlation values and (ii) the second correlation values based on (i) a plurality of most significant bits of the floating number and (ii) the sign bit of the floating number.

Abstract: Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

Abstract: One embodiment relates to a method of communicating data between a transmitter and a receiver of a communication system. In this method, a payload data stream is received from a network interface layer. The payload data stream includes data units eligible for retransmission and data units non-eligible for retransmission. These data units are grouped into containers, where a container is associated with a container identifier that distinguishes the container from other containers. The containers are grouped into data transmission units, where a data transmission unit includes at least one container along with redundancy information that facilitates error detection for that data transmission unit. The data transmission units are transmitted to the receiver as a transmission data stream. Other methods and systems are also disclosed.

Abstract: The present disclosure is directed to systems for achieving speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems. In one example, the system is a transmitter that includes a FEC encoder configured to generate and append redundant symbols to the input data stream to provide a FEC encoded data stream, a serial-to-parallel module configured to de-serialize the FEC encoded data stream and distribute the FEC encoded data stream over parallel FEC encoded data streams with at least one of the redundant symbols generated by the FEC encoder generated based on data sent over two or more of the parallel FEC encoded data streams, and a line code encoder configured to modulate one of the parallel FEC encoded data streams.

Abstract: Methods of correcting data in a memory, and memories adapted to correct data, include prioritizing error correction of the read data in response to locations and likely states of known bad or questionable data positions of a segment of a memory array selected for reading.

Abstract: A method begins by a dispersed storage (DS) processing module encrypting a data segment utilizing an encryption key to produce an encrypted data segment and performing a deterministic function on the encrypted data to produce a transformed representation of the encrypted data. The method continues with the DS processing module masking the encryption key utilizing the transformed representation of the encrypted data to produce a masked key, partitioning the masked key into a plurality masked key partitions, partitioning the encrypted data segment into a plurality of encrypted data segment partitions, and combining the plurality of masked key partitions with the plurality of encrypted data segment partitions to produce a plurality of combined partitions. For a combined partition of the plurality of combined partitions, the method continues with the DS processing module encoding the combined partition using a dispersed storage error coding function to produce a set of encoded data slices.

Abstract: An apparatus generally having a plurality of first circuits and a second circuit is disclosed. The first circuits may be configured to (i) generate a plurality of intermediate bits by dividing a plurality data bits by a plurality of minimal polynomials of an encoding along a first path and (ii) generate a plurality of parity bits by multiplying the intermediate bits by the minimal polynomials along a second path. A number of the parity bits may be variable based on a configuration signal. The second circuit may be configured to (i) delay the data bits and (ii) generate a plurality of code bits by appending the parity bits to a last of the data bits.

Abstract: A transport stream generating apparatus, a turbo packet demultiplexing apparatus, and methods thereof, the transport stream generating apparatus including: a Reed Solomon (RS) encoder to RS-encode turbo data, an interleaver to interleave the RS-encoded turbo data, a duplicator to add a parity insertion area to the interleaved turbo data, and a multiplexer to multiplex normal data and the turbo data processed by the duplicator to generate a transport stream. Accordingly, reception performance can be improved in an advanced vestigial sideband (AVSB) system.

Abstract: A system for configuring telemetry transponder cards uses a database of error checking protocol data structures, each containing data to implement at least one CCSDS protocol algorithm. Using a user interface, a user selects at least one telemetry specific error checking protocol from the database. A compiler configures an FPGA with the data from the data structures to implement the error checking protocol.

Abstract: A method for decoding encoded data comprising integrated data and header protection is disclosed herein. In one embodiment, such a method includes receiving an extended data array. The extended data array includes a data array organized into rows and columns, headers appended to the rows of the data array, column ECC parity protecting the columns of the data array, and row ECC parity protecting the rows and headers combined. The method then decodes the extended data array. Among other operations, this decoding step includes checking the header associated with each row to determine whether the header is legal. If the header is legal, the method determines the contribution of the header to the corresponding row ECC parity. The method then reverses the contribution of the header to the corresponding row ECC parity. A corresponding apparatus (i.e., a tape drive configured to implement the above-described method) is also disclosed herein.

Abstract: Aspects are directed to communicating data over power distribution lines carrying alternating current, using a communication protocol for communicating data between endpoint devices and an upstream data-collecting device. From first symbols having a plurality of bits, at least two second symbols are generated, the second symbols respectively including different subsets of the bits in the first symbol. Each first symbol is split into second symbols having a predefined bit size for an encoding operation that operates on entire symbols having the predefined bit size (e.g., smaller than the bit size of the first symbols). The second symbols are encoded and combined according to the communication protocol. The encoded symbols are communicated over the power distribution lines based on timing indicated at least in part by the alternating current.

Abstract: A digital broadcasting system and method of processing data are disclosed. Herein, a method of processing data in a transmitting system includes creating a data group including a plurality of mobile service data packets, re-adjusting a relative position of at least one main service data packet of a main service data section, the main service data section including a plurality of main service data packets, and multiplexing the mobile service data of the data group and the main service data of the main service data section in burst units. Herein, a position of an audio data packet among the main service data packets of the main service data section may be re-adjusted. Also, a position of an audio data packet included in the main service data section may be re-adjusted based upon a multiplexing position of the main service data section.

Abstract: A receiving system and data processing method therein are disclosed, by which mobile service data is received and processed.