Abstract: Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256).

Abstract: A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.

Abstract: Systems and methods described herein provides a method for dynamically allocating an iteration number for a decoder. The method includes receiving, at an input buffer, an input signal including at least one data packet. The method further includes calculating a first iteration number for decoding the at least one data packet. The method further includes monitoring at least one of available space of the input buffer and available decoding time for the at least one data packet. The method further includes dynamically adjusting the first iteration number to a second iteration number based on the available space or the available decoding time to continue decoding the at least one data packet.

Abstract: A method is described for transmitting broadcast signals. First encoding of first broadcast service data is performed. Second encoding of the first encoded first broadcast service data is performed. The broadcast signals having the second encoded first broadcast service data multiplexed with second broadcast service data are transmitted. Each of the second encoded first broadcast service data and the second broadcast service data is allocated in a different data unit. The second encoded first broadcast service data and the second broadcast service data are allocated in different data units, respectively. Different robustness are allocated to the first broadcast service data and the second broadcast service data.

Abstract: Data is received from a physical coding sublayer (PCS) of a physical layer, where the physical layer comprises a BASE-R physical layer. The data is used to generate a forward error correction (FEC) block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block. The FEC block is scrambled using a pseudo-noise sequence. The FEC block is sent to a physical medium attachment (PMA) sublayer of the physical layer.

Abstract: Methods and apparatuses for enabling or disabling MTC mode operations for a plurality of CPE devices in a MAC domain are provided. A system operator can control enabling MTC mode operations for certain CPE devices capable of MTC mode operations in a MAC domain by setting a control attribute in a CMTS enabled for MTC mode operations for the MAC domain.

Abstract: A test automation tool detects a first set of parameters defining one or more software environments to be tested, where the first set of parameters includes at least a component to be tested. The test automation tool then identifies a general test plan, where the general test plan includes a first set of test cases, and where the first set of test cases are defined by the first set of parameters. The test automation tool detects a first set of test case relevancy rules for a first test case of the first set of test cases included in the general test plan. The test automation tool then creates an errata test plan based on the general test plan, where the errata test plan includes a second set of test cases.

Abstract: Methods and modules for spatial decorrelation and recorrelation are described. A block of data values can be spatially decorrelated in two dimensions efficiently by processing rows of the data values in a particular order such that if the results of spatially decorrelating a first row will be used for column-wise spatial decorrelation of a second row then the data values of the first row are processed in an earlier iteration to that in which the data values of the second row are processed. This allows for highly parallelised processing of the block of data values. Spatial recorrelation can be performed as an inverse process to the spatial decorrelation.

Abstract: A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.

Abstract: A device implementing a forward error correction data transmission system may include at least one processor circuit. The at least one processor circuit may be configured to perform line encoding on a data stream received from a media access control (MAC) module, and periodically insert alignment markers after every number of blocks of the data stream, where the alignment markers are determined based at least in part on a data rate of an associated port. The at least one processor circuit may be further configured to transcode the data stream, where each alignment marker remains contiguous in the transcoded data stream. The at least one processor circuit may be further configured to add parity information to the transcoded data stream. The at least one processor circuit may be further configured to transmit the transcoded data stream over at least one physical lane of the associated port.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that performs programming and reading out with respect to the non -volatile memory, a code processor that generates a code word by encoding; and a controller that sets a threshold -voltage read level for determining whether a value of each bit in a received word read out from the non-volatile memory is “0” or “1”. A difference between the number of bits which have value equals “0” and the number of bits which have value equals “1” in the code word depends on a code rate of the encoding. The controller obtains the threshold-voltage read level based on the code rate.

Abstract: The present document is for a wireless communication with reduced internal signaling burden in the distributed antenna system (DAS). In the proposed method, a user equipment (UE) receives a decoding unit, from the network, by multiple distributed unit (DUs) distributed within the UE, and decodes the decoding unit, at each of the multiple DUs. Each of the multiple DUs reports first information on the decoding result to a central unit (CU) controlling the multiple DUs, and the CU determines decoded bit values of the decoding unit based on the first information acquired from each of the multiple DUs.

Abstract: A method and apparatus are presented for transmitting broadcast signals. Service data is encoded by an encoder. A signaling encoder encodes signaling data based on a mode of the signaling data. The signaling data is categorized to one of plural modes based on a modulation order for the signaling data. A frame builder builds at least one signal frame including the encoded service data in at least one data symbol and the encoded signaling data in at least one signaling symbol. A modulator modulates data in the at least one signal frame by an Orthogonal Frequency Division Multiplex (OFDM) scheme. A transmitter transmits the broadcast signals carrying the modulated data in the at least one signal frame. The broadcast signals further carry a bootstrap. The bootstrap includes category information indicating the mode of the signaling data in the at least one signaling symbol in the at least one signal frame.

Abstract: In one embodiment, a method includes loading first data into a first buffer of an interposer during a first time period and loading second data into a second buffer of the interposer and performing a first decoding operation on the first data using a first decoder during a second time period. The method includes loading third data into a third buffer of the interposer, performing the first decoding operation on the second data using the first decoder, and performing a second decoding operation on the first data using a second decoder during a third time period. Moreover, the method includes loading fourth data into a fourth buffer of the interposer, performing the first decoding operation on the third data using the first decoder, and performing the second decoding operation on the second data during a fourth time period. The first and second decoding operations are C1 or C2 decoding operations.

Abstract: A method and a system for estimating a parameter in a communication system are provided. The method includes estimating a parameter of a data channel model in a communication system, decoding a packet received through a determined noise channel to convert the packet into data indicating one of a success and failure of a reception of the packet, configuring a prototype channel having at least one unknown parameter, estimating the at least one unknown parameter using the data indicating the one of the success and the failure of the reception of the packet, and determining the size of a parity field of a forward error correction (FEC) symbol, using the estimated at least one unknown parameter.

Abstract: Example apparatus and methods combine erasure coding with data deduplication to simultaneously reduce the overall redundancy in data while increasing the redundancy of unique data. In one embodiment, an efficient representation of a data set is produced by deduplication. The efficient representation reduces duplicate data in the data set. Redundancy is then added back into the data set using erasure coding. The redundancy that is added back in adds protection to the unique data associated with the efficient representation. How much redundancy is added back in and what type of redundancy is added back in may be controlled based on an attribute (e.g., value, reference count, symbol size, number of symbols) of the unique data. Decisions concerning how much and what type of redundancy to add back in may be adapted over time based, for example, on observations of the efficiency of the overall system.

Abstract: A multi-stage codeword detector for detecting codewords from read signals received from a multi-level memory device, includes a first detection stage configured for a coarse detection of a first codeword from a received read signal; a second detection stage configured for a fine detection of a second codeword from the received read signal; and a deciding entity configured to decide on using the second detection stage for the received read signal in dependence on a reliability indicator indicating a certain reliability level of the received read signal.

Abstract: Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device. Coefficient data representing canonical coefficients can be pre-computed by an apparatus before the apparatus is provided with program data, for example. For example, coefficient data may be pre-computed external to the apparatus and stored before program data is provided to an apparatus.

Abstract: A data processing block that includes a syndrome computation unit suitable for generating odd syndrome values in response to a received codeword, an ELP solver suitable for generating even syndrome values, based on the odd syndrome values in a first mode, and generating an error location polynomial, based on the odd syndrome values and the even syndrome values in a second mode, and a Chien search unit suitable for generating solutions of the error location polynomial.

Abstract: A method and apparatus for transmitting a Forward Error Correction (FEC) packet block including a plurality of FEC packets in a multimedia system are provided. The method includes generating a plurality of first FEC packet blocks by performing a first FEC encoding on a plurality of source symbols, each of the plurality of first FEC packet blocks including at least one source packet and at least one repair packet for repair of each of the at least one source packet, generating a second FEC packet block by performing a second FEC encoding on the plurality of first FEC packet blocks, the second FEC packet block including at least one repair packet for the plurality of first FEC packet blocks, and transmitting the second FEC packet block that includes, in header information of each of the at least one source packet and the at least one repair packet.

Abstract: The present invention concerns a system for transmitting a plurality of modes of digital television signals within the same transmission channel where one transmission mode is more robust than another mode. The present invention also concerns a system for receiving and decoding such signals. More specifically, an aspect of the present invention involves a method and an apparatus for utilizing a proper length of preamble data for the improvement of reception. Furthermore, another aspect of the present invention involves a method and an apparatus for inserting a preamble into a proper place in a transmitted data stream relative to the filed synchronization data. Another aspect of the present invention involves a method and an apparatus for decoding trellis-coded data, using the predetermined preamble data.

Abstract: A set of one or more component syndromes associated with a turbo product code (TPC) codeword is obtained from a component syndrome buffer. Component decoding is performed on the set of one or more component syndromes.

Abstract: A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word.

Abstract: According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit.

Abstract: A system that includes a bus, a battery, core processing circuitry, radio frequency (RF) processing circuitry, first power regulating circuitry, second power regulating circuitry, and control circuitry is provided. The bus can be coupled to receive power from a source external to the system. The core processing circuitry and RF processing circuitry can be selectively coupled to each other via a switch. The switch can be operative to turn ON and OFF based on a signal level received on the bus. The first power regulating circuitry can be electrically coupled to the bus, the core processing circuitry, and the switch. The second power regulating circuitry can be electrically coupled to the battery, the RF processing circuitry, and the switch. The control circuitry can be operative to selectively turn ON and OFF the first power regulating circuitry and the second power regulating circuitry based on a number of monitored conditions.

Abstract: A memory device (e.g., a flash memory device) includes power efficient codeword error analysis circuitry. The circuitry analyzes codewords stored in the memory of the memory device to locate and correct errors in the codewords before the codewords are communicated to a host device that requests the codewords from the memory device. The circuitry includes a highly parallel configuration with reduced complexity (e.g., reduced gate count) that a controller may cause to perform the error analysis under most circumstances. The circuitry also includes an analysis section of greater complexity with a less parallel configuration that the controller may cause to perform the error analysis less frequently. Because the more complex analysis section runs less frequently, the error analysis circuitry may provide significant power consumption savings in comparison to prior designs for error analysis circuitry.

Abstract: A method of encoding data for transmission from a source to a destination over a communications channel is provided. A plurality of redundant symbols are generated from an ordered set of input symbols to be transmitted. A plurality of output symbols are generated from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much larger than the number of symbols in the combined set of symbols, wherein at least one output symbol is generated from more than one symbol in the combined set of symbols and from less than all of the symbols in the combined set of symbols, and such that the ordered set of input symbols can be regenerated to a desired degree of accuracy from any predetermined number, N, of the output symbols.

Abstract: Systems, methods, apparatus, and techniques relating to a transmitter interface are disclosed. A soft-IP transmitter interface includes a Reed-Solomon encoder operating according to any one of multiple bus width and bandwidth parameter pairs, and a gearbox module that includes multiple gearboxes. The multiple gearboxes receive input data at a bus width and clock rate parameter pair specified by the soft-IP transmitter interface and convert the input data into output data according to a number of physical lanes and bandwidth parameter pair specified by a physical medium attachment (PMA) standard.

Abstract: Signal processing, data encoding and/or decoding techniques are applied in a dictionary system. A dictionary is generated as a function of time shift and phase shift distortion. Atoms of the dictionary can be determined. Further, parameters of the dictionary can be flexibly chosen. In one aspect, signals can be processed as a function of the dictionary.

Abstract: Systems and methodologies are described that facilitate transmitting beacon symbols of a beacon message such that a sequence of symbols can satisfy a linear constraint over a field where the field elements can be identified with carriers. In this regard, a coding scheme can be applied to a beacon message; the coding scheme can produce a plurality of beacon symbols to transmit on given subcarriers. A receiving device of the beacon symbols can decode a beacon message by receiving less than the total number of symbols in a beacon message and determining the remaining symbol subcarriers based on the linear constraint. Thus, more efficient decoding of beacons is facilitated as well as resolving beacon ambiguity by figuring out which symbols satisfy linear constraints for the symbols, and resolving time and frequency shift by detecting an offset that would result in satisfaction of the linear constraint.

Abstract: In one embodiment, a method for assembling data from a medium includes reading a data set from the medium repeatedly using different settings until either: a reconstructed data set is obtained, or a maximum number of rereads has been reached, the data set including a plurality of sub data sets, each sub data set having a plurality of rows, and after each reread of the data set, good rows of data are stored to iteratively construct a good data set from a plurality of good rows as determined by C1 and/or C2 error correction code (ECC).

Abstract: The ECC circuit includes a Chien search unit configured to determine whether there is an error in each bit of a data sequence. The Chien search unit selects a coefficient of a nonlinear term from among terms of an error locator polynomial as a nonlinear coefficient, separates the error locator polynomial into a first location equation including only linear terms and a second location equation including only nonlinear terms, determines a third location equation by dividing the first location equation by the nonlinear coefficient, determines a fourth location equation by dividing the second location equation by the nonlinear coefficient, and determines whether there is an error for each of the bits by performing an XOR operation on a result of the third location equation using the substitution value and a result of the fourth location equation using an arbitrary element of the error locator polynomial as a substitution value.

Abstract: A broadcast receiving apparatus is disclosed. The broadcast receiving apparatus includes a receiver configured to receive a broadcast signal which includes video data; a detector configured to detect error information for determining whether there is an error in a packet identifier information, regarding the video data and correction information for correcting the packet identifier information; and a controller configured to detect the packet identifier information using the correction information, and detect the video data using the corrected packet identifier information, when it is determined that the error occurs in the packet identifier information.

Abstract: Circuitry for, in p parallel streams, searching a codeword having n symbols for roots of a cyclic code polynomial having a number of terms includes a plurality of multipliers, a source of constants derived from roots of the polynomial, and at least one counter that supplies an index. For each received symbol of the codeword, the multipliers multiply respective terms of the polynomial for a previous received symbol by constants from the source of constants, the counter advances to select respective products of the constants and the respective terms for the previous received symbol.

Abstract: The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.

Abstract: An identification provider provides predetermined identification data to an input signal, and generates a first signal. A differential encoder performs a differential encoding of a data series that is an aggregate of data having a matching number of elements to that contained in the first signal, and generates a second signal. A modulator modulates each of the first and second signals using a primary modulation, and generates first and second modulated data. An IFFT calculator performs an inverse fast Fourier transformation on each of the first and second modulated data, and generates first and second inverse transformed data. A selector compares peak-to-average power ratios calculated by baseband signals associated with the first and second inverse transformed data, and selects a baseband signal having the lower peak-to-average power ratio. A transmitter generates a transmission signal based on the selected baseband signal, and transmits the transmission signal.

Abstract: A digital broadcasting system which is robust against an error when mobile service data is transmitted and a method of processing data are disclosed. The mobile service data is subjected to an additional coding process and the coded mobile service data is transmitted. Accordingly, it is possible to cope with a serious channel variation while applying robustness to the mobile service data.

Abstract: A broadcast transmitting system and method are provided. The method includes performing RS encoding and CRC encoding on mobile service data bytes to build an RS frame, dividing the RS frame into a plurality of portions, adding K bytes of dummy data to one of the portions, converting data bytes of the plurality of portions into data bits, encoding each of the data bits to output data symbols, interleaving the data symbols, converting the interleaved data symbols into data bytes, forming data groups, inserting a plurality of known data sequences in each data group, deinterleaving data of the data groups, RS encoding mobile service data packets to insert first RS parity data in the data packets, interleaving data of the RS-encoded data packets, trellis encoding the interleaved data, recalculating second RS parity data based on initialization data and replacing the first RS parity data with the second RS parity data.

Abstract: A method is provided of encoding data within a RAID stripe, the RAID stripe being spread across k data disks and r redundancy disks of a RAID group, r?3, the RAID group having k+r disks, the k data disks and the r redundancy disks within the RAID stripe being distinct, such that, upon failure of any r disks of the k+r disks of the RAID group, the data can be fully recovered using the Forney algorithm. The method includes (a) partitioning the data into k data symbols, (b) storing each of the k data symbols to a respective data disk of the k data disks, (c) generating r Reed-Solomon redundancy symbols by applying the Forney algorithm to the k data symbols, and (d) storing each of the r Reed-Solomon redundancy symbols generated by the Forney algorithm to a respective redundancy disk of the r redundancy disks.

Abstract: A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.

Abstract: Webpages configured for display on a full-sized screen such as a computer monitor (111) are reconfigured for use with a mobile device in accordance with a user's preferences. A custom rendering tool engages the user in customizing the webpage in order to render the webpage information suitable for display on a mobile device. A browser toolbar is used, by which the user may highlight a section of interest section (121) from a webpage and save the customization information. A proxy server receives the customization information and uses the information to accurately retrieve the sections of interest later, even after the webpage or the section has been updated.

Abstract: A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction.

Abstract: In an arrangement of the disclosed systems, devices, and methods, a codeword encoded with a first number of check symbols is received and asymmetrically processed according to a second number of check symbols, where the second number of check symbols is less than the first number of check symbols, to produce an error locator polynomial and an error evaluator polynomial. A derivative of the error locator polynomial is produced by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant. The derivative of the error locator polynomial is produced using a variable finite-field multiplier and without use of a divider.

Abstract: A data storage device is disclosed comprising non-volatile solid-state array comprising M storage elements for storing data protected by Reed-Solomon (R-S) code, each storage element comprising multiple blocks, each block comprising multiple pages for storing data. The data storage device further comprises a controller in communication with the storage array and defining a superblock comprising logical grouping of M blocks, each located in different storage element, and multiple superpages in each superblock, each superpage comprising M pages, each located in a different storage element. The controller generates, for each superpage, at least one R-S code parity page for protecting data pages in the superpage, where number of data pages and the at least one parity page is equal to M?1. The controller assigns one page in each superpage as an inactive page not used in the R-S code, where at least two inactive pages are in different storage elements.

Abstract: A method includes the following steps: sorting service data into retransmissive service data and non-retransmissive service data; allocating resources to the retransmissive service data and the non-retransmissive service data respectively, and encapsulating the data into DTUs according to the allocated resources; sending, by a sender, the DTU that bears the service data; receiving, by the sender, a retransmission request that is sent according to a result of judging a bit error and a type of the retransmissive service, where the retransmission request carries information about the DTU that needs to be retransmitted; and retransmitting, by the sender, a corresponding DTU that bears the retransmissive service data requested for retransmission.

Abstract: A decoding circuit is disclosed that includes a decoding pipeline configured to receive a data block that includes a plurality of data symbols, encoded with a Reed-Solomon (RS) FEC coding thereafter further encoded by a second FEC coding. The data block also includes a first and second sets of FEC datagrams for correcting received words of the plurality of data symbols encoded with the RS FEC coding and second FEC coding, respectively. Each decoding stage of the pipeline is configured to decode the plurality of data symbols using the first and second sets of FEC datagrams. A post-processing circuit connected to an output of the pipelines is configured to perform bitwise RS decoding of ones of the plurality of data symbols in error.

Abstract: A method includes receiving a representation of a set of single error detection (SED) parity bits and a representation of data. The data includes an error correction coding (ECC) codeword including information bits and ECC parity bits. Each SED parity bit of the set of SED parity bits indicates a parity value for a corresponding portion of the data. The method includes, in response to determining that a particular portion of the representation of the data includes a single erasure bit, selectively modifying a bit value of the single erasure bit based on the representation of the SED parity bit that corresponds to the particular portion and generating an updated representation of the ECC codeword when the bit value of the single erasure bit corresponds to the ECC codeword and has been modified. The method may include initiating an ECC decode operation of the updated representation of the ECC codeword.

Abstract: A semiconductor device includes a memory region configured to include a plurality of banks and a redundancy region within each of the banks and an error check and correction (ECC) region configured to detect an address of the memory region at which an error has occurred and correct a defect of the memory region by replacing the address at which the error has occurred with a redundancy line of the redundancy region based on address information.

Abstract: Examples are disclosed for techniques associated with error correction for encoded data. In some examples, error correction code (ECC) information for the ECC encoded data is received that indicates the ECC encoded data includes one or more errors. A determination is made as to whether the ECC encoded data includes either a single error or more than one error. If the ECC encoded data includes a single error, an error location of the error is identified. If the ECC encoded data includes more than one error, separate error locations are identified for the more than one error. The single error or the more than one error is corrected and the ECC encoded data is then be decoded.

Abstract: An enhanced VSB receiver includes a tuner which tunes an RF signal and converts it into an IF signal, an IF mixer which converts the IF signal into a baseband signal, and a demodulator which demodulates the baseband signal into a VSB signal. The enhanced VSB receiver further includes a map recovery unit which recovers VSB map information of the VSB signal, an enhanced equalizer for compensating channel distortion of the VSB signal and outputting an equalized symbol, and an enhanced Viterbi decoder for estimating whether polarity inversion occurred during a symbol period of the equalized symbol and Viterbi-decoding the equalized symbol based on the polarity estimation.