Maximum Likelihood Patents (Class 714/794)
  • Patent number: 10958277
    Abstract: This application is directed to an electronic device including a phase locked loop (PLL) circuit. The PLL includes a voltage-controlled oscillator (VCO) and the PLL is configured to generate a plurality of periodic signals having a first frequency. Optionally, the periodic signals are equally separated in phase to cover an entire period cycle of the first frequency. The electronic device includes a first multiplexer coupled to the PLL, the first multiplexer being external to the PLL. The first multiplexer configured to receive a first selection signal, select a first periodic signal of the plurality of periodic signals based on the first selection signal, and provide the first selected periodic signal to a first clock-driven circuit that is distinct from the PLL. The electronic device further includes a controller circuit coupled to the first multiplexer, the controller circuit being configured to provide the first selection signal to the first multiplexer.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: March 23, 2021
    Assignee: Cobham Colorado Springs Inc.
    Inventor: Viorel Olariu
  • Patent number: 10956263
    Abstract: Memory systems, controllers, decoders and methods execute decoding with a mufti-level interference correction scheme. A decoder performs first soft decoding to generate log likelihood ratio (LLR) values of a select bit and bits of memory cells neighboring a memory cell of the select bit. A quantizer obtains an estimated LLR value of the select bit based on the LLR values of the select bit and the bits of the memory cells neighboring the memory cell of the select bit, when the first soft decoding fails. The decoder performs second soft decoding using the estimated LLR value when the first soft decoding fails, and performs third soft decoding using information obtained from application of a deep learning model to provide a more accurate estimate of the LLR value of the select bit when the second soft decoding fails.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Yu Cai, Fan Zhang
  • Patent number: 10938421
    Abstract: A memory system configured to decode a data set may pause a convergence process to update reliability metric values. The memory system may utilize a positive feedback system that updates the reliability metric values by analyzing current a posteriori reliability metric values to calculate average estimated reliability characteristic values associated with a memory error model. The updates to the reliability metric values may provide increased error correction capability and faster decoding.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 2, 2021
    Inventors: Eran Sharon, Alexander Bazarsky, Ariel Navon, Omer Fainzilber
  • Patent number: 10846170
    Abstract: An operation method of a decoder may include: performing a first sub-decoding operation on a target data chunk; performing a second sub-decoding operation on candidate chunks and a chip-kill chunk; performing a third sub-decoding operation to determine a global check node; performing a fourth sub-decoding operation to infer and update local variable nodes of the target data chunk and local variable nodes of a data chunk from the global check node; and repeating the first to fourth sub-decoding operations once by a set number of times based on components of the updated local variable nodes.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventor: Dae-Sung Kim
  • Patent number: 10802913
    Abstract: A solid state storage device using a prediction function is provided. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit generates collection read operation commands. The collection read operation commands are temporarily stored in a command queue, and transmitted to the non-volatile memory. According to each of the collection read operation commands, the non-volatile memory generates a corresponding encoded read data to the control circuit. After the error correction circuit performs a decoding operation on the encoded read data, a decoded content is generated and a first count of the decoded content is transmitted to a first register of the register set. After the encoded read data is decoded, a value stored in the first register is a first parameter and the first parameter is inputted into a prediction function of the function storage circuit.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 13, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Tsu-Han Lu, Hsiao-Chang Yen
  • Patent number: 10763808
    Abstract: A test and measurement device including a source configured to output a source signal, a source output configured to output the source signal to a connected cable, a guard drive circuit electrically coupled to the source and configured to receive the source signal and generated a guard drive signal, the guard drive circuit having a gain less than one, and a guard drive circuit output configured to output the guard drive signal to a connected guard.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: September 1, 2020
    Assignee: Keithley Instruments, LLC
    Inventors: James A. Niemann, Wayne C. Goeke
  • Patent number: 10721029
    Abstract: The present disclosure describes a method, an apparatus, and a computer readable medium for hybrid automatic repeat request (HARQ) transmissions. For example, the method may include generating a first codeword for a first information block, wherein the first codeword is a first polar code, and wherein the first information block includes cyclic redundancy check (CRC) bits; transmitting the first codeword to a receiver; determining that the first polar code is not successfully decoded at the receiver based at least on a first message received from the receiver; generating a second codeword for a second information block, wherein the second codeword is a first enhanced polar code, and wherein the second information block does not include any CRC bits; transmitting the second codeword to the receiver; and determining that the second codeword and the first codeword are successfully decoded at the receiver based at least on a second message received from the receiver.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: July 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Changlong Xu, Jian Li, Chao Wei, Neng Wang, Jilei Hou
  • Patent number: 10700811
    Abstract: A decoding device includes: a BP decoder that performs BP decoding on an input signal; a maximum likelihood decoder that performs maximum likelihood decoding on a signal subjected to the BP decoding; and a selector that selects one of the input signal, the signal subjected to the BP decoding, and a signal subjected to the maximum likelihood decoding. In a configuration of the decoding device, when a decoder is appropriately operated according to quality of data, a calculation scale can be reduced, and power consumption can be decreased.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 30, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
  • Patent number: 10691451
    Abstract: Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 23, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Keith M. Bindloss, Carl S. Dobbs, Evgeny Mezhibovsky, Zahir Raza, Kevin A. Shelby
  • Patent number: 10680647
    Abstract: Techniques are described for performing a check node update (CNU) as part of iterative decoding of a low density-parity check (LDPC) code. The CNU uses a min-sum decoding approach that monitors whether two values received in messages from two variable nodes connected to a check nodes are equal and are the minimum value among the values received by the check nodes from other variable nodes connected thereto. Upon detecting such an event, the minimum value is adjusted by reducing it by an adjustment value to generate an adjusted minimum value. This adjusted minimum value approximates the minimum value that a sum-product algorithm (SPA) decoding approach would have generated. The adjusted minimum value is included in a response message sent from the check node to a variable node. The bit corresponding to that variable node is decoded based on this adjusted minimum value.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Aman Bhatia, Naveen Kumar, Abhiram Prabhakar, Chenrong Xiong, Fan Zhang
  • Patent number: 10554359
    Abstract: A method of receiving phase tracking reference signal (PT-RS) by a user equipment (UE) in a wireless communication system, the method includes determining one or more resource blocks to which the PT-RS is mapped among N resource blocks allocated to the UE; and receiving the PT-RS via the one or more second resource blocks, wherein the N resource blocks are indexed as second resource block indices 0 to N?1 from a resource block having a lowest index of first resource block indices to a resource block having a highest index of the first resource block indices, wherein the PT-RS is mapped to the one or more resource blocks having indices of the second resource block indices and the indices are determined based on a first value related to a frequency density of the PT-RS and a second value related to a resource block offset, wherein the first value is determined based on a scheduled bandwidth related with the N resource blocks allocated to the UE, and wherein N is a natural number.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 4, 2020
    Assignee: LG Electronics Inc.
    Inventors: Kilbom Lee, Jiwon Kang, Kyuseok Kim, Kijun Kim, Kunil Yum
  • Patent number: 10528496
    Abstract: A controller may include a first encoder suitable for generating a first polar parity by performing a first polar encoding operation to respective first sections of an original message having a plurality of symbols, an interleaver suitable for generating an interleaved message by interleaving the original message according to first reliabilities, which are predetermined depending on locations of the respective symbols in the respective first sections in the original message, and second reliabilities, which are predetermined depending on locations of the respective symbols in the interleaved message, a second encoder suitable for generating a second polar parity by performing a second polar encoding operation to respective second sections included in the interleaved message and a memory interface suitable for storing the original message, the first polar parity and the second polar parity into a memory.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: January 7, 2020
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Jaekyun Moon, Soon-Young Kang, Sung-Whan Yoon
  • Patent number: 10498363
    Abstract: Provided is a low density parity check (LDPC) decoder. An LDPC decoder according to an embodiment of the inventive concept includes a variable node calculator for adding an input log-likelihood ratio (LLR) to message information of a check node to output the added values, a check node calculator for extracting signs of the output values of the variable node calculator, determining a minimum value of the output values, and calculating a correction term for the output values by using a binary logarithm to transmit to the variable node calculator, a hard decision block for determining bit values of the output values of the variable node calculator, and a parity check block for performing a parity check operation for determining validity of the bit value.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: December 3, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyuk Kim, Insan Jeon
  • Patent number: 10367534
    Abstract: A method of transmitting broadcast signals includes forward error correction (FEC) encoding mobile data; interleaving the FEC encoded mobile data; encoding signaling information for the mobile data; mapping the interleaved mobile data and the encoded signaling information into a data unit, wherein the data unit includes a first region and a second region, wherein the first region is concatenated with the second region, wherein the first region includes known data and the encoded signaling information, and wherein the second region includes known data and the encoded mobile data; and transmitting the broadcast signals including the data unit, wherein the data unit is multiplexed with a data unit of main data in a specific time period, wherein the signaling information includes information of the data unit having the interleaved mobile data.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 30, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: In Hwan Choi, Kook Yeon Kwak, Byoung Gill Kim, Jin Woo Kim, Hyoung Gon Lee, Won Gyu Song
  • Patent number: 10326551
    Abstract: Disclosed herein are systems and methods for forward packet recovery in a communication network with constrained network bandwidth overhead. In exemplary embodiments, a target byte protection ratio is determined. Error correcting frames are dynamically generated by a first processor such that error correcting information can be generated to approximate the target byte protection ratio. The data packets and error correcting information are then transmitted across one or more communication networks to a second processor. The second processor can use the error correcting information to regenerate or replace data packets missing or corrupted in transmission across one or more communication networks.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 18, 2019
    Assignee: Silver Peak Systems, Inc.
    Inventor: David Anthony Hughes
  • Patent number: 10236918
    Abstract: An encoder and decoder using LDPC-CC which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an encoding method of the same. A termination sequence length determining unit determines the sequence length of a termination sequence transmitted added to the end of an information sequence, according to the information length (information size) and encoding rate of the information sequence. A parity calculation unit carries out LDPC-CC coding on the information sequence and the known-information sequence necessary for generating a termination sequence of the determined termination sequence length, and calculates a parity sequence.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: March 19, 2019
    Assignee: Panasonic Corporation
    Inventors: Yutaka Murakami, Hisao Koga, Nobutaka Kodama
  • Patent number: 10219170
    Abstract: A device and method for performing channel estimation, including in a first iteration of channel estimation, determining a channel estimate based on at least a first pilot symbol of a reference signal received at the device; and in each respective iteration of one or more ensuing iterations determining a reference channel estimate based on at least one subsequent pilot symbol of the reference signal; decoding a data signal received at the device based on the reference channel estimate; determining a data channel estimate based on at least one data symbol from the decoded data signal; and calculating a channel estimate for the respective iteration based on the reference channel estimate, the data channel estimate, and a channel estimate from a previous iteration.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: February 26, 2019
    Assignee: Intel IP Corporation
    Inventors: Maxime Monin, Lea Castel, Tommaso Balercia
  • Patent number: 10103750
    Abstract: An error correction decoding apparatus includes column operators 201 and row operators 211 to 213 provided respectively in accordance with the columns and rows of a check matrix of an LDPC code. A received LLR (log-likelihood ratio) of a received sequence is input into the column operators 201 together with row LLRs from the row operators 211 to 213, whereupon the column operators 201 calculate a total value z1 of the received LLR of the received sequence and the row LLRs from the row operators 211 to 213. The row operators 211 to 213 hold operation results relating to row LLRs or column LLRs obtained during a previous operation, calculate column LLRs using the total value input from the column operators 201 and the held operation results, calculate row LLRs from the calculated column LLRs, and output the calculated row LLRs to the column operators 201.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: October 16, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kenya Sugihara, Wataru Matsumoto, Hideo Yoshida, Yoshikuni Miyata
  • Patent number: 10075191
    Abstract: The invention relates to a method for decoding read bits including information bits from memory cells of a solid-state drive. The method comprises providing an indication of reliability of the read bits, and, based on the indication of reliability, iteratively soft decoding the read bits in order to obtain the information bits, wherein the soft decoding comprises, at each iteration of the soft decoding, if the current number of iterations has reached a predetermined number of iterations indicative of an admitted latency of the solid state drive, and if no information bits having an error rate below a predetermined error rate have been obtained, providing a further indication of reliability of the read bits, and iteratively soft decoding the read bits based on the further indication of reliability. The invention also relates to a corresponding controller and a corresponding solid-state drive.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 11, 2018
    Assignee: NandEXT Srl
    Inventor: Margherita Maffeis
  • Patent number: 9985651
    Abstract: Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chandra C. Varanasi, Gerald L. Cadloni
  • Patent number: 9838035
    Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: December 5, 2017
    Assignee: MaxLinear, Inc.
    Inventors: Mingrui Zhu, Curtis Ling, Timothy Gallagher
  • Patent number: 9819423
    Abstract: An apparatus comprising a receiver configured to receive a super-symbol comprising a first modulation symbol and a second modulation symbol, wherein the first modulation symbol comprises a first modulation format, and wherein the second modulation symbol comprises a second modulation format, and a processor coupled to the receiver and configured to select, for the first modulation symbol, a first nearest candidate symbol from a first set of candidate symbols associated with the first modulation format, select, for the second modulation symbol, a second nearest candidate symbol independent of the first nearest candidate symbol from a second set of candidate symbols associated with the second modulation format, and determine a soft decision value for a first hit in the super-symbol according to the first nearest candidate symbol and the second nearest candidate symbol.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: November 14, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Clarence Kan, Wei-Ren Peng, Yan Cui
  • Patent number: 9780883
    Abstract: A system and method including multi-dimensional coded modulation wherein symbols within successive blocks of symbols are mapped using at least two different constellations to differentiate the symbols from each other. At least one data bit is encoded by an order of the symbols within each block of symbols. The receiver decodes the data by decoding at least one bit from the order of the symbols mapped with the first and second constellations.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: October 3, 2017
    Assignee: TYCO ELECTRONICS SUBSEA COMMUNICATIONS LLC
    Inventors: Hongbin Zhang, Hussam G. Batshon
  • Patent number: 9780990
    Abstract: A system and method including multi-dimensional coded modulation wherein symbols within successive blocks of symbols are mapped using at least two different constellations to differentiate the symbols from each other. At least one data bit is encoded by an order of the symbols within each block of symbols. The receiver decodes the data by decoding at least one bit from the order of the symbols mapped with the first and second constellations.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: October 3, 2017
    Assignee: TYCO ELECTRONICS SUBSEA COMMUNICATIONS LLC
    Inventors: Hongbin Zhang, Hussam G. Batshon
  • Patent number: 9665582
    Abstract: Software, systems, and methods are disclosed herein for enhanced updating of replica storage volumes within virtual machine environments. A first group of data blocks of a plurality of data blocks on an underlying storage volume that have changed are identified. A second group of data blocks of the first group of data blocks that are live are identified. Changed data items associated with the second group of data blocks are identified. An ancillary process is initiated on the changed data items. An update of the replica of the target storage volume with the second group of data blocks is also initiated.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: May 30, 2017
    Assignee: QUANTUM CORPORATION
    Inventors: Gregory L. Wade, J. Mitchell Haile
  • Patent number: 9632863
    Abstract: In general, techniques are described for performing track-error-correcting code on data. A hard drive comprising a storage device and a read channel may be configured to perform the techniques. The read channel may be configured to read data from a track comprising a plurality of data sectors each comprising a plurality of bits, and a parity sector comprising a plurality of parity bits, wherein the data includes a plurality of bit groups, each bit group including a single bit from each data sector, and wherein each parity bit corresponds to a respective bit group, perform a track parity check, and, responsive to determining that the data includes an error, identify one or more data sectors as possible sources of the at least one error and adjust a log-likelihood ratio for at least one bit from the bit group.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: April 25, 2017
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard L. Galbraith, Weldon M. Hanson, Roger W. Wood
  • Patent number: 9543983
    Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: sending a read command sequence for reading multiple memory cells so as to obtain multiple first bits; determining whether the first bits have a first error; if the first bits have the first error, executing a first iteration decoding procedure on the first bits so as to obtain multiple second bits, and recording first bit flipping information of the first iteration decoding procedure; determining whether the second bits have a second error; and If the second bits have the at least one second error, executing a second iteration decoding procedure on the second bits according to the first bit flipping information so as to obtain multiple third bits.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: January 10, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chien-Fu Tseng
  • Patent number: 9509340
    Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: November 29, 2016
    Assignee: Maxlinear, Inc.
    Inventors: Mingrui Zhu, Curtis Ling, Timothy Gallagher
  • Patent number: 9473177
    Abstract: A turbo decoder stores received data in words in systematic memory and parity memory in a way that is known that it will be used for later iterations by turbo decoder engines arranged to operate in parallel. A loader receives and separates LLRs into systematic and parity data and stores them into a portion of a word per cycle until a word is full in a corresponding one of the systematic memory and parity memory. The turbo decoder engines read the LLRs from one word of the systematic memory and one word of the parity memory in a single cycle. The data can be rearranged within the words in an order format for the turbo decoder engines to later read them by providing sub-words corresponding to respective ones of the plurality of turbo decoder engines.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: October 18, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Robert Bahary, Eric J Jackowski
  • Patent number: 9407293
    Abstract: A system (100) for encoding an input video frame (1005), for transmitting or storing the encoded video and for decoding the video is disclosed. The system (100) includes an encoder (1000) and a decoder (1200) interconnected through a storage or transmission medium (1100). The encoder (1000) includes a turbo encoder (1015) for forming parity bit data from the input frame (1005) into a first data source (1120), and a sampler (1020) for down-sampling the input frame (1005) followed by intraframe compression (1030) to form a second data source (1110). The decoder (1200) receives data from the second data source (1110) to form an estimate for the frame (1005). The decoder (1200) also receivers the parity bit data from the first data source (1120), and corrects errors in the estimate by applying the parity bit data to the estimate. Each bit plane is corrected in turn by a turbo decoder (1260). The decoder determines how reliably a pixel value was decoded, too.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: August 2, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Axel Lakus-Becker, Ka-Ming Leung
  • Patent number: 9355716
    Abstract: A method for determining decision metrics in a detector for a memory device. The method includes receiving a plurality of signal samples and extracting a set of statistics from the signal samples, wherein at least one of the statistics is non-linear or complex, is derived from a plurality of the signal samples, and is not a function of at least one real linear statistic that is derived from a plurality of the signal samples. The method also includes applying at least one decision metric function to the set of statistics to determine at least one decision metric value corresponding to at least one postulated symbol.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: May 31, 2016
    Assignee: University of Hawaii
    Inventors: Meysam Asadi, Xiujie Huang, Aleksandar Kavcic
  • Patent number: 9306600
    Abstract: Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Chandra C. Varanasi, Gerald L. Cadloni
  • Patent number: 9294224
    Abstract: Described herein are apparatus, system, and method for data synchronization via a maximum-likelihood decoder in a memory controller. The method comprises receiving a constrained codeword from a non-volatile memory (NVM) via a channel, the constrained codeword including an appended bit-stream; and decoding the received constrained codeword by reconstructing the appended bit-stream and invoking a synchronization procedure that applies a maximum-likelihood (ML) estimator to estimate locations of any insertion, deletion, or error in the reconstructed appended bit-stream.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventor: Ravi Motwani
  • Patent number: 9294129
    Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: March 22, 2016
    Assignee: MaxLinear, Inc.
    Inventors: Mingrui Zhu, Curtis Ling, Timothy Gallagher
  • Patent number: 9281840
    Abstract: A method for implementing multi standard programmable low-density parity check decoder in a receiver is provided. The method includes (i) generating, by a control signal generation unit, pre computed control signals associated with a h-matrix, (ii) obtaining, by a control signal storage unit of a hardware decoder unit, the pre computed control signals associated with the h-matrix, (iii) obtaining, by a LLR memory fetch & data align unit, LLR bytes from a LLR memory unit, (iv) rotating, by a rotation and aligning unit, the LLR bytes to obtain aligned valid LLR bytes, (v) processing, by the processing element unit, the aligned valid LLR bytes to obtain an output data, and (vi) decoding, the h-matrix associated with at least one standard and code rates based on the pre computed control signals.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 8, 2016
    Inventors: Abhijeet Balasaheb Magadum, Guruprasad Rachayya Timmapur, Susmit Kumar Datta
  • Patent number: 9256487
    Abstract: Systems and methods are provided for selecting precisions during iterative decoding with a low-density parity check (LDPC) decoder in order to maximize LDPC code's performance in the error floor region. The selection of the precision of the messages may be done in such a way as to avoid catastrophic errors and to minimize the number of near-codeword errors during the decoding process. Another system and method to avoid catastrophic errors in the layered (serial) LDPC decoder is provided. Lastly, a system and method that select precisions and provide circuitry that optimizes the exchange of information between a soft-input, soft-output (SISO) channel detector and an error correction code (ECC) decoder for channels with memory is provided.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: February 9, 2016
    Assignee: Marvell International Ltd.
    Inventors: Nedeljko Varnica, Gregory Burd, Kiran Gunnam
  • Patent number: 9195534
    Abstract: A method for storing and propagating error information in computer programs, in which a globally valid error variable is used for storing and propagating the error information, wherein for each recognized error a nonzero value for the error is added to the error variable as error information with a respective stipulated arithmetic sign, and wherein the value is formed from a discrepancy in the content of a coded variable from an expected value. This combination and integration of a separate global propagation variable with values derived from an error, particularly by virtue of detected discrepancies in the known error recognition and propagation paths using operations and operands in “coded processing”, achieves an increased propagation certainty.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: November 24, 2015
    Assignee: Siemens Aktiengesellschaft
    Inventors: Jan Richter, Andreas Schenk, Karl-Hermann Witte
  • Patent number: 9184878
    Abstract: Presented herein are non-disruptive noise estimation techniques that utilize a correlation between attributes of a received signal and the noise to generate estimated noise values for symbols of the signal. More specifically, a digital signal comprising symbols transmitted over a telecommunications network is received. For each of a plurality of the symbols, an estimated noise value associated with the respective symbol is generated through a correlation of a log-likelihood ratio (LLR) value to predetermined noise values. The estimated noise values for the plurality of symbols are used to generate noise information representing time and frequency characteristics of noise in the telecommunications network.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: November 10, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Hang Jin, Koen Van Renterghem, Richard Meller, Denis Downey, Glendon L. Akins, III
  • Patent number: 9165654
    Abstract: A nonvolatile memory device includes a cell array, a distributed page buffer including a plurality of page buffer units disposed below the cell array, the plurality of page buffer units having a certain size; and a distributed page buffer control circuit including a plurality of page buffer control circuit units, each page buffer control circuit unit being arranged at one side of a corresponding page buffer unit, and configured to control operations of the corresponding page buffer unit, the plurality of page buffer control circuit units each having a predetermined size.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: October 20, 2015
    Assignee: SK HYNIX INC.
    Inventors: Sung Lae Oh, Dong Hyuk Kim
  • Patent number: 9130598
    Abstract: According to one embodiment, a decoding apparatus includes first and second acquisition units, a holding unit, a calculation unit, and a decision unit. The first acquisition unit acquires first measurement values of measurements performed to measure an eigenvalue of an encoded Z operator to a first encoded qubit of the two encoded qubits. The second acquisition unit acquires second measurement values of measurements performed to measure an eigenvalue of an encoded X operator to a second encoded qubit of the two encoded qubits. The holding unit holds error probabilities for the first measurement values and the second measurement values. The calculation unit calculates probabilities for measurement values of an encoded Bell measurement by using the first measurement values, the second measurement values, and the error probabilities. The decision unit decides measurement values of the encoded Bell measurement, based on the calculated probabilities.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: September 8, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hayato Goto, Hironori Uchikawa, Kouichi Ichimura, Satoshi Nakamura, Mamiko Kujiraoka
  • Patent number: 9130599
    Abstract: A data processing system includes a binary data detector having a hard decision output, a reliability calculator operable to calculate an error pattern reliability metric for each of a number of dominant error patterns associated with the hard decision output, and a converter operable to convert the error pattern reliability metrics to multi-level soft information.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: September 8, 2015
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Seongwook Jeong, Lu Pan, Jianzhong Huang, Haitao Xia
  • Patent number: 9106461
    Abstract: According to an aspect of an embodiment of the present disclosure, a method of relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data includes adding an ISI cancellation value to input data received at a first clock rate to generate first speculative data. The method further includes subtracting the ISI cancellation value from the input data to generate second speculative data. The method also includes sampling the first speculative data and the second speculative data at a second clock rate that is one-fourth of the first clock rate such that a timing constraint associated with performing the ISI reduction is relaxed.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: August 11, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Samir Parikh
  • Publication number: 20150135031
    Abstract: An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 14, 2015
    Applicant: LSI Corporation
    Inventors: Earl T. Cohen, Yunxiang Wu, Alexander Hubris, Christopher Brewer
  • Patent number: 9032276
    Abstract: The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Wu Chang, Fan Zhang, Yang Han, Ming Jin
  • Patent number: 9026883
    Abstract: A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 5, 2015
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Chiaming Lo, Yi-Chang Liu, Lawrence Chen Lee, Wei-Yu Lai, Wei-De Wu
  • Patent number: 9026876
    Abstract: Systems and methods for computing sign disagreement between signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector; and detecting one or more consecutive sign disagreements between an extrinsic output of a detector and an extrinsic output of a decoder.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: May 5, 2015
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Wu Chang
  • Patent number: 9026880
    Abstract: A check node processing unit updates an extrinsic value ratio based on a prior value ratio for each row of a parity check matrix with respect to input data. An identifying unit identifies, based on an element of the parity check matrix that can be identified by a row and column associated with the updated extrinsic value ratio, a next-target element in the same column and in a different row. The identifying unit identifies an element to be updated in the next step by the check node processing unit, from among multiple elements included in the same column. A variable node processing unit updates, based on the extrinsic value ratio, a prior value ratio associated with the identified next-target element after the check node processing unit completes the updating of each row. The check node processing unit and the variable node processing unit alternately and iteratively execute their operations.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: May 5, 2015
    Inventor: Atsushi Hayami
  • Patent number: 9026894
    Abstract: A channel decoder includes a demodulator, a filter, a detector module, and first and second circuits. The demodulator receives an input signal based on data read from a storage medium, and demodulates the input signal to generate a data signal. The filter generates equalized data based on the data signal. The detector module executes a Viterbi algorithm based on the equalized data to generate estimates of data originally stored in the storage medium, and based on the execution of the Viterbi algorithm, generates a first and second sets of depths. The first set of depths includes depths larger than depths in the second set of depths. The first circuit generates a first error signal based on the first set of depths. The second circuit generates a second error signal based on the second set of depths. The filter generates the equalized data based on the first and second error signals.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: May 5, 2015
    Assignee: Marvell International Ltd.
    Inventors: Hongwei Song, Zining Wu
  • Patent number: 9025704
    Abstract: Certain aspects of the present disclosure relate to techniques for generating likely demodulation candidates using Vector Candidate Sampling (VCS). VCS is used to generate high likelihood candidates for Multiple Input Multiple Output (MIMO) demodulation that approaches optimal maximum a posteriori (MAP) performance with reasonable complexity. A receive data vector is recorded corresponding to a signal received at a MIMO receiver. A plurality of likely candidates are determined for MIMO demodulation via VCS, based at least on the receive data vector. Determining the likely candidates may include perturbing the receive data vector for each candidate based on a pre-determined perturb vector, and estimating a corresponding transmit data vector based at least on the perturbed receive data vector for the candidate and an estimator matrix, wherein the likely candidate comprises the estimated data vector.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: May 5, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: James E. Beckman, Alexei Yurievitch Gorokhov
  • Patent number: 9021332
    Abstract: An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 28, 2015
    Assignee: Seagate Technology LLC
    Inventors: Erich F. Haratsch, Jeremy Werner, Zhengang Chen, Earl T. Cohen, Yunxiang Wu, Ning Chen