Abstract: An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract: The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol.

Abstract: Systems and methods for computing sign disagreement between signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector; and detecting one or more consecutive sign disagreements between an extrinsic output of a detector and an extrinsic output of a decoder.

Abstract: Certain aspects of the present disclosure relate to techniques for generating likely demodulation candidates using Vector Candidate Sampling (VCS). VCS is used to generate high likelihood candidates for Multiple Input Multiple Output (MIMO) demodulation that approaches optimal maximum a posteriori (MAP) performance with reasonable complexity. A receive data vector is recorded corresponding to a signal received at a MIMO receiver. A plurality of likely candidates are determined for MIMO demodulation via VCS, based at least on the receive data vector. Determining the likely candidates may include perturbing the receive data vector for each candidate based on a pre-determined perturb vector, and estimating a corresponding transmit data vector based at least on the perturbed receive data vector for the candidate and an estimator matrix, wherein the likely candidate comprises the estimated data vector.

Abstract: A channel decoder includes a demodulator, a filter, a detector module, and first and second circuits. The demodulator receives an input signal based on data read from a storage medium, and demodulates the input signal to generate a data signal. The filter generates equalized data based on the data signal. The detector module executes a Viterbi algorithm based on the equalized data to generate estimates of data originally stored in the storage medium, and based on the execution of the Viterbi algorithm, generates a first and second sets of depths. The first set of depths includes depths larger than depths in the second set of depths. The first circuit generates a first error signal based on the first set of depths. The second circuit generates a second error signal based on the second set of depths. The filter generates the equalized data based on the first and second error signals.

Abstract: A check node processing unit updates an extrinsic value ratio based on a prior value ratio for each row of a parity check matrix with respect to input data. An identifying unit identifies, based on an element of the parity check matrix that can be identified by a row and column associated with the updated extrinsic value ratio, a next-target element in the same column and in a different row. The identifying unit identifies an element to be updated in the next step by the check node processing unit, from among multiple elements included in the same column. A variable node processing unit updates, based on the extrinsic value ratio, a prior value ratio associated with the identified next-target element after the check node processing unit completes the updating of each row. The check node processing unit and the variable node processing unit alternately and iteratively execute their operations.

Abstract: A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified.

Abstract: An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure.

Abstract: Methods, apparatuses, and systems are provided for generating a candidate search set for ML detection of 2n-QAM signals transmitted on two or more MIMO spatial streams. A method includes estimating an initial solution yq for a received 2n-QAM symbol value b0b1 . . . bn-1, wherein all possible 2n-QAM symbol values are Gray-mapped constellation points; and performing an iteration for each hypothetical value of each bit position i of the initial solution yq, wherein each iteration comprises: determining a search center as: if ith bit of the initial solution equals the hypothetical value assumed for the current iteration, the initial solution yq; or if ith bit of the initial solution does not equal the hypothetical value assumed for the current iteration, a mirror constellation point yqc to the initial solution yq; and searching outward from the determined search center for candidate constellation points.

Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.

Abstract: This invention is related to a low-complexity MIMO detector in a wireless communication system with near optimal performance. An initial symbol estimation is performed for a received symbol vector. The soft information of the received symbol vector can be more accurately calculated using every candidate symbol vector of a combined set of candidate symbol vectors, wherein the combined set is generated based on the initial estimation. By combining aspects of both the linear detection and the ML detection, the complexity of the proposed detector becomes orders of magnitude lower than that of a ML detector, but the performance is very close to that of an ML detector.

Abstract: The error correcting decoding device of the present invention performs Low-Density Parity-Check (LDPC) decoding which accommodates a plurality of code rates while sharing circuits to suppress increase in circuit scale. If the set code rate is a second code rate which is a higher code rate than a first code rate, a column processing and row processing calculating unit (120A) uses a distributed submatrix in which a number of columns are selected and combined, wherein the number of columns is equal in number to the number of columns with which a first submatrix is constructed from a distributed check matrix corresponding to a second check matrix which accommodates the second code rate. At this time, the column processing and row processing calculating unit (120A) uses a distributed submatrix such that the row degree is less than or equal to the row degree of the first submatrix.

Abstract: A device creates a graph based on source code, and analyzes the source code to identify private variables and functions of the source code and public variables and functions of the source code. The device determines, based on the graph, a size threshold and semantics-related characteristics of functions and variables for each module, of multiple modules, and assigns, based on the graph, the private variables and functions to a corresponding module of the multiple modules. The device reduces, based on the graph, a number of the public variables and functions assigned to each module, and generates the multiple modules based on one or more of the graph, the size threshold, the assigned private variables and functions, and the number of the public variables and functions assigned to each module.

Abstract: The present disclosure includes systems and techniques relating to decoding signals produced within a storage device. A described technique includes retrieving a first codeword from a storage medium, decoding the first codeword, performing a retry process when the decoding was not successful, and retrieving one or more second codewords from the storage medium during the retry process to at least maintain a drive throughput. The retry process can include identifying one or more data chunks within the first codeword having potential defects, generating an erasure mask based on the one or more data chunks, applying, based on a window, one or more erasures within one or more different regions of the first codeword based on one or more corresponding regions of the erasure mask to produce one or more versions of the first codeword, and decoding the one or more versions of the first codeword.

Abstract: Systems and methods for power efficient iterative equalization on a channel are provided. An iterative decoder decodes received data from a channel detector using a decoding process. The decoder computes a decision metric based on the decoded data and adjusts the number of iterations of the decoding process based on the decision metric. The adjustment occurs prior to a reliability criterion for the decoded data being satisfied. The decoder may pass control back to the channel detector if the adjusted number of iterations has occurred or if the reliability criterion is satisfied. Adjusting the number of iterations of the decoding process may include increasing the number of iterations from a predetermined number of iterations. The decision metric may be based on syndrome weight or hard decisions. The decision metric may be chosen to reduce average power consumption of the detector, the decoder, or circuitry including the detector and the decoder.

Abstract: Embodiments of decoding data stored in solid-state memory arrays are disclosed. In one embodiment, multiple read operations are performed while taking inter-cell interference (ICI) into account. Soft-decision information, such as log-likelihood ratios (LLRs), is determined by using known data and its corresponding multi-read output. Soft-decision information is provided to a detector. Reliability is improved and performance is increased.

Abstract: A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein the processing order of the layers of the LDPC parity check matrix are rearranged during the decode process in an attempt to avoid error mechanisms brought about by the iterative nature of the LDPC belief propagation decoding process, such as stopping sets and trapping sets.

Abstract: A method and system for a sequence estimation in a receiver, such as for use when receiving a sample of a received inter-symbol correlated (ISC) signal corresponding to a transmitted vector of L symbols, with L being a integer greater than 1, and with symbol L being a most-recent symbol and symbol 1 being least recent symbol of the vector. A plurality of candidate vectors may be generated, wherein element L?m of each candidate vector holding one of a plurality of possible values of the symbol L?m, with m is an integer greater than or equal to 1, and elements L?m+1 through L of each candidate vectors holding determined filler values. A plurality of metrics may be generated based on the plurality of candidate vectors, and based on the generated plurality of metrics, a best one of the possible values of the symbol L?m may be selected.

Abstract: Computer-implemented methods and systems may perform one or more operations including, but not limited to: receiving input data from a source; applying an interleaving protocol to the input data to generate at least one component codeword; decoding the at least one component codeword; determining a first convergence value of at least one decoded component codeword; computing extrinsic data associated with the at least one component codeword according to the bit error count and the first convergence of at least one component codeword; determining a second convergence value associated with the at least one component codeword according to the extrinsic data associated with the at least one component codeword.

Abstract: A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.

Abstract: A receiver receives an inter-symbol correlated (ISC) signal with information symbols and a corresponding parity symbol. Values of information symbols are estimated utilizing parity samples that are generated from the parity symbols. One or more maximum likelihood (ML) decoding metrics are generated for the information symbols. One or more estimations are generated for the information symbols based on the one or more ML decoding metrics. A parity metric is generated for each of the one or more generated estimations of the information symbols. The parity metric is generated by summing a plurality of values of one of the generated estimations to generate a sum, and wrapping the sum to obtain a parity check value that is within the boundaries of a symbol constellation utilized in generating the information symbols.

Abstract: A set of reliability metrics is provided for use by an iterative probabilistic decoding process for non-volatile storage. A plurality of sense operations are performed on at least one set of non-volatile storage elements which are programmed to a plurality of programming states. A set of reliability metrics such as logarithmic likelihood ratios is provided based on the sense operations. The set of reliability metrics is can be used by an iterative probabilistic decoding process in determining a programming state of at least one non-volatile storage element based on at least one subsequent sense operation involving the at least one non-volatile storage element. The plurality of sense operations can be performed at different ages (e.g., number of program/erase cycles) of the at least one set of non-volatile storage elements and the set of reliability metrics can be based on an average over the different ages.

Abstract: A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

Abstract: Techniques are provided for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. A reduced state sequence estimation (RSSE) decoder is provided for a multidimensional code. A multidimensional code symbol comprises a number of symbol components of lower dimensionality. The RSSE decodes comprises at least one branch metric unit that calculates branch metrics for a received signal based on intersymbol interference and intrasymbol interference estimates, the at least one branch metric unit compensating for intrasymbol interference caused by symbol components within a current multidimensional code symbol; and a decision feedback unit that processes survivor symbols to calculate the intersymbol interference estimates for different code states of the multidimensional code and channels used to transmit the multidimensional code.

Abstract: An exemplary embodiment of the present invention provides an incremental lattice reduction method comprising: receiving an input signal at a plurality of input terminals; evaluating a reliability assessment condition using a primary symbol vector estimate of at least a portion of the input signal; terminating the incremental lattice reduction method if the reliability assessment condition is satisfied; and if the reliability assessment condition is not satisfied, performing at least one iteration of a lattice reduction detection sub-method to obtain a secondary symbol vector estimate.

Abstract: Bin identification information for a cell is generated. An estimation function is received where the estimation function trends toward a maximum soft read value at a first end and trends toward a minimum soft read value at a second end. A soft read value is determined for the cell based at least in part on the bin identification information and the estimation function.

Abstract: A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein an adaptive check node approximation is performed at the check node processor utilizing the smallest magnitude log-likelihood ratio (LLR) and the second smallest magnitude log-likelihood ratio (LLR) to adapt to the current conditions at the check node.

Abstract: In one embodiment a data decoding apparatus includes first and second decoding blocks configured to decode codeword bits in a first mode determined by a first probability of non-standard errors and a second mode determined by a second probability of non-standard errors. The apparatus also includes a mode modification logic configured to cause at least one of the first and second decoding blocks to operate in the second mode when the first and second decoding blocks fail to decode the codeword bits in the first mode. In another embodiment, a method includes decoding codeword bits in a first mode determined by a first probability of non-standard errors. When decoding the codeword bits in the first mode fails to decode the codeword bits, the codeword bits are decoded in a second mode determined by a second probability of non-standard errors.

Abstract: In one aspect, the present invention improves Turbo equalization and/or soft interference cancellation processing in communication receivers by providing an efficient and accurate technique to compute the second moment of a received symbol, e.g., an interfering symbol, as a function of the expected bit values of only those bits in the symbol that are magnitude-controlling bits according to a defined modulation constellation. Advantageously, the expected bit values in at least one embodiment are computed using a LUT that maps bit LLRs to corresponding hyperbolic tangent function values. Further, the expected symbol value is computed as a linear function of terms comprising the expected bit values and the soft symbol variance is efficiently computed from the second moment and the expected symbol value squared. This simplified processing reduces receiver complexity, particularly in the context of modulation constellations having non-constant magnitudes, and thus saves power and/or improves design economics.

Abstract: A radio communication device including: a processor configured to store each of quantization values of codeword to a memory in accordance with a transmission format, so as to fit each of the quantization values within a specified number of areas which are allocated in the memory, each of the areas having a specified size, and so as to satisfy at least one of a first condition and a second condition, the first condition indicating that the specified number is fewer than the maximum first bit number corresponding to a first transmission format with which a first bit number of the codeword is maximum among the predetermined transmission formats, and the second condition indicating that the specified size is fewer than the maximum second bit number corresponding to a second transmission format with which a second bit number of each of the quantization values is maximum among the predetermined transmission formats.

Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

Abstract: A state metric calculator for calculating state metrics of stages in a trellis of a sequence estimation technique is described. The calculator has a processing path containing operations needed for calculating a state metric of a trellis stage from state metrics of an earlier trellis stage. One or more data stores are located in the processing path to divide the path into separate sections. The sections can then operate on the production of different state metrics to one another in, if desired, the same clock cycle.

Abstract: A low-density parity check (LDPC) code decoding method may be provided. The LDPC code decoding method may linearize or perform step-approximation on a natural logarithm hyperbolic cosine function included in a check node updating equation of a sum-product algorithm used for decoding an LDPC code, and may convert the linearized function to correspond to a check node updating equation of a min-sum algorithm.

Abstract: A data communication network to transmit and/or receive data using soft-decision information is provided. A target access point in a data communication network may compute soft-decision information with respect to information bits corresponding to a transmission symbol, and transmit the computed soft-decision information to a destination device or an access point connected to the destination device. The destination device or the access point connected to the destination device may combine soft-decision information of a plurality of access points, and detect information bits based on the combined soft-decision information.

Abstract: An embodiment of a method for a multiple-antenna receiver is disclosed. For this embodiment of the method, a detector obtains a channel matrix and a symbol vector. Contents of the channel matrix and the symbol vector are accessed in order and out of order, where the out of order access of the contents of the channel matrix and the symbol vector respectively provide a reordered channel matrix and a reordered symbol vector. The channel matrix is decomposed with the symbol vector to obtain first decomposition inputs. The reordered channel matrix is decomposed with the reordered symbol vector to obtain second decomposition inputs. The first decomposition inputs are sphere detected to provide first candidates. The second decomposition inputs are sphere detected to provide second candidates. Reliability information is generated from the first candidates and the second candidates.

Abstract: Systems and methods for detecting data in a received multiple-input-multiple-output signal are provided. First, second, and third signals are received and form a vector y. The received signals are associated with first, second, and third data values that form a vector x. A channel matrix (H) is received, and a QR decomposition of the channel matrix is performed, such that H=QR. The vector y is transformed into a vector z according to z=QHy. A distance value between the rector z and the vector x is determined for each possible third data value. A nearest constellation point is calculated based on a first of the possible third data values. The calculating step is repeated for each of the possible third data values to generate a set of constellation point triplets. The distance values are determined using the set of constellation point triplets.

Abstract: Provided is an apparatus and method for iteratively detecting and decoding a received signal in a wireless communication system. An apparatus for iterative detection and decoding (IDD) in a wireless communication system may determine a predetermined group to be updated in a first soft decision sequence, may transmit detection control information of the determined group, and may generate a second soft decision sequence based on a detection operation result of a predetermined received signal portion that is extracted based on the detection control information.

Abstract: Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.

Abstract: A communication system includes: a decoding-probability module for calculating a decoding likelihood with a control unit for characterizing an alternative hypothesis regarding an arriving communication; a null-probability module, coupled to the decoding-probability module, for calculating a null likelihood for characterizing a null hypothesis regarding the arriving communication; a weight-calculation module, coupled to the decoding-probability module, for generating a decision weight corresponding to the decoding likelihood, the null likelihood, or a combination thereof; a reliability calculation module, coupled to the decoding-probability module, for calculating a decoding reliability with the decision weight, the decoding likelihood, and the null likelihood, the decoding reliability corresponding to a decoded-result; and a decoding module, coupled to the reliability calculation module, for decoding the arriving communication with a decoding parameter based on the decoding reliability for communicating with

Abstract: A communication system includes: a module configured to decode a remainder portion of a receiver message using a mechanism with a compensation channel value calculated from decoding an evaluation portion of the receiver message with a different mechanism, or using a mechanism-controller generated using a mismatch characterization based on determining a partial-sensitive output and a partial-insensitive output, or a combination thereof for communicating with a device.

Abstract: A system for reading data from a data storage device includes a channel detector configured to detect bits of digital data corresponding to the data read from the storage device, and, for each of the bits of digital data, determine a probability that each of the bits is a 0 or a 1. A decoder module is configured to generate confidence indicators associated with a first subset of the digital data. The confidence indicators include the probability, received from the channel detector, that each of the bits in the first subset of the digital data is a 0 or a 1, and/or bit flip data indicating a number of times each of the bits in the first subset of the digital data was flipped during decoding. A digital defect detection module is configured to selectively identify the first subset of the digital data as defective based on the confidence indicators.

Abstract: Monitors, architectures, systems and methods for determining one or more quality characteristics of a storage channel. The monitor generally includes an iterative decoder configured to decode data from the storage channel and generate information relating to a quality metric of the storage channel and/or the iterative decoder, a memory configured to store a threshold value for the quality metric, and a comparator configured to compare the threshold value with a measured value of the quality metric. The monitor enables accurate determination of storage channel quality without use of conventional Reed-Solomon metrics.

Abstract: An apparatus may include a channel estimation component to determine a channel estimation matrix H for a tone of a multiplicity of tones in a multiple input multiple output (MIMO) communications signal. The apparatus may further include a processor circuit coupled to the receiver component, and a flow selection component for execution on the processor circuit to calculate a figure of merit for power loss for the received tone based upon the channel estimation matrix, and based upon the calculated figure of merit, perform either a max-log calculation or a maximum likelihood calculation to determine a received signal metric, but not both calculations. Other embodiments are described and claimed.

Abstract: A signal detector/decoder is implemented in multiple stages. The beginning stage is configured to input channel data bits and to output hard data bits based on the channel bits and a maximum likelihood (ML) path. The next stage includes a postcoder coupled to receive channel domain information from the first stage and to convert the channel domain information to user domain information. The final stage includes a reliability unit coupled to receive the user domain information from the postcoder and to output user domain soft information for the hard data bits based on the ML path estimation and the user domain information.

Abstract: A communication device includes a turbo encoding section including a plurality of component encoders, wherein the plurality of component encoders within the turbo encoding section use different constraint lengths.

Abstract: A method of storing data includes receiving data including a first group of bits and a second group of bits and initiating a shaping encoding operation on the second group of bits to generate a third group of bits. The third group of bits has more bits than the second group of bits. The shaping encoding operation is configured to produce a non-uniform probability distribution of bit values in the third group of bits. The first group of bits and first error correction coding (ECC) parity bits corresponding to the first group of bits are stored to a first logical page that is within a physical page of a MLC memory and the third group of bits and second ECC parity bits corresponding to the third group of bits are stored to a second logical page that is within the physical page of the MLC memory.

Abstract: A method for estimating a scrambling code used on an uplink of a WCDMA system. The scrambling code is obtained from a Gold code, sum of a first specific M-sequence of the user and of a second M-sequence known from the receiver. After sampling of the signal received at the chip frequency of the scrambling code, the successive samples are subject to a differential treatment and the sequence of differential values is multiplied by the second M-sequence. The observables thereby obtained are decoded with the aid of a belief propagation iterative decoding. The decoded values then serve to determine the content of the shift register of the generator of the first M-sequence. One then deduces therefrom the Gold code and an estimation of the scrambling code, ?.

Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.

Abstract: A continuous parallel Viterbi decoder configured to (a) compute Trellis paths from an input bitstream encoded with a convolutional code, (b) backtrack the Trellis paths to generate an output signal, (c) store the Trellis paths in a shared memory, and (d) coordinate simultaneous read/write operations from and to the shared memory.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit having a data detection circuit is disclosed that includes: a scaling circuit, a soft output calculation circuit, and a factor calculation circuit. The scaling circuit is operable to scale a branch metric value by a scaling factor to yield a scaled output. The soft output calculation circuit is operable to calculate a soft output based at least in part on the scaled output. The factor calculation circuit operable to modify the scaling factor based at least in part on the soft output.