Maximum Likelihood Patents (Class 714/794)
  • Patent number: 8848842
    Abstract: An embodiment of a decoder is disclosed. For this embodiment of the decoder, a first estimation unit and a second estimation unit are for iterative decoding. A scheduler is to receive a mode select signal to provide either an indication of first scheduling information or second scheduling information to the first estimation unit and the second estimation unit responsive to the mode select signal.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Xilinx, Inc.
    Inventor: Christopher H. Dick
  • Patent number: 8850294
    Abstract: A decoding apparatus and method for estimating a reliability value by detecting uncorrected packet errors. The decoding apparatus includes a hard-decision unit and a reliability determination unit. The hard-decision unit performs hard-decision on a soft-input of a code. The reliability determination unit generates a reliability estimation value of the hard-decision result according to whether a packet error exists in the hard-decision result. The hard-decision unit performs hard-decision in response to the reliability estimation value.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sergey Zhidkov, Do-jun Rhee
  • Patent number: 8843813
    Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data transfer system is disclosed that includes a data detector, a defect detector and a gating circuit. The data detector provides a soft output, and the defect detector is operable to receive the soft output and the data signal, and to assert a defect indication based at least in part on the soft output and the data signal. The gating circuit is operable to modify the soft output of the detector whenever the defect indication is asserted.
    Type: Grant
    Filed: May 25, 2013
    Date of Patent: September 23, 2014
    Assignee: AGERE Systems Inc
    Inventor: Weijun Tan
  • Patent number: 8826108
    Abstract: The present disclosure describes techniques for pre-scaling decoder input values. In some aspects a soft-decoding input indicating a reliability of an encoded bit is received, the soft-decoding input is scaled based on a value of the soft-decoding input, and a hardware-based soft-decoder is enabled to use the scaled soft-decoding input to decode the encoded bit. By so doing, resolution of the soft-decoding input can be preserved during subsequent decoding operations improving performance of the hardware-based soft-decoder.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: September 2, 2014
    Assignee: Marvell International Ltd.
    Inventors: Li Zhang, Sudhir Srinivasa, Hongyuan Zhang, Rohit U Nabar, Atul Salhotra
  • Patent number: 8826110
    Abstract: The present invention is related to systems and methods for defect scanning.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: September 2, 2014
    Assignee: LSI Corporation
    Inventors: Ming Jin, Fan Zhang, Lei Chen, AbdelHakim S. Alhussein
  • Patent number: 8826094
    Abstract: Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (?) values and check edge message (?) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: September 2, 2014
    Assignee: Broadcom Corporation
    Inventors: Andrew J. Blanksby, Alvin Lai Lin
  • Patent number: 8819500
    Abstract: A system including a reconstruction module and a correlation module. The reconstruction module is configured to reconstruct data bits detected from first signals, and to generate second signals based on the reconstruction of the data bits detected from the first signals. The correlation module is configured to generate first correlation values by correlating (i) the first signals and (ii) the second signals, and to generate second correlation values by self-correlating the second signals. In response to one or more of (i) the first signals and (ii) the second signals including a floating number having (i) a plurality of bits and (ii) a sign bit, the correlation module is configured to generate one or more of (i) the first correlation values and (ii) the second correlation values based on (i) a plurality of most significant bits of the floating number and (ii) the sign bit of the floating number.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: August 26, 2014
    Assignee: Marvell International Ltd.
    Inventors: Shaohua Yang, Zining Wu
  • Patent number: 8806311
    Abstract: A trellis encoding device includes a plurality of trellis encoders to perform trellis-encoding of a transport stream into which a supplementary reference signal (SRS) has been inserted, and performs a memory reset in a region that precedes an SRS; and a parity compensation unit to compensate for parities of the transport stream in accordance with values stored in memories included in the trellis encoders. The plurality of trellis encoders may be implemented in diverse types. The trellis encoding device can perform a memory reset selectively using the stored value of the memory and the inverted value thereof, or selectively using the stored value of the memory and a fixed value. By properly resetting the memory in processing the transport stream into which the SRS has been inserted, DC offset can be reduced.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eui-jun Park, Jung-jin Kim, Seok-hyun Yoon, Kyo-shin Choo, Keon-yong Seok
  • Patent number: 8799737
    Abstract: Systems, methods, and other embodiments associated with data decoding are described. According to one embodiment, a method includes receiving an output value from one of a first block and a second block that form a pair of concatenated decoding blocks. The method includes determining a value of a modification criteria and modifying the output value based, at least in part, on the value of the modification criteria to form a modified output value. The modified output value is input to one of the first and second decoding blocks.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: August 5, 2014
    Assignee: Marvell International Ltd.
    Inventors: Nedeljko Varnica, Gregory Burd
  • Patent number: 8798210
    Abstract: Methods, system and apparatuses for carrier frequency offset estimation are disclosed. The method includes: receiving a preamble sequence rn with a correlator and correlating the preamble sequence with a locally stored Barker code bn to obtain a correlation result cn; extracting peak values from every L points in cn to form a peak value sequence xn, L being a length of a Barker code that corresponds to the sampling rate; performing frequency offset estimation to xn by using at least two frequency offset estimation apparatuses, the at least two frequency offset estimation apparatuses adopting different delay parameters D; and inputting the results output from the at least two frequency offset estimation apparatuses into a frequency offset combination module to calculate a final carrier frequency offset estimate, whereby accurate frequency estimation can be achieved and an appropriate acquisition range of frequency offset can be ensured.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Omnivision Technologies (Shanghai) Co., Ltd.
    Inventor: Yun Zhang
  • Patent number: 8799752
    Abstract: A method for reducing a number of bits for representing a value is disclosed. A first value represented with a first number of bits is transformed to a second value represented with a second number of bits, wherein the first number of bits is greater than the second number of bits. The transformed second value is scaled by a scale factor to a third value. Transforming includes selecting a target window with a width of a third number of bits, wherein the third number of bits is smaller than the first number of bits. Transforming further includes saturating the first value to a most significant bit (MSB) within the selected target window and extracting bits within the selected target window from the saturated value.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 5, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Yu Kou, Lingqi Zeng
  • Patent number: 8799751
    Abstract: A low-complexity optimal soft MIMO detector is provided for a general spatial multiplexing (SM) systems with two transmit and NR receive antennas. The computational complexity of the proposed scheme is independent from the operating signal-to-noise ratio (SNR) and grows linearly with the constellation order. It provides the optimal maximum likelihood (ML) solution through the introduction of an efficient Log-likelihood ratio (LLR) calculation method, avoiding the exhaustive search over all possible nodes. The intrinsic parallelism makes it an appropriate option for implementation on DSPs, FPGAs, or ASICs. In specific, this MIMO detection architecture is very suitable to be applied in WiMax receivers based on IEEE 802.16e/m in both downlink (subscriber station) and uplink (base station).
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 5, 2014
    Assignee: Redline Communications Inc.
    Inventors: Mahdi Shabany, Roya Doostnejad
  • Patent number: 8792595
    Abstract: A wireless communications device and method carries out a process including estimating channel information based on a received signal; generating pseudo-transmission signal point candidates based on the channel information and/or transmission signal point candidates; and generating a replica of the received signal based on the pseudo-transmission signal point candidates and the estimated channel information. The process further includes performing matrix operations on the basis of the received signal and the replica thereof; selecting pseudo-transmission signal point candidates which have a greater effect on likelihood calculations; reverting the selected pseudo-transmission signal point candidates to original transmission signal point candidates and calculating final likelihoods; and restoring the received signal on the basis of the calculated likelihoods.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 29, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Keisuke Yamamoto, Takehiko Kobayashi, Satoru Ejima
  • Patent number: 8793560
    Abstract: Techniques for efficiently and accurately computing log-likelihood ratio (LLRs) for code bits are described. A set of code bits may be mapped to a modulation symbol in a signal constellation. Different code bits in the set may be associated with different LLR functions. A receiver obtains received symbols for a transmission sent via a communication channel. The receiver derives LLRs for code bits based on the received symbols and piecewise linear approximation of at least one LLR function. The piecewise linear approximation of each LLR function may comprise one or more linear functions for one or more ranges of input values. The receiver may select one of the linear functions for each code bit based on a corresponding received symbol component value. The receiver may then derive an LLR for each code bit based on the linear function selected for that first code bit.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: July 29, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Jonathan Sidi, Rajesh Sundaresan
  • Patent number: 8787179
    Abstract: A method is for entities implementing a phase of communicating data conveyed by a plurality of transport channels, the data being multiplexed into at least one multiplexing frame. The data is rate-matched by transforming an input data block of an initial size into an output data block of a final size. The method includes determining a first parameter, which is an integer, and transmitting the first parameter from one of the entities to another of the entities. The method also includes calculating the final size, according to the initial size, the first parameter, a second parameter and a maximum payload of the multiplexing frame. The second parameter is a non-dimensional number corresponding to a maximum percentage of bits to be punctured. The first parameter is selected from a first range, and the second parameter is selected from a second range that is different from the first range.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: July 22, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Vincent Belaiche
  • Patent number: 8774326
    Abstract: A method of operation of a communication system includes: utilizing an estimation module estimating a log-likelihood ratio for a transmission; and utilizing a slicing module, coupled to the estimation module, slicing a constellation by: reading the log-likelihood ratio from the estimation module, defining a threshold within the constellation, and adjusting the threshold based on the log-likelihood ratio for determining a symbol.
    Type: Grant
    Filed: April 8, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chun Kin Au Yeung, Sungsoo Kim, Jungwon Lee
  • Patent number: 8775913
    Abstract: Methods and apparatus are provided for computing soft data or log likelihood ratios for received values in communication or storage systems. Soft data values or log likelihood ratios are computed for received values in a communication system or a memory device by obtaining at least one received value; identifying a segment of a function corresponding to the received value, wherein the function is defined over a plurality of segments, wherein each of the segments has an associated set of parameters; and calculating the soft data value or log likelihood ratio using the set of parameters associated with the identified segment. The computed soft data values or log likelihood ratios are optionally provided to a decoder.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 8, 2014
    Assignee: LSI Corporation
    Inventors: Erich F. Haratsch, Nenad Miladinovic, Andrei Vityaev
  • Patent number: 8761317
    Abstract: Log-likelihood ratios produced by a decoder are incorporated into a soft symbol to soft bit estimation process and are used to perform improved channel estimation and impairment covariance estimation. In an example method, a plurality of soft bits and corresponding probability metrics for a series of received unknown symbols are generated. Estimates of the received unknown information symbols are then regenerated, as a function of the soft bits and corresponding probability metrics. An estimate of the average amplitude of the received unknown information symbols, or an estimate of the propagation channel response experienced by the received unknown information symbols, or both, are calculated, as a function of the regenerated symbol estimates. The results are applied to produce demodulated symbols for a second decoding iteration for the series of received unknown symbols.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: June 24, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Elias Jonsson
  • Patent number: 8761318
    Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: June 24, 2014
    Assignee: Coherent Logix, Incorporated
    Inventors: David B. Drumm, James P. Golab, Jan D. Garmany, Kevin L. Shelby, Michael B. Doerr
  • Patent number: 8760780
    Abstract: A system and method for predicting the likelihood of failure of the individual sectors of a magnetic storage disk based upon the monitoring of adjacent sector performance in responding to access requests. The prediction for a specific target sector's fidelity can be made through the gathering of sector performance data that occurs during normal read/write actions to the adjacent sectors, without a recent access request necessarily being made to the target sector. Scrubbing of the sectors can also be directed based upon the needed sector access data for target sector fidelity prediction.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: June 24, 2014
    Assignee: Amazon Technologies, Inc.
    Inventor: Marc J. Brooker
  • Patent number: 8761322
    Abstract: The present disclosure presents methods and apparatuses for enhanced received signal processing using signal-based channel impulse response (CIR) estimation. For example, according to an example method presented herein, a user equipment (UE) or a component therein may receive a signal corresponding to a transmitted signal sent by a network entity, wherein the transmitted signal comprises at least a data channel, estimate chip contents of the transmitted signal, based on the received signal including the data channel, to obtain estimated chip contents, and compute an estimated channel impulse response (CIR) based on at least the estimated chip contents. Based on this estimated CIR, the UE may thereafter reprogram a received signal reconstruction filter, perform interference cancellation procedures, and/or adjust one or more equalizer taps. By performing such functions, the UE may exhibit improved communication characteristics and enable a more robust user experience.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: June 24, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Manish Jain, Aditya Dua, Manini Shah, Keith Saints, Farrokh Abrishamkar
  • Patent number: 8751895
    Abstract: A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Haruka Obata, Tatsuyuki Ishikawa, Hironori Uchikawa, Kenji Sakurada
  • Patent number: 8750433
    Abstract: A demodulation circuit includes a hard decision process unit and a soft decision process unit. The hard decision process unit is configured to perform a hard decision process using a demodulated signal, and the demodulated signal is a demodulated received signal. The soft decision process unit is configured to determine a range of assignment with respect to a transitioning part in the demodulated signal, calculate a likelihood value of a bit, and perform a soft decision process.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: June 10, 2014
    Assignee: Fujitsu Limited
    Inventors: Naoto Adachi, Masataka Umeda
  • Patent number: 8744017
    Abstract: A method and system for demapping a hierarchical signal is disclosed. The method includes receiving a hierarchical signal comprising first and second encoded, modulated signals. A conditional probability relating to the structure of the second encoded, modulated signal is determined. The hierarchical signal is demodulated using the conditional probability to generate a first encoded data stream. The first encoded data stream is decoded to recover information bits.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: June 3, 2014
    Assignee: CMMB Vision USA Inc.
    Inventors: Zixia Hu, Hui Liu
  • Patent number: 8744018
    Abstract: Certain embodiments provide methods that may allow for improvements in performance and power consumption by terminating the turbo decoding process early when one of at least two test criterion is satisfied in communications systems, including UMTS, WCDMA, and TD-DCMA.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: June 3, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jinghu Chen, Wanlun Zhao, Mingxi Fan, Fuyun Ling, Peter John Black
  • Patent number: 8739009
    Abstract: In iterative decoding, a data recovery scheme corrects for corrupted or defective data by determining reliability metrics for blocks of decoded data. Block or windowed detectors generate block reliability metrics for data blocks (rather than individual bits) of decoded data using soft information from the regular decoding mode or from new iterative decoding iterations performed during error recovery mode. An error recovery system triggers corrective decoding of selected data blocks based on the block reliability metrics, by for example, comparing the block reliability metrics to a threshold or by selecting an adjustable number of the least reliable data blocks.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: May 27, 2014
    Assignee: Marvell International Ltd.
    Inventors: Nedeljko Varnica, Yifei Zhang, Panu Chaichanavong, Gregory Burd
  • Patent number: 8732537
    Abstract: A probabilistic approach of symbol error estimation is disclosed. The probabilistic approach of symbol error estimation reflects the number of symbol errors more precisely than the number of unsatisfied checks. The more precise quality metric calculated in accordance with the present disclosure allows a codec system to achieve a better overall performance. In addition, many other features that previously depend on the number of unsatisfied checks as the sector quality metric may also benefit by adopting the more precise quality metric.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: May 20, 2014
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Wu Chang, Ming Jin, Shaohua Yang
  • Patent number: 8731114
    Abstract: A Log-Likelihood Ratio (LLR) combining method and apparatus for Hybrid Automatic Repeat Request (HARQ) in a wireless communication system for reducing a number of the LLR bits of previous packet stored for LLR combining are provided. The LLR combining apparatus includes an LLR combiner for combining a first LLR of a currently received packet and a second LLR of a previously received packet, an LLR buffer for storing the second LLR and a first packet exponent for recovering the second LLR in the same size as the first LLR, and an HARQ controller for determining whether the currently received packet is a retransmission packet or an initial transmission packet, and for controlling the LLR combiner to generate a third LLR by combining the first and second LLRs for the retransmission packet and to bypass the initial transmission packet.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seul Ki Bae, Joo Hyun Lee, Sung Hwan Kim
  • Patent number: 8726138
    Abstract: A method and apparatus for decoding of tailbiting convolutional codes (TBCC) are disclosed. The proposed modified maximum-likelihood TBCC decoding technique preserves error correction performance of optimal maximum-likelihood based TBCC decoding, while the computational complexity is substantially decreased since a reduced number of decoding states has been evaluated. Compare to other sub-optimal TBCC decoding algorithms, modified maximum-likelihood TBCC decoding achieves improved packet error rate performance with similar computational complexity.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: May 13, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Ju Won Park, Brian Banister, Je Woo Kim, Jong Hyeon Park, Matthias Brehler, Remi Gurski, Tae Chang
  • Patent number: 8719658
    Abstract: A method for accessing extrinsic information in a turbo decoder is disclosed. Operation phases for Forward State Metric Calculators (FSMCs) and Reverse State Metric Calculators (RSMCs) in multiple maximum a posteriori probability (MAP) decoders are misaligned differently based on whether a current half iteration is even or odd. First extrinsic information is read from a memory into the FSMCs and RSMCs using the misaligned operation phases. Second extrinsic information is determined using the MAP decoders. Each row of the second extrinsic information is stored to a different bank in the memory using the misaligned operation phases.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: May 6, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Zhiqiang Cui, Iwen Yao, Qiang Huang
  • Patent number: 8705666
    Abstract: In one aspect there is provided a method. The method may include receiving a signal transmitted through a channel; receiving an estimate of the channel; determining from the estimate of the channel at least one statistic representative of a variability of the estimate of the channel; decoding the received signal by at least searching for an output using a plurality of cost metrics determined based on at least the estimate of the channel and the at least one statistic; and providing, based on at least one of the plurality of cost metrics, the output. Related apparatus, systems, methods, and articles are also described.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: April 22, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Boon Sim Thian, Andrea Goldsmith
  • Patent number: 8707123
    Abstract: In one embodiment a variable barrel shifter includes a shifter operable to apply a cyclic shift to each of a number of portions of a data word, a pivot circuit operable to swap sections of the data word around at least one pivot point in the data word, a first multiplexer operable to select between an input of the variable barrel shifter or an output of the pivot circuit as an input to the shifter, a second multiplexer operable to select between the input of the variable barrel shifter or an output of the shifter as an input to the pivot circuit, and a third multiplexer operable to select between the output of the shifter or the output of the pivot circuit as an output to the variable barrel shifter.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: April 22, 2014
    Assignee: LSI Corporation
    Inventors: Dan Liu, Qi Zuo, Yong Wang, Yang Han, Shaohua Yang
  • Patent number: 8705665
    Abstract: A process for computing Log-Likelihood-ratios (LLRs) in a detector of a wireless communication receiver is disclosed, with the, LLRs being used by a channel decoder. A signal is received from a telecom front end, the signal corresponding to data belonging to a finite set of constellation symbols, each constellation symbol being arranged in a lattice constellation impaired by additive noise and a multiplicative channel. A limited set of distances representative of Euclidian distances between the received signal and a finite set of predetermined constellation symbols are computed, possibly multiplied by the channel. A set of soft decision LLRs are derived from the computed set of distances under the constraint of a limited length of the list of distances. The derived LLRs are completed by clipping values read from a look-up table which is simultaneously addressed by the values of the SNR and a bit index.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: April 22, 2014
    Assignee: ST-Ericsson SA
    Inventors: Andrea Ancora, Sebastien Aubert
  • Patent number: 8707146
    Abstract: A method for conditionally stopping execution of a turbo decoder is proposed. The decoder has elementary decoders. Each elementary decoder performs a sequence of decoding operations and is arranged to receive an input from at least one other elementary decoder. The method determines for each specific decoding operation if the sequence of elementary decoding operations of the specific elementary decoder has substantially converged or substantially diverged. The method terminates the execution of decoding operations if a number of sequences has substantially converged or substantially diverged.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: April 22, 2014
    Assignee: Ericsson Modems SA
    Inventors: Sébastien Charpentier, Andrea Ancora
  • Patent number: 8700979
    Abstract: An error correcting code decoding device includes a first decoding circuit, a word-length reduction circuit configured to reduce bit lengths of a first external values corresponding to a plurality of bits obtained after decoding process performed by the first decoding circuit a first predetermined number of times and to reduce bit lengths of words included in word string, and a second decoding circuit configured to decode the bit string by executing a decoding process a second predetermined number of times for calculating second external values and posterior values of the bits included in the bit string in accordance with the word string including the words having the reduced bit lengths using the first external values having the reduced bit lengths as second prior probabilities that corresponding bits among the plurality of bits are the predetermined value.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 15, 2014
    Assignee: Fujitsu Limited
    Inventors: Hiroaki Arai, Shunji Miyazaki, Kazuhisa Obuchi
  • Patent number: 8687746
    Abstract: Systems, methods, devices, and computer program products are described for Turbo decoding in a wireless communication system. Turbo encoded wireless signals may be received and demodulated, and forwarded to a branch metric calculator. The branch metric calculator may calculate a set of branch metrics for the demodulated signal. A state metric unit may receive the set of branch metrics and a previously calculated set of state metrics. The state metric unit may perform various comparisons of the set of state metrics before the received set of branch metrics is added to a portion of the state metrics identified through the comparisons.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: April 1, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Zhiqiang Cui, Iwen Yao, Qiang Huang
  • Patent number: 8681907
    Abstract: Iterative demapper. Demodulation and/or demapping of a signal (e.g., based on a constellation whose points have a corresponding mapping with associated labels) is performed such that each dimension is processed separately without accounting for influences from the other dimension. For example, the demapping process operates on each respective dimension separately and independently. In some instances, the processing operates iteratively, in that, information identified from processing one of the dimensions is employed in directing the processing in another of the dimensions. Such operation may be performed iteratively by updating/modified information associated with one or more of the dimensions as well. Moreover, decoding may operate in accordance with iterative demapping (e.g., error correction code (ECC) and/or forward error correction (FEC) code by which information bits are encoded) to make estimates of bits within a signal sequence, and those estimates may be used in a subsequent iteration of demapping.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: March 25, 2014
    Assignee: Broadcom Corporation
    Inventor: Kelly Brian Cameron
  • Patent number: 8683303
    Abstract: Operational parameter adaptable LDPC (Low Density Parity Check) decoder. A novel means is presented by which LDPC coded signal can be decoded, and any one or more operational parameters can be adjusted during the decoding processing. For example, the original information extracted from a received LDPC coded signal (e.g., log likelihood ratios (LLRs)), can be modified during (or before) the iterative decoding processing performed in accordance with decoding an LDPC coded signal. Such modification of an operational parameter can include any one or combination of scaling, compression (and expansion/decompression), adding an offset to or subtracting an offset from, scaling, rounding, and/or some other modification of an operational parameter. The bit (or variable) edge messages and/or the check edge messages can also undergo modification during decoding processing.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: March 25, 2014
    Assignee: Broadcom Corporation
    Inventor: Andrew J. Blanksby
  • Patent number: 8654873
    Abstract: In one embodiment, a Television (TV) receiver to perform a method of synchronizing a demodulator at a Viterbi decode input in the TV receiver using one or more bit de-interleaved even and odd Orthogonal Frequency Division Multiplexing (OFDM) symbols is provided. The method includes (i) performing a Viterbi decoding on the bit de-interleaved even and odd OFDM symbols when a frame boundary does not exist for the bit de-interleaved even and odd OFDM symbols, (ii) performing a convolutional encoding on an decoded data output of the Viterbi decoding, (iii) determining whether an output of the convolutional encoding of the bit de-interleaved OFDM symbols matches an input at a Viterbi decode, and (iv) determining whether the output of the convolutional encoding of the bit de-interleaved even and odd OFDM symbols matches with a SYNC pattern or a SYNC? pattern to obtain a RS packet align boundary.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 18, 2014
    Inventors: Gururaj Padaki, Sunil Hosur Rames, Rakesh A Joshi, Raghavendra Raichur, Rajendra Hegde
  • Patent number: 8656247
    Abstract: A matrix multiplier multiplies the signal output from a first adder by an inverse matrix T?1 of a partial matrix T of a parent parity check matrix, and outputs the multiplication result to a first switch. The output of the matrix multiplier becomes a second parity vector P2. A second switch is switched on at a transmission time of the information word vector ‘s’, a third switch is switched on at a transmission time of the first parity vector P1, and the first switch is switched on at a transmission time of the second parity vector P2. When a puncturing scheme is applied to the parent parity check matrix, a controller controls the first and second switches to puncture the parity according to the corresponding coding rate.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: February 18, 2014
    Assignees: Samsung Electronics Co., Ltd, Postech Academy Industry Foundation
    Inventors: Gyu-Bum Kyung, Hyun-Koo Yang, Se-Ho Myung, Hong-Sil Jeong, Kyeong-Cheol Yang, Dong-Seek Park, Jae-Yoel Kim
  • Patent number: 8650459
    Abstract: A log-likelihood ratio (LLR) for a bit bi in a message is determined by generating a first term, including by summing LLRs corresponding to bits in a first codeword having a specified value. The first codeword has a corresponding first message and bit bi of the first message corresponds to a 0. A second term is generated, including by summing LLRs corresponding to bits in a second codeword having the specified value. The second codeword has a corresponding second message and bit bi of the second message corresponds to a 1. The LLR for bit bi in the message is generated based at least in part on the first term and the second term.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: February 11, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Frederick K. H. Lee, Jason Bellorado, Zheng Wu, Marcus Marrow
  • Patent number: 8645808
    Abstract: A method for communication includes receiving at a receiver a signal from a transmitter embodying data encoded with an error correction code. The signal is processed in order to extract a sequence of samples in a complex signal space. Scalar values are extracted from the samples and the scalar values are processed so as to define one or more clusters of scalar data points. Gain and noise of the signal are estimated responsively to the defined clusters. Bit value metrics for the signal are computed based on the samples and the estimated gain and noise of the signal. The error correction code is decoded using the bit value metrics.
    Type: Grant
    Filed: October 28, 2012
    Date of Patent: February 4, 2014
    Assignee: Marvell International Ltd.
    Inventor: Meir Griniasty
  • Patent number: 8644432
    Abstract: A method for operating a Viterbi decoder uses few data move operations to improve efficiency. The Viterbi decoder predicts a state in which the convolution encoder might have operated while generating a convolutionally encoded data stream. The Viterbi decoder maintains a first set of states and based on the received convolutionally encoded data stream, predicts second and third sets of states. The Viterbi decoder then calculates first and second sets of decision bits based on the transitions to the second and third sets of states. Path metric values associated with the third set of states are stored in a memory buffer. Thereafter, during trace-back, the Viterbi decoder extracts first and second decoded bits from first and second sets of decision bits respectively.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Vatsal Gaur
  • Patent number: 8644431
    Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: February 4, 2014
    Assignee: Coherent Logix, Incorporated
    Inventors: David B. Drumm, James P. Golab, Jan D. Garmany, Kevin L. Shelby, Michael B. Doerr
  • Patent number: 8645810
    Abstract: A termination indication is computed during an iteration of an iterative decoding of a representation of a codeword according to a schedule. The termination indication is tested to see if the decoding has converged or is not likely to converge. The testing of the termination indication shows convergence or lack of likelihood thereof even if a codeword bit estimate was flipped during an immediately preceding traversal of the schedule. Preferably, the termination indication includes an error correction syndrome weight, a zero value whereof indicates convergence, and the computing of the termination indication includes, in response to the flipping of a codeword bit estimate, flipping the error correction syndrome bits that are influenced by that codeword bit estimate.
    Type: Grant
    Filed: July 31, 2011
    Date of Patent: February 4, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Eran Sharon, Idan Alrod, Ariel Navon, Omer Fainzilber, Simon Litsyn
  • Patent number: 8638886
    Abstract: A parallel implementation of the Viterbi decoder becomes more efficient when it employs end-state information passing as disclosed herein. The improved efficiency enables the usage of less area and/or provides the capacity to handle higher data rates within a given heat budget. In at least some embodiments, a decoder chip employs multiple decoders that operate in parallel on a stream of overlapping data blocks, using add-compare-select operations, to obtain a sequence of state metrics representing a most likely path to each state. Each decoder passes information indicative of a selected end-state for a decoder operating on a preceding data block. Each decoder in turn receives, from a decoder operating on a subsequent data block, the information indicative of the selected end-state. The end-state information eliminates any need for post-data processing, thereby abbreviating the decoding process.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: January 28, 2014
    Assignee: Credo Semiconductor (Hong Kong) Limited
    Inventor: Runsheng He
  • Patent number: 8640014
    Abstract: Soft bit metric generation computational complexity can be reduced by identifying and utilizing only the dominant terms in a reliability calculation such as a logarithmic likelihood ratio (LLR). The dominant terms are those terms for which the signs of the x and y components match those of channel outputs of the channel outputs. One technique for identifying the dominant terms is by determining the most likely transitions from two consecutive channel output samples Values for the dominant terms can be estimated by either the joint reliability of two consecutive samples of the in-phase component (x1,x2) or by the joint reliability of two consecutive samples of the quadrature components (y1,y2).
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: January 28, 2014
    Assignee: Acacia Communication Incorporated
    Inventors: Fan Mo, Sameep Dave, Christian Rasmussen, Mehmet Aydinlik
  • Patent number: 8635516
    Abstract: A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols and subtracts the intersymbol interference from the received signal. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: January 21, 2014
    Assignee: Agere Systems LLC
    Inventors: Kameran Azadet, Erich F. Haratsch
  • Patent number: 8630377
    Abstract: A method of detecting interference in a received sample vector using hidden Markov modelling by first estimating noise variance, where estimating noise variance comprises the steps of receiving a sample vector of noise and interference, sorting the sample vector in the frequency domain by order of increasing magnitude to produce an ordered vector, finding a sub-vector of the ordered vector that minimizes the distance from a noise measure, and estimating the noise variance.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: January 14, 2014
    Assignee: Industrial Research Limited
    Inventor: Alan James Coulson
  • Patent number: 8631306
    Abstract: A memory system comprises a non-volatile memory device that stores user data and state information regarding the user data. In a read operation of the non-volatile memory device, a memory controller calculates a priori probabilities for the user data based on the state information, calculates a posteriori probabilities based on the a priori probabilities, and performs a soft-decision operation to determine values of the user data based on the a posteriori probabilities.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: January 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki jun Lee, Hong Rak Son, Jun jin Kong