Abstract: A method for iteratively decoding a block turbo code includes: receiving a signal frame formed of a product code obtained by serially concatenating block codes; forming a reliability array for signal demodulation and initializing extrinsic reliability information; performing a complexity-reduced soft decision output Viterbi decoding algorithm for all of the codewords existing on a current axis and calculating extrinsic reliability using soft decision output information output as a result of the decoding; checking whether an iterative decoding completion condition is satisfied, and outputting a decoded value and terminating an iterative decoding process when the condition is satisfied; and normalizing reliability information when the condition is not satisfied, performing reliability equalization, and repeating the decoding process for a next axis.

Abstract: Metric calculation design for variable code rate decoding of broadband trellis, TCM (trellis coded modulated), or TTCM (turbo trellis coded modulation). A single design can accommodate a large number of code rates by multiplexing the appropriate paths within the design. By controlling where to scale for any noise of a received symbol within a received signal, this adaptable design may be implemented in a manner that is very efficient in terms of performance, processing requirements (such as multipliers and gates), as well as real estate consumption. In supporting multiple code rates, appropriately selection of the coefficients of the various constellations employed, using the inherent redundancy and symmetry along the I and Q axes, can result in great savings of gates borrowing upon the inherent redundancy contained therein; in addition, no subtraction (but only summing) need be performed when capitalizing on this symmetry.

Abstract: A method and apparatus are provided that reduce the amount of memory needed to perform forward-backward recursion to identify posterior probabilities. Under the invention, a forward recursion is performed to identify forward recursion scores. The forward recursion scores are then used directly in a backward recursion to determine posterior probabilities for each state in a set of time frames. The usefulness of this invention is especially high when there is a large number of discrete states, such as when there are more than one set of discrete states in the model.

Abstract: A data signal processing apparatus is capable of reproducing original data with a small number of repetition times of an iterative decoding process, which is realized by likelihood information operating means that generate updated likelihood information, carry out a predetermined operation on a plurality of pieces of likelihood information corresponding to the original data obtained by the iterative decoding process, and reproduce the original data.

Abstract: Several embodiments of a space diversity trellis interleaver system are provided for communicating data over a plurality of separate communication paths in order to inhibit distortion caused by impulse noise or other correlated noise and enhance the data transmission rate of data communications. The transmitter is designed to receive a plurality of data streams from data terminal equipment (DTE), which can be one or more devices. One or more convolutional encoders, preferably trellis encoders, encode each of the data streams. In an alternative embodiment, more than one trellis encoder is used to trellis encode each data stream. Data segments from the convolutionally encoded data streams are interleaved with a switch. The plurality of interleaved convolutionally encoded data streams are modulated and transmitted onto a respective plurality of separate communication paths. At the receiver, the plurality of data streams is received from the separate communication paths and demodulated.

Abstract: A decoding system and method for providing relatively high likelihood of obtaining at least two paths of getting to each decoding state from at least three paths. The system and method also selects a maximum likelihood path from the two paths, where a log likelihood of getting to a state in the decoder is determined by a soft-input value encoded with a trellis so as to provide at least three paths for getting to the state.

Abstract: A decoder that receives, as input, probability information AMP/CR×yt. This probability information is obtained by dividing a channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CA×APPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit. The soft-output decoding circuit, which may be a large scale intergrated circuit, generates log soft-output CI×I?t and/or external information 1/CA×EXt using additive coefficients for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit.

Abstract: Method and apparatus for soft bit computation with a reduced state equalizer. The method assures that the number of states in the equalizer is reduced to obtain acceptable complexity, while also ensuring that soft bit computation is performed for substantially all bits. The method involves computing a first set of soft bits from bits transmitted in a received signal, using a reduced-state trellis with finite non-zero delay, calculating hard decisions in response to the received signal, and also ensuring that substantially all soft bits are computed by employing zero-delay soft decision-making or decision-feedback equalization to compute a second set of soft bits. Furthermore, the hard decisions are used to compute the second set.

Abstract: A decision function generator for a Viterbi decoder includes a compressor module for receiving arguments of a decision function and for evaluating functions of the arguments of the decision function, a memory module coupled to the compressor module for generating an intermediate function from the functions of the arguments, and a decompressor module coupled to the memory module for generating a sign value, an integer value, and a fractional value constituting a value of the decision function from the intermediate function.

Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.

Abstract: An apparatus and method are described for mapping a plurality of multimedia streams (e.g., received from a set of satellite transponders) across a lesser plurality of decoders. In one embodiment, arbitration logic allocates the multimedia streams to divide the decoding load equally among the group of decoders (or at least as equally as possible). Allocation may occur statically, when the system is initialized, or dynamically, as the streams are being processed. In addition, in one embodiment, the arbitration logic monitors the amount of multimedia data for each stream stored in a buffer and causes streams to be serviced by the decoders which have relatively more stored multimedia data.

Abstract: A SOVA decoding method determines, for each information symbol time and each state of a decoding trellis, a vector of probabilities for each possible symbol value in accordance with transition path probabilities for reaching the state with respective information symbol values and probability vectors for the states at the previous information symbol time from which the state can be reached, and also determines a total probability for each state. A soft output is provided by summing probabilities for corresponding symbol values all states of the trellis at an information symbol time relating to the start of the vectors, corresponding to a desired survivor path length. The vectors can comprise probability ratios instead of probabilities to reduce storage especially for binary signal decoding, and logarithmic probabilities or ratios can be used to simplify computation.

Abstract: An Forward Error Correction (FEC) apparatus and method for reducing Bit error rates (BER) and Frame Error Rates (FER) using turbo decoding in a digital communication system. In a constituent decoder for decoding a turbo code, a first adder calculates the LLR of a received code symbol by calculating the difference between the probability of the code symbol being 1 and that of the code symbol being 0 at an arbitrary state of a turbo decoding trellis. A second adder adds the transmission information and a priori information of the code symbol. A third adder calculates the difference between the outputs of the first and second adders as extrinsic information. A first multiplier multiplies the output of the third adder by a predetermined weighting factor as a feedback gain. A correction value calculator calculates a correction value using the difference between the best metric and the second best metric of the code symbol. A fourth adder adds the correction value to the output of the first multiplier.

Abstract: The present invention provides a method of and an apparatus for changing the gain of a receive path amplifier during the middle of a packet transmission, and particularly changing the gain during a guard interval between a symbol with encoding bits disposed therein and a subsequent data symbol encoded in a manner corresponding to the encoding bits.

Abstract: Some embodiments of the present invention include a decoding system in which the decoding system uses iterative decoding techniques to decode signals encoded with lattice codes and/or multilevel coset codes. The decoding techniciucs according to some embodiments of the invention may be less complex than some decoding techniciues such as maximum likelihood decoding techniciues. Other embodiments of the prevent invention are described and claims.

Abstract: In a partial-response maximum-likelihood (PRML) signal detection and processing technique, reduction of data detection error events caused due to medium noise is achieved. For a PRML detection data result obtained after PRML data demodulation, a code error event that depends on a signal distance, and which has a high frequency of occurrences, is noticed and its occurrence probability is estimated. A locally-existing medium noise quantity is estimated from preceding and subsequent code patterns of the PRML detection data result. Based on this, the occurrence probability of the error event is compensated to improve the detection precision. As a result, data modulation with reliability higher than conventional maximum likelihood detection can be realized with a simple circuit structure.

Abstract: Methods and systems for performing iterative soft slicing methods are disclosed. A data signal is received and processed into individual data tones. A noise estimator provides noise estimates for each data tone. A beamformer utilizes the noise estimates to provide first and second components of a constellation point estimate. A ratio of the first and second components corresponds to the constellation point estimate. A soft slicer uses outputs from the beamformer and noise estimator to determine weighted constellation points without dividing the first component by the second component.

Abstract: Techniques are provided for the addition and comparison operations associated with a Viterbi decoding algorithm at substantially the same time. To this end, an operation of the type a±b>c±d (where a and b are to be added, c and d are to be added, and then the sums compared to determine the larger of the two sums) can be formulated, in accordance with the invention, into a±b?c?d>0 (where the addition of a and b and of c and d, and their comparison, are substantially concurrently performed). More specifically, in order to facilitate substantially concurrent addition and comparison operations in a Viterbi decoder, in one embodiment, the present invention performs multi-operand addition in a carry save form. With the results of addition represented in carry save form, the evaluation of comparator conditions is relatively straightforward.

Abstract: A data transmission method etc. are provided. At the transmitting side, an error-detecting code of the transmitted data is calculated, frame by frame, the error-detecting code is arranged after the corresponding transmitted data, and frame data is generated in such a way that bit arrangements of the transmitted data and of the error-detecting code are set in a reverse order to each other. At the receiving side, the transmitted data and the error-detecting code are assumed by assuming a final bit position of the frame data, frame by frame, for the received frame data and the error-detecting code of the assumed transmitted data is calculated. A position such where the assumed error-detecting code agrees with an error-detecting code calculated on the basis of the assumed transmitted data is determined to be the final bit position of the frame data.

Abstract: An approach is provided for transmitting messages using low density parity check (LDPC) codes. Input messages are encoded according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The LDPC codes are transmitted over a radio communication system (e.g., satellite network), wherein a receiver communicating over the radio communication system is configured to iteratively decode the received LDPC codes according to a signal constellation associated with the LDPC codes. The receiver is configured to iteratively regenerating signal constellation bit metrics after one or more decoding iterations.

Abstract: The present invention relates to a turbo decoder having a state metric, a calculating method using the turbo decoder and a computer-readable recoding medium for executing a calculation method implemented to the turbo decoder. The turbo decoder includes branch metric calculation unit, state metric calculation unit and log likelihood ratio calculation unit. The present invention may reduce calculation steps by simplifying a conventional turbo decode algorithm, reducing a size of a hardware, which the turbo decoder can be implemented in as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The present invention can be implemented in an error correction in wireless communication system and satellite communication system.

Abstract: A Viterbi equalizer for equalization of a data signal transmitted via a channel that is subject to interference has at least one add-compare-select unit (ACS), which carries out an ACS operation for each channel state in a time step k. Furthermore, the equalizer has a unit for calculating metric increments in advance and for storing the metric increments. The calculation unit calculates in advance the metric increments relating to all the transitions from a state which can be predetermined in the time step k to the states which can be reached by the transitions in the time step k+1. The metric increments are retained in an output memory such that they can be called up for utilization in the ACS unit.

Abstract: The invention concerns a method for jointly decoding and equalizing a digital signal protected by a trellis-defined code and transmitted though a channel. The method consists in carrying out a maximum likelihood estimate of each current bit xn by minimizing the quadratic error between the observed symbol Vn and the current symbol in the channel output zn, the quadratic error being calculated (1002) from the set of observed symbols based on the branch metric of the last transition en1(X)?en(X) according to the relationship (I); wherein k represents the rank of the coefficients of transverse filtering introduced by the radioelectric channel. The branch metric is calculated by backtracking through the successive states and the error propagating process is inhibited (1003) while backtracking through the successive states by storing at each node S survivors and by updating each survivor at the next time.

Abstract: Disclosed is a method of validating a byte sequence having a plurality of states, the method comprising designating one or more noise states from among the plurality of states; generating a most probable state sequence for the byte sequence; utilizing said state sequence to identify all noise in the byte sequence; and localizing said noise in said noise states. Once localized, the noise may be deleted from the byte sequence.

Abstract: A hybrid ARQ retransmission method in a communication system wherein data packets consisting of identical or partly identical modulation symbols encoded with a forward error correction (FEC) technique prior to transmission are retransmitted based on a repeat request and subsequently bit-level combined on the basis of soft-information values. The calculation of the soft-information values being input into an FEC decoder comprises the steps of calculating and buffering the soft-information values of the most significant bits (MSBs) of each (re)transmitted data packet; combining, for matching modulation symbols, the current soft-information values of the MSBs with the buffered soft-information values of at least one of the previous received transmitted packets; and calculating the soft information for at least some of the remaining bits (XSBs) from the combined soft information values of the MSBs.

Abstract: A method and apparatus for decoding turbo codes using a sliding window method is disclosed. In decoding a received sequence using a Maximum A Posteriori (MAP) algorithm, a learning by a backward processing is performed for a predetermined length and first resultant values of an L-symbol length sequence and second resultant values of a W-symbol length sequence calculated by a backward processing are stored. Third resultant values are calculated by a forward processing. The calculation of the third resultant values overlaps in time with the next learning. A decoding symbol output is determined using the third resultant values and the second resultant values of the previous window.

Abstract: A method and apparatus for decoding convolutional codes used in error-correcting circuitry for digital data communication. To increase the speed and precision of the decoding process, the branch and/or state metrics are normalized during the soft decision calculations, whereby the dynamic range of the decoder is better utilized. Another aspect of the invention relates to decreasing the time and memory required to calculate the log-likelihood ratio by sending some of the soft decision values directly to a calculator without first storing them in memory.

Abstract: A data transmission system is provided for transmitting user data to and receiving data from a communication channel, including a parity check matrix having M tiers, wherein M?2, Dmin=2*M for M=1 . . . 3 or 2*M?Dmin?6 for M>3, wherein Dmin is the minimum Hamming distance, tc=M, wherein tc is the column weight, and cycle?4=0. A linear block encoder encodes the user data in response to the parity check matrix, and a transmitter transmits an output of the linear block encoder to the communication channel. A soft channel decoder decodes data, and a soft linear block code decoder to decode data decoded by the soft channel decoder in response to the parity check matrix.

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed that uses precomputation (look-ahead) to increase throughput, with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract: According to an embodiment of the invention, the information is transmitted in symbols encoded at a source to a destination. A log likelihood ratio is respectively calculated for each of the encoded symbols. The calculated log likelihood ratios for the information bits are accumulated where the contribution from each of the encoded symbols is accounted for in the accumulating step. Each of the information bits is decoded according to the accumulated log likelihood ratios. An acknowledgment (ACK) is sent to the source for each block of the decoded information bits that passed the error check. A negative acknowledgment (NACK) is sent to the source for each block of the decoded information bits that did not pass the error check. After the source receives the negative acknowledgment (NACK), the encoded symbols are retransmitted to the destination.

Abstract: In a sequence estimation method and a sequence estimator of the present invention, a metric is calculated using a received signal and its estimated value, also another metric is calculated using a filtering result via a matching filter, one of these metrics is selected based on a characteristic of the channel or these metrics are combined, when a transmitted signal sequence transmitted from a transmission side is estimated based on a characteristic of a received signal and a channel using a list output Viterbi algorithm for deciding one or a plurality of survivors for each state of the Viterbi algorithm including one or more states. The operation speed and the characteristic of a channel can be improved using the smallest circuit scale even if the characteristic of a channel has a long delay time, in a sequence estimation method and a sequence estimator.

Abstract: A decoder for performing log-sum corrections by means of a linear approximation, putting stress on speed, with a reduced circuit dimension without adversely affecting the decoding performance of the circuit. The decoder includes a linear approximation circuit that computes the log-sum corrections using the function F=?a P?Q+b, where the coefficient ?a represents the gradient of the function and the coefficient b represents, the intercept and are expressed by a power exponent of 2.

Abstract: A method and an apparatus for determining the log-likelihood ratio of a received signal. The log-likelihood ratio is determined by calculating distance between the received symbol and closest constellation point matching a bit and the distance between the received symbol and the closest constellation point not matching the bit.

Abstract: The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an interleaved forward-reverse addressing which greatly relieves the amount of memory required. This approach is in marked contrast to conventional turbo decoders which employ either a dual port main memory or a single port main memory in conjunction with a complex ping-ponged scratch memory. In the system of this invention, during each cycle accomplishes one read and one write operation in the scratch memories. If a particular location in memory, has been read, then that location is free. The next write cycle can use that location to store its data. Similarly a simplified beta RAM is implemented using a unique addressing scheme which also obviates the need for a complex ping-ponged beta RAM.

Abstract: A method and apparatus are disclosed for MAP decoding of signals encoded using error correction codes to make maximum probability decisions about each transmitted bit. A MAP decoding algorithm is disclosed that exploits properties of Reed-Muller error correction codes that use q-ary block codes to provide a decoding algorithm having a complexity that is proportional to n logq n for Reed-Muller codes. The disclosed MAP decoding algorithm employs two matrices D and {overscore (D)} to represent the code set and has an overall complexity that is exponential for a general code set. For Reed-Muller codes, the disclosed MAP decoding algorithm employs matrices Bi and {overscore (Bi)} that are sparse matrices (i.e., contain many zero entries), thereby reducing the number of required operations and yielding a complexity that is proportional to n logq n.

Abstract: A coding section 101 performs error detection coding of data for each predetermined error detection unit, and an M-ary modulation section 102 arranges data belonging to a plurality of error detection units in one transmission unit, and transmits that data. A first decoding section 114 decodes a received signal, and performs error detection on the decoding result for each error detection unit. A second demodulation section 115 modifies the likelihood of each bit based on the result of error detection in the first decoding section 114. By this means, it is possible to improve the error correction capability of a signal that has undergone M-ary modulation using high-precision likelihoods, and to improve transmission quality.

Abstract: In a data recording apparatus, values of parity bits to be additionally provided every one predetermined length block in data obtained by demodulating the original data are determined so as to satisfy a part of or an entire the predetermined run length limitation rule in ranges of a current predetermined length block, the plurality of parity bits, and a next predetermined length block that is positioned next to the current block. The parity bits having the values are additionally provided to the current block.

Abstract: A multi-user turbo decoder combining multi-user detection and forward error correction decoding is disclosed in which randomly ordered indices are assigned to interfering users before a decoding tree is constructed in the multi-user decoder for each symbol interval for every iteration and for each new block of data. By building the decoding tree in this manner for each symbol interval, a reduced complexity search is more likely to include paths (and nodes) in the tree containing the correct value for the channel symbols. All users thus share in the benefit of root level placement in the decoding tree. In an alternative embodiment of the invention only one decoding pass is accomplished and there is no re-construction of the decoding tree based on further random index ordering for iterative decoding. No modification to the transmitted signaling method is needed.

Abstract: An apparatus for and method of generating normalized soft decision information output from an inner decoder (i.e. equalizer) in a communications receiver. The invention is operative to normalize the soft decision information before it enters a soft outer decoder. The normalization is performed using a noise power estimate that is dynamically calculated in response to changing noise statistics on the channel. The normalized soft decision output is then applied to the soft outer decoder thus realizing maximum performance therefrom. The noise power estimate is derived from the training sequence and/or the data portion of the received signal. Both types of estimates are calculated. A binary or smoothly weighted average is calculated using both types of estimates. The weighting factor is determined based on one or more performance metrics, such as the Signal to Noise Ratio (SNR).

Abstract: A branch metric calculation unit calculates a set of branch metric values for subsequent samples of the sampled input signal. Each of the set of branch metric values is an indication for the likelihood that an amplitude value of a sample corresponds to a particular state, a state being defined as a sequence of n-ary digits. A delay unit, which forms part of a delay chain of delay units, includes a first delay unit of the delay chain which is coupled to the branch metric calculation unit. A path metric calculation chain of path metric calculation units includes one or more path metric calculation units having first inputs coupled to a delay unit and second inputs coupled to a preceding path metric calculation unit. The path metric calculation unit calculates the path metric values from the branch metric values, a path metric value being on indication for the likelihood that a sequence of samples corresponds to a sequence of states.

Abstract: A digital data storage (DDS) system for reading DDS tapes employs a partial response maximum likelihood detection system which utilises redundancy in the 8-10 DC free modulation encoding to reduce low frequency noise. The system incorporates a time-varying trellis decoder which embodies some of the PR1 rules together with the rules regarding the charge state or the digital sum variation (DSV) implicit in 8-10 modulation coding. The decoder operates to reject low frequency noise such as that caused by crosstalk noise between adjacent tracks on the tape. The trellis topography has been considerably simplified by adopting a two step six state trellis which operates on bit pairs and in which the states relate to the current DSV value, and sign of the previous bit.

Abstract: Radiocommunication systems, methods and terminals are described wherein metrics associated with MLSE detecting techniques, e.g., using the Viterbi algorithm, are accumulated in a manner which is less computationally intensive than conventional techniques. The delta metrics associated with each state are partitioned into, for example, six different terms. These terms are then selectively accumulated in phases, before decisions, during decisions and after decisions, to reduce the total number of computations associated therewith. Additionally, certain symmetries associated with exemplary modulations are taken into account in order to further simplify processing and memory requirements of these detecting techniques.

Abstract: A method and device for adaptive quantization of soft bits includes numerically sorting soft bits of an external data block having a log likelihood ratio distribution of the soft bits, each of the soft bits having a value, the sorted soft bits having extreme values, determining two point values in the log likelihood ratio distribution of the data block respectively located at a clipping distance away from each extreme value of the sorted soft bits, defining an adapted quantization range with a half-length equal to half of a difference between the two point values or with a half-length equal to a larger of two absolute values of the two point values, and placing each of the soft bits within a respective sub-range of the adapted quantization range. An adapted quantization range is determined whenever the log likelihood ratio distribution of the data block changes.

Abstract: An arrangement for selecting the largest of a plurality of input currents (pma (k?1), pmb (k?1)) and adding a further current (Ibmk) to the selected current, the arrangement comprising: a plurality of inputs (901, 902) for receiving said input currents; a further input (905) for receiving said further current; an output (906, 907) for delivering an output current proportional to the sum of the largest of the input currents and the further current; means for feeding each of the received input currents to the main current conducting path of a respective transistor, (T900, T902) each of the transistors having its control electrode connected to a common point; a respective follower transistor (T901, T903) connected between the input and the common point; and a mirror transistor (T904) having its control electrode connected to the common point for producing a current whose value is related to that of the largest input current.

Abstract: An iterative turbo decoder and method for error correcting communication signal data are provided. The decoder implements a stopping rule through use of signature codes to determine whether successive iterations of decoder data are the same.

Abstract: A data compression method for executing encode commands for PackBits compression by a processor. The encode commands include a first command to obtain an encode processing state of the PackBits compression and control output of a control code (+1, ?2 etc.) based on the encode processing state, a second command to control output of input data (A to F) based on the encode processing state, and a third command to control output of a control command upon completion of the PackBits compression. In this arrangement, the PackBits encode processing can be performed at a high speed by the processor.

Abstract: A method is described for decoding a signal in a noise environment using maximum likelihood soft decision decoding for input streams containing known data. ISI problems are ameliorated, and decoding is implemented by palmtop computers and devices of limited computational capability. Decoded signals make use of the (12, 8) Hamming Code for a MOBITEX application. A table with predetermined ISI values is downloaded from a host processor to an on-board DSP at runtime. Known information in the frame header is utilized to help determine unknown data. Decoding proceeds in one embodiment by finding codewords that minimize a sum corresponding to data values extracted from header information. Other tables generated for use contain soft decision information and FEC words. Minimizing data translation by using known data and other embodiments advantageously minimize computational resources required to decode data by maximum likelihood soft decision decoding.

Abstract: A system and method for improving error detection and correction for transmitted data. An iterative error detection method is used to determine a relative likelihood that decoded data is an accurate representation of the original data. An independent error correction unit operates on the decoded data and a result from the independent error correction unit is injected into the iterative error detection method to improve the reliability of the error detection method.

Abstract: A communication system is composed of an encoder encoding an input sequence to sequentially generate output codes X0, X1, . . . , and a decoder decoding the output codes by a MLSD (Maximum Likelihood Sequence Detection) method with a trellis memory length being L. The output code Xk of the output codes X0, X1, . . . is determined based on the input sequence for k that is not equal to i(N+1) with i being any of natural numbers and with N being a natural number. The output code Xi(N+1) of the output codes X0, X1, . . . are uniquely determined based on a subset of a set consisting of the output codes Xi(N+1)?L+1, Xi(N+1)?L+2, . . . , Xi(N+1)?1 of the output codes X0, X1, . . . The subset includes the output code X1(N+1)?L+1 of the output codes Xi(N+1)?L+1, Xi(N+1)?L+2, . . . , X1 (N+1)?1.

Abstract: A method and a system for decoding information signals encoded by a multi-state encoding architecture and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are detected in a symbol decoder, implemented using look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The symbol decoder is implemented as a pair of slicers, each detecting an input signal with respect to one of two disjoint symbol-subsets. A third slicer detects the input with respect to the union of the two disjoint symbol-subsets. Decisions from the first, second and third slicers are processed to define 1D square error terms expressed in Hamming metrics. Reduced bit count error terms allow follow-on error processing to be performed with a minimum of computational complexity.