Abstract: A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.

Abstract: An ECC determining unit determines whether an error detected by using an ECC has been corrected. When the detected error has not been corrected, an equalizer output sequence transfer unit transfers an equalizer output sequence yk stored in an equalizer output sequence storage unit to a transfer data storage unit in a hard disk controller, so that a high-performance decoding unit (software) performs repetitive decoding, using the transferred equalizer output sequence yk.

Abstract: A method (700) and apparatus (600) are described for performing 2M?1 parallel ACS operations to generate 2M path metric outputs and buffering the 2M path metric outputs in connection with a track buffer (112) in an Ultrawide Bandwidth (UWB) receiver for decoding a message sequence encoded according to a convolutional code. Contents of the track buffer are updated in accordance with Register Exchange and outputs from the track buffer can further be input to a voting unit (114) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.

Abstract: A method for detecting signals affected by intersymbol interference provides for a path memory in the form of a trellis admitting survivor paths comprising a first and a second stage. The first stage includes a shift register exchange with a given number of states and a given length ?. The first stage outputs a first state SAkk-? on the survivor path for the best state Ak, and a second state SBkk-? on the survivor path for another state Bk. The second stage is configured as a two-state shift register exchange having a respective memory length ?, including respective first and second registers. In the respective first and second registers the survivor paths are stored leading to a respective first ?0k and second ?1k state, whereby the respective first register contains the backend of the best survivor path, while the respective second register contains the backend of an alternative survivor path.

Abstract: A data recording and reproducing system adds a first error correcting code to input data to generate a first code block, encodes the first code block with a second error correcting code to generate a second code block, interleaves the second code block to generate a recording block, and records and reproduces the recording block via a partial response channel including a recording medium. An output signal from the partial response channel, and thus the second code block, is decoded; the decoded data and the reliability of the decoded data is determined, based on likelihood information obtained during iterative decoding; and the first error correcting code is decoded. The decoded data and the reliability information are supplied to the first error correcting code decoder.

Abstract: A data recording/reproducing method and apparatus for correcting data errors on a recording medium even with the use of a conventional ECC. The data recording/reproducing apparatus includes a generation unit that generates predetermined data units by dividing an ECC sector including error correction codes generated by an error correction encoder into prescribed data units and encoding the prescribed units into iterative encoded data units using an iterative encoder so that the predetermined data units may include the iterative-encoded data units, a recording unit, a reproducing unit, an iterative decoder for conducting iterative decoding on the predetermined data units, and an error correction decoder. The apparatus further includes a distribution unit for distributing the predetermined data units generated by the generation unit. The distribution unit distributes the iterative encoded data units using at least two ECC sectors and records the distributed data units on a recording medium.

Abstract: A path-select-signal memory section in the Viterbi detector outputs each decoded data B?Sik corresponding to a branch that occurred a prescribed time ago in a surviving path to each state at a present time, in response to path select signals SEL0, SEL1. A shift register stores the path select signals SEL0, SEL1 in order of time. A binary output unit outputs a decoded bit corresponding to a branch that occurred a prescribed time ago in a surviving path. Output signal lines of the binary output unit and a selector train are connected according to a trellis diagram that corresponds to encoding operation.

Abstract: A data detection and decoding system in which a single parity bit added to the end of each code word by the encoder is used in the channel detector to improve the accuracy with which bit decisions are made in the channel detector. The bit estimates and the reliability estimates are then processed by the decoder to recover the original input bits. By using single parity for this dual purpose in combination with a decoder that follows the channel detector and uses the bit estimates and reliability estimates to recover the original input bits, performance of the data detection and decoding system is greatly improved while also overcoming the disadvantages of known digital recording systems.

Abstract: Turbo encoded data is received in a wireless communication system. A signal is received including the turbo encoded data. An initial data estimation is performed on the received signal. At least one iteration of turbo decoding is performed on the estimated data. A subsequent data estimation is performed using the received signal and the result of the turbo decoding. At least one iteration of turbo decoding is performed on a result of the subsequent data estimation.

Abstract: Decoder design adaptable to decode coded signals using min* or max* processing. A very efficient means of min* processing or max* processing may be performed within a communication device to assist in the very complex and cumbersome calculations that are employed when decoding coded signals. The types of coded signals that may be decoded using min* processing or max* processing are varied, and they include LDPC (Low Density Parity Check) coded signals, turbo coded signals, and TTCM (Turbo Trellis Coded Modulation) coded signals, among other coded signal types. Many of the calculations and/or determinations performed within min* processing or max* processing are performed simultaneously and in parallel of one another thereby ensuring very fast operation. In a finite precision digital implementation, when certain calculated bits of min* or max* processing are available, they govern selection of resultants from among multiple calculations and determinations made simultaneously and in parallel.

Abstract: An iterative method and a device for decoding received signals transmitted in data frames via various channels. In order to be able to utilize the computing capacity of digital signal processors (DSPs) as efficiently as possible, it is proposed that, starting at a first channel, the quality of the decoded signal transmitted via the first channel is checked following every iteration and switchover takes place to at least one further channel if a specifiable switchover condition exists. The switchover condition may, for example, be a specifiable quality of the decoded signal transmitted via the channel under consideration. To determine the quality of the decoded signal a cyclic redundancy check (CRC), in particular, is proposed following every iteration.

Abstract: An approach is provided for transmitting messages using low density parity check (LDPC) codes. Input messages are encoded according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The LDPC codes are transmitted over a radio communication system (e.g., satellite network), wherein a receiver communicating over the radio communication system is configured to iteratively decode the received LDPC codes according to a signal constellation associated with the LDPC codes. The receiver is configured to iteratively regenerating signal constellation bit metrics after one or more decoding iterations.

Abstract: Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to perform updating of edge messages with respect to bit nodes as well as updating of edge messages with respect to check nodes in the context of decoding LDPC coded signals. In addition, several very efficient architectures are presented to performing check node processing that involves the updating of edge messages with respect to check nodes. One embodiment performs check node processing using min** (min-double-star) processing in conjunction with min**? (min-double-star-minus) processing. Another embodiment performs check node processing using min†† (min-double-dagger) processing in conjunction with min†? (min-dagger-minus) processing. In addition, a single FIFO may be implemented to service a number of macro blocks in a parallel decoding implementation.

Abstract: The need for separate CRC bits is eliminated by taking advantage of what has been determined to be an embedded error detection capability of the tail bits generated by the constituent encoders of a turbo coder to perform error detection following turbo decoding. Specifically, it has been recognized that the tail bits are similar to CRC bits that would be generated by a CRC encoder that uses as its generating polynomial the feedback polynomial used by the turbo encoder. At the turbo decoder, after a final turbo decoding iteration cycle, a check is performed on the decoded systematic information bits by calculating the tail bits from the decoded information bits using that generating polynomial and bit-by-bit comparing the calculated tail bits with the systematic tail bits decoded by the turbo decoder. If a mismatch occurs at one or more bit positions, an error is indicated.

Abstract: An apparatus for reproducing data includes a branch metric computation unit and a plurality of parallel computation units. Each parallel computation unit includes path metric computation units that compute path metric values based on branch metric values. Path metric memories store the path metric values to be used in a next following path metric computation, and reliability computation units compute path reliability. Modified-path generating units generate an inverted path that is inverse to a path indicated by an output of the reliability computation units as having low reliability. If any one of the modified-path generating units generates the inverted path, a corresponding one of the path metric computation units stores a path metric value corresponding to the inverted path in a corresponding one of the path metric memories as a path metric value to be used in a next following path metric computation.

Abstract: A method of decoding is provided comprising processing iterations. In each processing iteration, there is a first Max-Log-MAP decoding operation giving rise to a systematic error due to the Max-Log approximation, and a first weighting operation to weight extrinsic information from the first decoding operation to be applied as a priori information to the second Max-Log-MAP decoding operation. This is followed by a second Max-Log-MAP decoding operation, also giving rise to a systematic error due to the Max-Log approximation, and a second weighting operation to weight extrinsic information from the second decoding to be applied as a priori information to the first Max-Log-MAP decoding of the next iteration. The weights are applied to compensate for the systematic error due to the Max-Log approximation made in the last Max-Log-MAP decoding operation.

Abstract: At the receiver in a wireless communications system, the likelihood of a false CRC pass that can occur when a weak received signal produces an all ZERO output from a convolutional or a turbo decoder is minimized. To prevent an all ZERO output, a convolutional decoder selects from among those determined equally most likely transmitted sequences of bits in a data block one that has a weight greater than the one having the minimum weight. A turbo decoder selects a ONE rather than a ZERO as the value of a transmitted bit in a data block when for that bit a bit value of a ZERO and a ONE are determined to be equally likely.

Abstract: IPHD (Iterative Parallel Hybrid Decoding) of various MLC (Multi-Level Code) signals. Various embodiments are provided by which IPHD may be performed on MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signals mapped using a plurality of mappings. This IPHD may also be performed on MLC LDPC coded modulation signals mapped using only a singe mapping as well. In addition, various embodiments are provided by which IPHD may be performed on ML TC (Multi-Level Turbo Code) signals. These principles of IPHD, shown with respect to various embodiments IPHD of MLC LDPC coded modulation signals as well as the IPHD of ML TC signals, may be extended to performing IPHD of other signal types as well. Generally speaking, based on the degree of the MLC signal, a corresponding number of parallel paths operate in cooperation to decode the various levels of the MLC signal.

Abstract: A Viterbi decoder that identifies errors in a full decision output comprises a full decision generator that generates the full decision output. An error detector detects errors in the full decision output and generates a signal when the full decision output errors are detected.

Abstract: A Viterbi decoder that identifies errors in an early decision output comprises an early decision generator that generates the early decision output. An error detector detects errors in the early decision output and generates a signal when the early decision output errors are detected.

Abstract: A maximum a posteriori probability (MAP) block decoder for decoding a received data block of input samples. The MAP block decoder segments the received data block into at least a first segment and a second segment and calculates and stores alpha values during forward processing of the first segment. The MAP block decoder uses a first selected alpha value calculated during forward processing of the first segment as initial state information during forward processing of the second segment. The first and second segments may overlap each other, such that the last M samples of the first segment are the same as the first M samples of the second segment.

Abstract: A system and method are provided for maximum likelihood estimation in a channel receiving data with inter-symbol interference (ISI). The method receives a serial stream of digital information bits. Decisions are made concerning the received information bit values, which the method accepts as processed information, with soft decisions (SDs) and corresponding initial hard decisions (HDs). The method then identifies a sequence of processed information in a correction matrix, and uses the correction matrix to cross-reference the sequence to a HD look-up value. In response to accessing the HD look-up value, a modified HD is created. The modified HD is decoded, for example, by using forward error correction (FEC), creating a decoded HD. The method compares the decoded HD to the initial HD, and updates the correction matrix HD look-up value in response to the comparison.

Abstract: Methods and apparatus are disclosed for soft decision decoding using reliability values based on a log base two function. A signal is processed to determine one or more reliability values for a soft decision decoder by computing one or more log-likelihood ratio (LLR) values using a log base two function. The soft decision decoder may employ, for example, a belief propagation algorithm. The soft decision decoder can decode, for example, Low-Density Parity Check codes or turbo codes.

Abstract: Methods and apparatus that do not require a memory between the combiner and decision boundary estimator in a digital communications receiver and that enjoy unaltered performance are described. The methods and apparatus include new ways of estimating bit decision boundaries and may also include new ways of estimating soft bit values.

Abstract: An apparatus and method for turbo decoding using a variable window size. A control logic block receives information about a code rate of received data bits and a data block size, adjusts a window size according to the code rate information, and computes an initial delay. Delta metric blocks compute delta metrics from input data bits of the block size, wherein the delta metrics represent a transition probability for a path from a state to another state, respectively. An alpha metric block receives a delta metric in synchronization with the initial delay, and computes an alpha metric representing a forward state transition probability in each state. One or more beta metric blocks receive delta metrics according to the adjusted window size, and compute beta metrics representing a backward state transition probability in each state, respectively.

Abstract: A digital signal decoding device according to an aspect of the present invention is a digital signal decoding device for generating a binary code sequence by maximum likelihood estimation from a convolutionally encoded input signal sequence, includes an add-compare-select unit configured to compare only two metric values one unit time before the calculation time of a predetermined branch metric value calculated from the input signal sequence at two successive times at each time, to add the predetermined branch metric value to the two metric values independently of the compare process, to select one of the two sums in accordance with the comparison result of the two metric values, and to output the selected value as a metric value to be used at the next time.

Abstract: A soft demodulation method and apparatus including calculating partial sums for a unit of each predetermined number of bits of a codeword received from a channel; calculating a value of each entry of the decoding table by referring to the partial sums; and detecting a maximum among values of all entries of the decoding table and calculating a log-likelihood ratio (LLR) using the detected maximum. Accordingly, it is possible to reduce the amount of computation required to perform a soft demodulation process using run-length limited (RLL) codes and to simplify the soft demodulation process.

Abstract: Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon's limit. In the instance of LDPC coded signals, various level LDPC codewords (e.g., an MLC block) are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks that corporately form an MLC block. Encoded bits from levels of the MLC block are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.

Abstract: In one or more embodiments, a method of processing a soft value sequence according to an iterative soft-input-soft-output (SISO) algorithm comprises carrying out sliding-window processing of the soft value sequence in a first iteration using first window placements and in a second iteration using second window placements, and varying the window placements between the first and second iterations. In at least one embodiment, a communication receiver circuit is configured to carry out iterative SISO processing, wherein it processes a soft value sequence using sliding windows, and wherein it varies window placements between one or more iterations. The communication receiver circuit comprises, for example, all or part of a turbo decoding circuit or other type of iterative block decoding circuit, an equalization and decoding circuit, a soft demodulation and decoding circuit, a multi-user detection and decoding circuit, or a multiple-input-multiple-output detection and decoding circuit.

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract: The present invention discloses a method and system for improving the decoding efficiency in a wireless receiver to obtain a correct decoded data string. The method comprises generating an active state metric matrix of a receiving codeword, calculating a differential metric matrix pertinent to the active state metric matrix, identifying a maximum likelihood path and one or more alternative paths based on the differential metric matrix, deriving a first decoded data string corresponding to the maximum likelihood path, deriving a plurality of second decoded data strings corresponding to the one or more alternative paths, respectively examining the integrity of the first decoded data string; and examining the integrity of the plurality of second decoded data strings after the first decoded data string is determined erroneous, wherein the wireless receiver obtains the correct decoded data string.

Abstract: A trellis traceback apparatus and method are disclosed. In one aspect, the apparatus may include a branch indication memory, memory address logic, a selector, and a shift register. The memory may store branch indication information for a state at a section, the information indicating a branch that leads to the state. The memory address logic may indicate the section. The selector may receive the branch indication information for the state at the indicated section. The selector may select the branch indication information based on received selection information. The shift register may provide information stored in a plurality of register segments to the selector as the selection information, and the shift register may receive and store the selected branch indication information.

Abstract: A second stage SOVA detector comprises a dynamic state reordering block with inputs that receive absolute state domain data from a first stage SOVA detector. The second stage SOVA detector provides relative state domain data outputs and selection bit outputs. The second stage SOVA detector comprises pipeline registers. The pipeline registers receive the relative state domain data outputs and the selection bit outputs and provide pipelined outputs. The second stage SOVA detector comprises a reliability update-register exchange unit receiving the pipelined outputs and providing detected data bits and reliabilities.

Abstract: Inverse function of min*:min*? (inverse function of max*:max*?). Two new parameters are employed to provide for much improved decoding processing for codes that involve the determination of a log corrected minimal and/or a log corrected maximal value from among a number of possible values. Examples of some of the codes that may benefit from the improved decoding processing provided by the inverse function of min*:min*? (and/or inverse function of max*:max*?) include turbo coding, parallel concatenated trellis coded modulated (PC-TCM) code, turbo trellis coded modulated (TTCM) code, and low density parity check (LDPC) code among other types of codes. The total number of processing steps employed within the decoding of a signal is significantly reduced be employing the inverse function of min*:min*? (and/or inverse function of max*:max*?) processing.

Abstract: A maximum a posteriori (MAP) processor employs a block processing technique for the MAP algorithm to provide a parallel architecture that allows for multiple word memory read/write processing and voltage scaling of a given circuit implementation. The block processing technique forms a merged trellis with states having modified branch inputs to provide the parallel structure. When block processing occurs, the trellis may be modified to show transitions from the oldest state at time k?N to the present state at time k. For the merged trellis, the number of states remains the same, but each state receives 2N input transitions instead of the two input transitions. Branch metrics associated with the transitions in the merged trellis are cumulative, and are employed for the update process of forward and backward probabilities by the MAP algorithm.

Abstract: Method for computing distances to received data points. A preferred embodiment comprises determining a first point on a grid nearest to the received point, computing a second point closest to the received point inside a specified area, wherein the second point is a point in a first coset, computing a third, fourth, and fifth point, wherein each point is a member of a different coset and each point is the closest point in its coset to the received point, and computing a distance from the received point to each of the second, third, fourth, and fifth points.

Abstract: A reduced complexity turbo decoding scheme combines elements from two MAP (Maximum a posteriori) algorithms, namely a LogMAP algorithm and a max-LogMAP algorithm. Forward and backward recursive metrics are computed in accordance with the max-LogMAP algorithm, while output extrinsic LLR (Log Likelihood Ratio) values are computed in accordance with the LogMAP algorithm.

Abstract: A radio frequency identification (RFID) decoding subsystem includes a pre-decode module and a decode module. The pre-decode module is coupled to process down-converted RFID signals into pre-decoded baseband data. The decode module is coupled to: enable a counting process based on the pre-decoded baseband data to produce a count resultant; and compare the count resultant with a threshold at a data bit interval to produce decoded RFID data.

Abstract: A method decodes a noisy signal from the coordinates of a point in a point constellation, each point associated with a digital data item of a determined number of bits, consisting of determining components of a received point; determining a reference point corresponding to the constellation point closest to the received point; determining at least one concurrent point corresponding to the constellation point closest to the reference point, having a bit of determined rank opposite to the bit of determined rank of the reference data; and determining, at least for the bit of the reference digital data at said determined rank, a precision data item based the received, reference, and concurrent points, in which the determination of the bits of the concurrent point is performed based on the values of some of the bits of the reference digital data and on said rank.

Abstract: A channel condition detecting unit detects a condition of a channel between a transmitting apparatus and a receiving apparatus, in accordance with a pilot signal. A reference check matrix employed for LDPC coding in the transmitting apparatus is stored in the check matrix reconstructing unit. The check matrix reconstructing unit reconstructs the reference check matrix in accordance with a detection result of the channel condition detecting unit. An LDPC decoding unit obtains a probability value of each of bits in the receive data by executing the LDPC decoding operation based on a check matrix supplied from the check matrix reconstructing unit, for a likelihood value of each of the bits in an encoded bit sequence input from a detecting unit. A hard decision unit subjects a probability value of each of bits in the receive data to hard decision and obtains the receive data.

Abstract: An ECC decoder outputs, to a likelihood substituting unit, information on data in data blocks that is corrected to be valid. Based on the information, the likelihood substituting unit substitutes likelihood corresponding to the data corrected to be valid by the maximum value, and outputs it to an LDPC decoder. The LDPC decoder decodes user data with likelihoods partly substituted by the maximum value using LDPC parity, and calculates likelihood of data that constitutes the user data. The LDPC decoder outputs the calculated likelihood to a channel APP decoder as external data.

Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Abstract: The present invention provides a reduced memory implementation for the min-sum algorithm compared to traditional hardware implementations. The improvement includes innovative MIN_SUM method with reduced memory requirements suitable of computer implementation that combines the traditional row update process and column update process into a single process, in that the traditional CNU unit and VNU unit are combined into a single CVNU unit. The improvement not only reduces the time required for decoding by half, but also reduces the logic and routing efforts. Furthermore, instead of storing the whole intermediate LLR values using a significant number of memories, only a set of parameters associated with the intermediate LLR values is stored. The set of parameters includes: 1. sign of LLR; 2. the minimum LLR, 3. sub-minimum LLR, and 4. the column location of minimum value in each row.

Abstract: A branch metric duplication method substantially reduces interconnection delays. The branch metric duplication method is particularly useful to implement a high speed radix-4 Viterbi decoder targeted for FPGA applications. The decoder includes a plurality of branch metric computation units (BMCUs), at least one add-compare-select unit (ACSU) having a plurality of cells, and a survivor path memory unit (SMU). The plurality of BMCUs, the at least one ACSU, and the SMU are configured to implement the decoder.

Abstract: The present invention is a multi-carrier communication system for transmitting/receiving signals via at least four sub-channels, comprising: a transmitter for transmitting data independently via the four sub-channels; a receiver comprising a receive unit disposed for each sub-channel for receiving data from a corresponding sub-channel and performing soft decision of the receive data; and means for inputting soft decision target values in receive units corresponding to three sub-channels other than a target sub-channel to a receive unit of the target sub-channel, wherein the receive unit of the target sub-channel adjusts its own soft decision target value using the soft decision target values that are input from the receive units of the other sub-channels, and decides the receive data based on this adjusted soft decision target value.

Abstract: A decoding process for decoding a received block of N systematic binary data samples or N systematic duobinary data samples using a maximum a posteriori probability (MAP) decoding algorithm. The decoding process calculates a set of four log-likelihood values using the corresponding forward state metric, reverse state metric, and branch metric values for each of N/2 pairs of systematic binary data or each of N/2 pairs of duobinary data in the received block. The decoding process also calculates, for each set of four log-likelihood values a delta value corresponding to the difference between the largest and the second largest of the four log-likelihood values in each set. The decoding process repeats for at least a second iteration. The decoding process is stopped based on a plurality of delta values calculated during two consecutive iterations.

Abstract: Two correlation signals which are obtained by computing correlations between two reference signals and a reception signal are inputted to a level-0 cell, the reference signals being generated on the basis of combinations of crosstalk coefficients. A level-1 soft judgment target signal is produced by using soft judgment target signals that are outputted by two sets of level-0 cells respectively and, similarly, a level (N+1) cell is formed by using two sets of level-N cells, whereby a soft judgment target signal creation portion with a hierarchical structure is constituted. A judgment unit outputs a soft judgment value of the target subchannel on the basis of the soft judgment target signal that is outputted by the level (N+1) cell, and judges a reception signal.

Abstract: A method and structure of processing soft information in a block code decoder, includes a soft-input soft-output decoder receiving a length n soft input vector, creating a binary vector Y corresponding to the soft input vector, hard decoding each linear function Xi of Y and a test pattern Zi of one or more test patterns, wherein if the hard decoding is successful a codeword produced by the hard decoding of Xi is added to a set S, removing redundant codewords in S to form a reduced set S? based on processing a number of errors found during the hard decoding and a guaranteed error correcting capability of the block code decode, and an extrinsic value estimator generating n soft outputs based on c estimated soft output values and (n-c) non-estimated soft output values wherein the c estimated soft output values are computed from one or more positions of soft input vector and one or more codewords in S?.

Abstract: A communication channel including Reed-Solomon (RS) and single-parity-check (SPC) encoding/decoding. Multiple RS codewords are combined and then SPC encoded into an RS/SPC array. A soft-input soft-output (SISO) channel detector detects the RS/SPC encoded bits and provides soft (reliability) information on these bits. A combined RS and SPC error correction block provides a recovered user output. An iterative soft input decoding algorithm combines RS and SPC error correction.

Abstract: Digital circuits and methods for designing digital circuits are presented. More particularly, the present invention relates to error correction circuits and methods in communications and other systems. In the present invention, a novel K-nested layered look-ahead method and its corresponding architecture, which combine K-trellis steps into one trellis step (where K is the encoder constraint length), are proposed for implementing low-latency high-throughput rate Viterbi decoder circuits. The main idea of the present invention involves combining K-trellis steps as a pipeline structure and then combining the resulting look-ahead branch metrics as a tree structure in a layered manner to decrease the ACS precomputation latency of look-ahead Viterbi decoder circuits. The proposed method guarantees parallel paths between any two trellis states in the look-ahead trellises and distributes the add-compare-select (ACS) computations to all trellis layers.