Abstract: A maximum likelihood sequence estimator (MLSE) sub-receiver is disclosed, in one embodiment of the present invention and includes an MLSE equalizer device responsive to input data to generate equalized data. The input data is generated from transmitted data by wireless transmission. The MLSE equalizer device processes the input data to generate residual channel response using a known codebook and the residual channel response to generate an MLSE codebook. The MLSE sub-receiver further includes an MLSE decoder responsive to the equalized data and the MLSE codebook for processing to determine maximum likelihood between the equalized data and the MLSE codebook. The MLSE decoder uses the maximum likelihood for decoding the equalized data to generate a decoded transmitted data by mitigating the effects of multi-path communication channel due to wireless transmission of the transmitted data.

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: Several embodiments of a space diversity trellis interleaver system are provided for communicating data over a plurality of separate communication paths in order to inhibit distortion caused by impulse noise or other correlated noise and enhance the data transmission rate of data communications. The transmitter is designed to receive a plurality of data streams from data terminal equipment (DTE), which can be one or more devices. One or more convolutional encoders, preferably trellis encoders, encode each of the data streams. In an alternative embodiment, more than one trellis encoder is used to trellis encode each data stream. Data segments from the convolutionally encoded data streams are interleaved with a switch. The plurality of interleaved convolutionally-encoded data streams are modulated and transmitted onto a respective plurality of separate communication paths. At the receiver, the plurality of data streams is received from the separate communication paths and demodulated.

Abstract: An equalizer comprises: an FIR; a trellis decoder coupled to the FIR; a mapper coupled to the trellis decoder; and a decision feedback equalizer coupled to the mapper. The decision feedback equalizer receives the mapped and scaled output of the trellis decoder as input and an error signal is generated by subtracting an output of the decision feedback equalizer from the input to the trellis decoder.

Abstract: In digital communications, a multi-mode block-coded modulation/demodulation method carries out adaptive one-way transmission of a multi-mode digital signal by using, between at least two different modes, different settings for level number, level code, set-partitioning method and modulation method that are component elements of a multi-level block-coded modulation system.

Abstract: Parallel concatenated turbo trellis encoder structure. A dual path turbo trellis coded modulation encoder employs two interleavers and two constituent encoders and is also operable to encode symbols whose code rate may vary on a symbol by symbol basis. In addition, each of the interleavers of the parallel concatenated turbo trellis encoder structure may perform modified interleaving where input bits are treated differently depending on the order in which they are received. This interleaving may be differentiated on a bit level. In some embodiments, the implementation of the parallel concatenated turbo trellis encoder structure ensures that the output order of encoded symbols is the same as the order in which the input is received. This input may itself be in the form of bits and/or symbols. Alternatively, the parallel concatenated turbo trellis encoder structure may also support a scrambled ordering of the encoded output with respect to the input.

Abstract: A P-tap parallel decision-feedback decoder (PDFD) is also disclosed. The PDFD includes a plurality of state shift registers. For each state of a code utilized by an incoming data stream, a survivor metric for a state is shifted into the first shift register for the state. Each first shift register has M cells. A decision device is coupled to the first shift registers for outputting a first survivor metric according to survivor metrics in the first shift registers. A second shift register has N delay cells, and the first survivor metric is shifted into the second shift register.

Abstract: Systems and modules for use in trellis-based decoding of encoded sets of data bits. A memory system has multiple arrays for storing an index for each one of multiple states. With each array element being associated with a state through which a decoding path may pass through, the contents of each array element is an index which points to an immediately preceding state. This immediately preceding state is represented by another array element in another array. Each array is populated with array element entries as encoded data set are received by a separate decoder which generates the indices. For every given number of arrays in a group, a trace-back process traces back the path followed by an encoding procedure for encoding the encoded set. By tracing back this path through the various arrays, the original unencoded set of data bits can be found.

Abstract: A decoding method of a product code calculates a kth soft output value of each of r C1 codewords [Ct] (t=1, 2, . . . , r) detected at a codeword generating step. Beginning from t=1, if a kth value of a C1 codeword [Ct] is zero, a first variable, with a predetermined initial value, is compared with the likelihood of the codeword. The first variable is substituted with the sum of a greater one of the first variable and the likelihood and a correction value of the difference between them. If the kth value is nonzero, then the second variable is updated in the same manner. The update of the first and second variables is carried out with incrementing t from one to r, and the kth soft output value is calculated from the difference between the first and second variables updated.

Abstract: A decoder system for concatenated codes such as turbo codes, comprises at least two component decoders mutually coupled through a reliability value handler for handling reliability values. The reliability value handler comprises a scaling unit for providing non linearly scaled reliability values. This reduces the reliability values provided by the component decoders, such that the non linearly scaled reliability values better reflect the genuine reliability information or Log Likelihood Ratio (LLR) in a practical realization of the decoder system generally having sub optimal component decoders.

Abstract: An information recording and reproduction apparatus has a turbo decoder that decodes turbo encoded data. The turbo decoder has a number of likelihood ratio calculation units, forward direction path probability calculation units the number of which is less than the number of the likelihood ratio calculation units, and backward direction path probability calculation units the number of which is less than the number of the likelihood ratio calculation units. The likelihood ratio calculation units calculate in parallel the likelihood ratio for each of a plurality of data blocks. The forward direction path probability calculation units time-divisionally calculate probabilities of the forward direction paths for the data blocks. The backward direction path probability calculation units time-divisionally calculate probabilities of the backward direction paths for the data blocks.

Abstract: An apparatus and method for efficiently distributing energy to a packet data channel. A turbo encoder generates a sequence of systematic symbols and a sequence of parity symbols by encoding an information bit stream. An interleaver interleaves the systematic symbol sequence and the parity symbol sequence, separately and serially concatenates the interleaved systematic symbol sequence and the interleaved parity symbol sequence. An energy distributor rearranges the concatenated symbols so that the systematic symbols are disposed in a high energy-having portion of a predetermined transmission period when transmission energy varies for the transmission period. A modulator modulates the rearranged symbols.

Abstract: Disclosed is an implementation method for simplifying a complicated message-passing function in a decoder for decoding block codes encoded with low-density parity-check (LDPC) codes and only using a summator and a shifter to simplify the hardware structure of the decoder, in which method the input interval of the message-passing function for binary representation of a message input is divided and the respective divided intervals are linearized to allow the calculation of the output of the message-passing function without using a memory. Based on the fact that the message-passing function is similar in structure to an exponential function, the linearized intervals are set to make the maximum value expressible in each digit of the binary representation as the boundary of the intervals.

Abstract: A PRML system with a branch estimator. The PRML system includes an analog-to-digital converter (ADC) for receiving an analog input signal and converting the analog input signal into a digital sampled signal according a sampling clock; a branch estimator for receiving the digital sampled signal and estimating each branch eigenvalue; and a Viterbi decoder for decoding an output signal according to the digital sampled signal and the branch eigenvalues. Since the PRML system employs the branch estimator to estimate the branch eigenvalues of trellis of the Viterbi decoder directly, the PRML system can be simplified and the execution speed of the PRML system can be increased.

Abstract: An apparatus for correcting offset includes an optical pickup converting data recorded on an optical disc to an electrical signal; an AD converter quantizing a reproduction signal for each clock in synchronization with a bit period of the reproduction signal and sequentially outputting the signal as a quantized data column for each clock; an adder adding an offset adjustment amount to the quantized data column serving as an input signal; a Viterbi decoder performing Viterbi decoding on the signal after offset adjustment for binarization; and an offset correction value operating unit calculating the offset adjustment amount so that a value obtained by dividing a standard deviation of path metric difference between a survivor path and another path merged into the survivor path in the Viterbi decoder by an average of the path metric difference is minimized.

Abstract: A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between god and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss.

Abstract: An apparatus for providing data dependent detection in a data read channel is disclosed. Parameters in a read channel are dynamically adjusted according to data dependent noise. For example, a comparison in an add-compare-select (ACS) unit of a Viterbi decoder may be adjusted or offset terms in error event filters may be biased to choose a Viterbi sequence with more transitions or to compensate for polarity dependent noise.

Abstract: In playback of data recorded on an optical disk, an error minimization circuit holds a plurality of ideal values for partial response (PR) equalization as equalization targets, and updates tap coefficients of a finite impulse response (FIR) filter so that the errors between the outputs of the FIR filter reflecting the output of an analog-to-digital converter (ADC) and the equalization targets are minimized. An error detection circuit and an addition/weighting circuit generate a signal representing the errors between the outputs of the FIR filter and the equalization targets as a parameter signal correlated with the error rate of played-back data. The quality of the analog signal is adjusted so that the parameter signal is minimized, to thereby optimize the margin of the error rate of played-back data.

Abstract: A decoder for decoding data from a communication channel includes a parity check matrix including M tiers, wherein M?B, Dmin=B*M for M=1 . . . E or B*M?Dmin?F for M>E. Dmin is the minimum Hamming distance and tc=M, wherein tc is a column weight. The parity check matrix includes no period-four cycles. B, Dmin, E, F and M are integers. A soft channel decoder is configured to decode data. A soft linear block code decoder is configured to decode data decoded by the soft channel decoder in accordance with the parity check matrix.

Abstract: A method and apparatus for performing H-ARQ transmission is described herein. Bits received on a first transmission are stored and combined with the bits received on later transmissions thereby increasing the likelihood of a correct decoding on later transmissions. Additionally, a plurality of coding schemes (e.g., Convolutional Codes, Block Turbo Codes, Convolutional Turbo Codes, Low Density Party Check Codes, . . . , etc.) are utilized, with an information element being reserved to signal what form of H-ARQ is being utilized.

Abstract: An iterative method and a device for decoding received signals transmitted in data frames via various channels. In order to be able to utilize the computing capacity of digital signal processors (DSPs) as efficiently as possible, it is proposed that, starting at a first channel, the quality of the decoded signal transmitted via the first channel is checked following every iteration and switchover takes place to at least one further channel if a specifiable switchover condition exists. The switchover condition may, for example, be a specifiable quality of the decoded signal transmitted via the channel under consideration. To determine the quality of the decoded signal a cyclic redundancy check (CRC), in particular, is proposed following every iteration.

Abstract: The invention relates to an error correcting decoder apparatus (100) and method. The decoder apparatus (100) comprises a likelihood estimator (101) which generates a sequence of bit value likelihood estimates, such as log likelihood ratios, for multi bit symbols of a data sequence. The decoder apparatus (100) further comprises a decoder element (103), such as a Maximum A Priori (MAP) or appropriate Soft Output Viterbi decoder. The decoder element (103) generates a decoded data sequence in response to the bit value likelihood estimates. The decoder apparatus (100) also comprises a weighted processor (105) which generates a weighted compensation data sequence from the decoded data sequence. The weighted compensation data is used to modify the sequence of bit value likelihood estimates. The decoding is subsequently repeated using the improved bit value likelihood estimates whereby improved decoding performance is achieved.

Abstract: A signal detector to detect data in an input signal. The signal detector includes a finite impulse response (FIR) filter to equalize the data to a first target length. A Viterbi-like detector is matched to a primary target and generates a most likely path corresponding to the data in the input signal. A linear post-processor determines at least one most likely error event in the most likely path and generates revised paths based on the at least one most likely error event. A media noise processor operates on the data with a secondary target that is different than the primary target. The media noise processor computes path metrics corresponding to each of the revised paths as a function of a non-linear noise model and selects one of the revised paths based on the path metrics.

Abstract: A method for detecting data symbols corrupted by intersymbol interference and timing error, comprises calculating a first plurality of state probabilities for received symbols using a forward recursive process on a joint intersymbol interference/timing error (ISI/TE) trellis, calculating a second plurality of state probabilities for the received symbols using a backward recursive process on the joint ISI/TE trellis, and using the first plurality of state probabilities and the second plurality of state probabilities to calculate a posteriori state transition probabilities for the received symbols. An apparatus that performs the method is also disclosed.

Abstract: Efficient LDPC code decoding with new minus operator in a finite precision radix system. A new mathematical operator is introduced and applied to the decoding of LDPC coded signals. This new operator is referred to as the min†? (min-dagger minus) operator herein. This min†? processing is appropriately applied during the updating of the edge messages with respect to the variable nodes. In a bit level decoding approach to decoding LDPC coded signals, the updating of the edge messages with respect to the bit nodes is performed using the new min†? operator. This approach provides very comparable performance to min** processing as also applied to updating of the edge messages with respect to the bit nodes and may also provide for a significant savings in hardware. Also, within finite precision radix systems, the new min†? operator provides a means by which always meaningful results may be achieved during the decoding processing.

Abstract: A turbo coded communication system includes a gray scale mapper in a transmitter for generating a symbol constellation of modulated signals points that can be separated by boundary lines in the constellation space into bitwise groups of zero bits and one bits where the shortest distance from a boundary line to received value in the constellation space indicates the bitwise soft metrics that is computed using a set of bitwise soft metric equations are a function of a minimum angle using closed form algebraic equations in turbo decoding receiver. In the case of phase shift keying (PSK) modulation, the bit boundary lines are predetermined by a minimum angle in the constellation space for a specified M-ary modulation, so that, the soft metric equations are only a function of the received signal value for providing efficient computation of the bitwise soft metric.

Abstract: A turbo coded communication system includes a gray scale mapper in a transmitter for generating a symbol constellation of modulated signals points that can be separated by boundary lines in the constellation space into bitwise groups of zero bits and one bits where the shortest distance from a boundary line to received value in the constellation space indicates the bitwise soft metrics that is computed using a set of bitwise soft metric equations are a function of the minimum distance using closed form algebraic equations in turbo decoding receiver. In the case of quadrature amplitude modulation (QAM), the bit boundary lines are predetermined by a minimum distance in the constellation space for a specified M-ary modulation, so that, the soft metric equations are only a function of the received signal value for providing efficient computation of the bitwise soft metric.

Abstract: An add-compare-select (ACS) arithmetic unit for a Viterbi decoder is provided.

Abstract: A method for improving gain performance of a Viterbi decoder wherein data relating to the best path and a secondary path are stored for the Viterbi decoder. Slicer errors are determined for the best path and the secondary path for current symbols using the stored data and errors for previous symbols are corrected responsive to the determined slicer errors.

Abstract: In one aspect the invention is a method for sequence estimating. The method includes receiving convolutional codes. The method further includes using a lazy Viterbi decoder to decode the convolutional codes. The convolutional codes may be stream convolutional codes. The convolutional codes may also be block convolutional codes. The lazy Viterbi decoder may be used in a software radio environment.

Abstract: Single stage implementation of min*, max*, min and/or max to perform state metric calculation in soft-in soft-out (SISO) decoder. This allows for calculation of state metrics in an extremely efficient, fast manner. When performing min or max calculations, comparisons are made using 2 element combinations of the available inputs. Subsequently, logic circuitry employs the results of the 2 element comparisons the smallest (min) or largest (max) input. The max or min implementations may be employed as part of the max* and/or min* implementations. For max* and/or min* implementations, simultaneous calculation of appropriate values is performed while determining which input is the smallest or largest. Thereafter, the determination of which input is the smallest or largest is used to select the appropriate resultant value (of the values calculated) for max* and/or min*. Various degrees of precision are employed for the log correction values within the max* and/or min* implementations.

Abstract: A forward error correction method for decoding coded bits generated by low density parity check matrixes. The method comprises converting each of the coded bits into a log likelihood ratio (LLR) value, and applying the converted values to variable nodes; delivering messages applied to the variable nodes to check nodes; checking a message having a minimum value among the messages, and determining a sign of the message having the minimum value; receiving messages updated in the check nodes, adding up signs of the received messages and a sign of an initial message, applying a weighting factor of 1 when all signs are identical, and when all signs are not identical, updating a message of a variable node by applying a weighting factor; determining LLR of an initial input value; and hard-deciding values of the variable nodes, performing parity check on the hard decision values, and stopping the decoding when no error occurs.

Abstract: Provides a normalizing apparatus that normalizes input signals to a turbo decoder without significantly increasing a size of a circuit. An input signal buffer (341) obtains a sum S for N pieces of input signal data I(i). An input data averaging part (342) obtains an average A by dividing the sum S by the number of data N. A divider (343) obtains normalized data I(i)/A by dividing the input signals I(i) by the average A. A weighting part (345) multiplies the normalized data I(i)/A with a weighting coefficient ?, which is determined based on a ratio of a number of input data and a number of output data in rate matching. As a result, the normalization is made possible. Because a signal receiving quality does not need to be determined, an increase in circuit size is inhibited.

Abstract: An apparatus and method for executing a Viterbi algorithm includes initial state registers, at least one transition register, and an adder/subtracter network. Furthermore, evaluation units and a selection unit are provided for switching the apparatus between a first operating mode and a second operating mode. The selection unit can select different evaluation units depending on the selected operating mode.

Abstract: The present invention relates generally to error-correction coding and, more particularly, to a decoder for concatenated codes, e.g., turbo codes. The present invention provides a decoder for decoding encoded data, the decoder comprising: a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculates probability estimates for said symbols in a next iterative state; normalising means which normalises said next states estimates; a switch that receives both said normalised and said unnormalised next state estimates, the output of the switch being coupled to the input of the processor; wherein the switch is arranged to switch between the normalised and unnormalised next state estimates depending on the iterative state.

Abstract: The present invention discloses an apparatus used to generate a branch metric for a Viterbi decoder. The apparatus includes a linear feedback shift register and a convolutional encoder. The linear feedback shift register performs a calculation based on a specific primitive characteristic polynomial and creates a binary number sequence after the calculation. The convolutional encoder generates the branch metric by encoding the binary number sequence. Besides, the apparatus is further capable of selecting one of the several built-in primitive characteristic polynomials by inputting a selection signal in order to conform to the request of the different systems.

Abstract: Communication decoder employing single trellis to support multiple code rates and/or multiple modulations. A single trellis is employed by the decoder to decode a plurality of encoded symbols. Each of the plurality of encoded symbols is governed by a rate control. A rate control sequence, having a period, is used to decode the plurality of encoded symbols that may be arranged within a frame. Various parameters of the plurality of encoded symbols may vary on a symbol by symbol basis; these parameters may include modulation, constellation, mapping, and/or bandwidth efficiency. For example, various symbols may be encoded differently, yet they may all be decoded using the same trellis. The functionality of this decoder may be implemented within a variety of different decoder embodiments including a trellis code modulation (TCM) decoder, a turbo trellis code modulation (TTCM) decoder, and/or a parallel concatenated turbo code modulation (PC-TCM) decoder.

Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Abstract: A Viterbi decoder identifies errors in an early decision output and includes an early decision generator that generates the early decision output. A full decision generator generates a full decision output. An error detector detects errors in the early decision output and generates a disable signal. A secondary early decision generator generates a secondary early decision output. The error detector includes a comparing circuit that disables a prior early decision output if the secondary early decision output is different than the prior early decision output. Alternately, a best path flag generator generates a best path flag when the Viterbi decoder identifies two best paths having the same path metric. A comparing circuit disables the early decision output if a prior secondary early decision output is different than the early decision output, the best path flag is true and a prior best path flag is true.

Abstract: TTCM (Turbo Trellis Coded Modulation) decoder design. The design also adapts to any number of devices that perform decoding of Trellis Code Modulation (TCM) signals. After performing initial symbol processing within a data block to generate a number of check point values, the design selectively re-calculates some forward metrics (alphas) and backward metrics (betas), and the design is able to calculate extrinsic (ext) information for each symbol within the data block successively. The data block is subdivided into a number of sub-blocks that are intelligently processed to enable extremely fast processing. Generally speaking, the design performs initial processing starting from both block ends, and upon approaching the block middle, the design begins to process the block using skip backs to previous sub-blocks. The design employs a great deal of parallel and simultaneously processing to provide for very fast computation of the various values required to decode the block.

Abstract: A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth m×n matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.

Abstract: A system and method for the resynchronization of a sequential decoder that decodes received signal samples stored within an input buffer is disclosed. The system comprises two auxiliary decoders coupled to the sequential decoder for running a simplified MAP decoding process when the input buffer reaches a threshold saturation level. Control of the respective increments of a read pointer and a write pointer allows one to detect the saturation of the input buffer and to derive a sequence of signal samples to the appropriate auxiliary decoder. The selected auxiliary decoder estimates a resynchronization state for the sequential decoder based on the sequence of signal samples. According to the read and the write pointers value, normal sequential decoding is resumed, otherwise, the second auxiliary decoder is selected. The selected auxiliary decoder estimates a resynchronization state for the sequential decoder based on a new sequence of signal samples.

Abstract: In a digital information processing system wherein a model of a finite state machine (FSM) receiving a plurality of FSM inputs and producing a plurality of FSM outputs is represented by a reduced-state trellis and wherein the FSM inputs are defined on a base closed set of symbols, a novel method is presented for updating soft decision information on the FSM inputs into higher confidence information whereby (1) the soft decision information is inputted in a first index set, (2) a forward recursion is processed on the input soft decision information based on the reduced-state trellis representation to produce forward state metrics, (3) a backward recursion is processed on the input soft decision information based on the reduced-state trellis representation to produce backward state metrics, wherein the backward recursion is independent of the forward recursion and (4) the forward state metrics and the backward state metrics are operated on to produce the higher confidence information.

Abstract: Techniques for performing substantially concurrent add-compare-select-add operations and substantially concurrent compare-select-add operations for use in turbo decoders are provided. In one aspect of the invention, a technique for processing data in accordance with a turbo decoder comprises the following steps. Data values of two sets of input data are respectively added to generate a set of sums. Substantially concurrent with the addition step, correction values are respectively added to the sums to generate a set of corrected sums. Substantially concurrent with the respective input data value and correction value addition steps, the sums are compared against one another, and an absolute value of a difference between the sums is compared against base and bound values. Then, one of the corrected sums is selected based on the comparison steps. Preferably, respective sub-steps within the input value addition step, the correction value addition step, and the comparison step are performed concurrently.

Abstract: An equalizer is used with complex modulation modems to reduce intersymbol interference. The equalizer includes an equalizer filter that receives an input data signal and adapts to compensate for the noisy communications channels to reduce intersymbol interference to the input signal. A branch metric computer demodulates the equalizer filter adapted input data signal. A decision device delivers an alpha value, starting phase information and confidence values from the demodulated input data signal. A gain determination function receives the confidence values and determines adaptation gain for the equalizer filter. A remodulator receives the alpha value and starting phase information and remodulates the alpha value and starting phase information into a remodulated data signal. A summing function compares the remodulated data signal to a delayed version of the input signal to generate an error signal for the equalizer filter to adjust the equalizer filter.

Abstract: A method and device for decoding a sequence of physical signals. A Viterbi algorithm is carried out a first time for all physical signals, resulting in a maximum likelihood path, wherein there is one signal value for each physical signal and which has been determined along the entire trellis according to the Viterbi algorithm. A reliability value is determined for each signal value of the maximum likelihood path.

Abstract: A method for decoding a predetermined code word is specified in which the code word comprises a number of positions having different values. In this method, encoding is performed, in particular, by way of a terminated convolutional code. Each position of the code word is correlated with a safety measure (soft output) for a most probable Boolean value by performing the correlation on the basis of a trellis representation. The decoding of the code word is determined by the correlation of the individual positions of the code word.

Abstract: There is provided a signal evaluation apparatus and signal evaluation method capable of consistently measuring an accurate bit error rate regardless of the distribution profile of the difference of likelihoods (difference metrics) of data sequences. In the signal evaluation apparatus for decoding data sequences by means of maximum likelihood decoding, at least one pair of paths between which a distance has a minimum value are selected by a path selector circuit 10. With regard to the paths selected by the path selector circuit 10, a difference metric obtained by a difference metric calculator circuit 9 is statistically processed by a ?- and ?-calculator circuit 13 to calculate a bit error rate. Then, the bit error rate is corrected by correction means (11, 12, 14) on the basis of the number of measurement samples of the paths selected by the path selector circuit 10 and the number of all samples.

Abstract: A method of transmitting convolutionally encoded data with separate, independent and looped encoding over at least one data portion. The data is distributed over one or more cycles, and a plurality of cycles can be grouped into packets for discontinuous transmission if necessary. Weighted decoding is effected independently and cycle by cycle: it starts at a robust location, with a relatively high likelihood, and terminates at a weak location, with a weak likelihood, ignoring the concept of time. This limits the size of the packets of errors and prevents the propagation of packets of errors due to scrambling. Independent encoding and decoding of data can be effected without exchanging parameters between cycles and the parameters of each cycle (size, redundancy, constraint length) can be separate. Different degrees of protection and time-delay are permitted as a function of the nature of the data to be transmitted (voice, digital data, signaling, etc.).

Abstract: A method (100) for simplifying soft-decision metric decisions in a M-ary modulation system includes determining (102) a single function for a soft-decision metric for each bit in a symbol by restricting the set of all possible Gray-coded constellation points to those closest to a boundary between a bit value of 0 and 1 for each bit in the input symbol and applying a predetermined function corresponding to the range of restricted constellation points to the entire possible range of symbols. A next step includes inputting (104) a symbol having real part, x, and an imaginary part, y. A next step includes (106) setting a soft-decision metric for each bit in the symbol using the predetermined function from the determining step (102).