Abstract: Old user data, old metadata, and old error correction parity information are received. New metadata corresponding to the old user data is generated. The old metadata and the new metadata are combined to obtain combined metadata. New error correction parity information is generated using the combined metadata. The old error correction parity information and new error correction parity information are combined to obtain combined error correction parity information. The old user data, new metadata, and combined error correction parity information are stored in solid state storage.

Abstract: Provided are a method of decoding an LDPC code for producing several different decoders using a parity-check matrix of the LDPC code, and an LDPC code system including the same. The system includes: an LDPC encoder outputting an LDPC codeword through a channel; a first LDPC decoder decoding the LDPC codeword received through the channel, and when the decoding has failed in a second LDPC decoder, decoding the LDPC codeword according to original parity check matrix of the LDPC codeword, using soft information newly generated after the decoding is ended in the second LDPC decoder; and the second LDPC decoder, when the decoding has failed in the first LDPC decoder, receiving the soft information on each bit from the first LDPC, and decoding the LDPC codeword according to a new parity-check matrix produced from the parity-check matrix of the LDPC codeword using the received soft information on each bit.

Abstract: An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.

Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.

Abstract: The invention relates to a method for encoding digital data, in particular of data processed in a microprocessor unit. In the method according to the invention for a respective data word (A, B, C) of a series of data words to be encoded subsequently a parity code (P(A), P(B), P(C)) is computed on the basis of the data of the respective data word (A, B, C). Further the respective data word (A, B, C) is altered with the aid of the data word (A, B, C) preceding it in the series, wherein the altered data word (Aa, Ba, Ca) and the parity code (P(A), P(B), P(C)) represent the encoded data word (Ac, Bc, Cc) and the encoded data word (Ac, Bc, Cc) can be decoded with the aid of the data word (A, B, C) preceding it in the series.

Abstract: A method includes accepting input including at least part of a codeword that has been encoded by an ECC defined by a set of parity check equations. The codeword includes data bits and parity bits. A decoding process is applied to the codeword using the data bits and only a first partial subset of parity bits in the input, and using only a second partial subset of equations. Upon a failure to decode the codeword using the partial subsets, the codeword is re-decoded using the data bits and all parity bits in the input, and using all equations. The set of parity check equations is defined such that any parity bit in the codeword appears in multiple equations, and any parity bit in the first partial subset of the parity bits appears in a plurality of equations in the second partial subset of the equations.

Abstract: An apparatus and method for transmitting and receiving data in a wireless communication is provided. The method includes determining a number of zero-padding bits, determining a number (Npad) of bit groups in which all bits are padded with zeros, padding the all bits within 0th to (Npad?1)th bit groups indicated by a shortening pattern with zeros, mapping information bits to bit positions which are not padded in Bose Chaudhuri Hocquenghem (BCH) information bits, BCH encoding the BCH information bits to generate Low Density Parity Check (LDPC) information bits, and LDPC encoding the LDPC information bits to generate a zero-padded codeword, wherein the shortening pattern is defined as an order of bit groups defined as 6, 5, 4, 9, 3, 2, 1, 8, 0, 7, 10 and 11.

Abstract: An apparatus for recognizing a failure in a cryptographic unit, wherein the cryptographic unit includes a determinator for determining an input control signal and an output control signal, with the determinator being formed to determine the input control signal on the basis of an encryption of an input control signal parity of a group of input signals or an input signal of the group of input signals with an encryption number and to determine the output control signal on the basis of an encryption of an output control signal parity of a group of the output signals or an output signal of the group of output signals with the encryption number. Furthermore, the apparatus for recognizing includes an evaluator for evaluating the input control signal and the output control signal to recognize a failure of the cryptographic unit on the basis of a comparison between the input control signal and the output control signal.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.

Abstract: An apparatus includes a circuit configured to at least one of (i) encode first data to produce encoded data or (ii) decode second data to produce decoded data. The circuit is configured to operate according to a predetermined matrix. Each element of the predetermined matrix labeled with a hyphen corresponds to a zero matrix. Each element of the predetermined matrix labeled with a number corresponds to a respective cyclic-permutation matrix.

Abstract: A plurality of columns for a check matrix that implements a distance d linear error correcting code are populated by providing a set of vectors from which to populate the columns, and applying to the set of vectors a filter operation that reduces the set by eliminating therefrom all vectors that would, if used to populate the columns, prevent the check matrix from satisfying a column-wise linear independence requirement associated with check matrices of distance d linear codes. One of the vectors from the reduced set may then be selected to populate one of the columns. The filtering and selecting repeats iteratively until either all of the columns are populated or the number of currently unpopulated columns exceeds the number of vectors in the reduced set. Columns for the check matrix may be processed to reduce the amount of logic needed to implement the check matrix in circuit logic.

Abstract: Apparatuses and methods associated with instant syndrome computation in a layered LDPC decoder are described. According to one embodiment, an apparatus includes a plurality of hardware layers, where a hardware layer is configured to compute a syndrome value from one or more bit values in the codeword. The apparatus includes a plurality of physical memories configured to store a plurality of syndrome values, where a physical memory is configured to store syndrome values computed by one or more hardware layers. The apparatus includes circuitry configured to simultaneously store a syndrome value computed by a hardware layer in physical memories associated with a bit in the codeword. The apparatus includes a decode logic configured to signal successful decoding of the codeword based, at least in part, on determining that a set of syndromes are satisfied based on values stored in the plurality of physical memories.

Abstract: A co-hosted cyclical redundancy check (CRC) calculations system is arranged to use a processor to generate initial addresses for reading the data from a mirrored device that has address ranges over which a CRC result is to be calculated. An memory mapping unit detects when the initial address falls within an address range over which the CRC result is to be calculated. A read snoop unit snoops the data read from a mirrored memory that has data stored using a mirrored address. A CRC co-generator receives the snooped data read from mirrored memory and uses the snooped data read from the mirrored memory to calculate the CRC result.

Abstract: A method and device for determining a size of a transport block based on modulation and coding related information, and resource information.

Abstract: An encoding method changes an encoding rate of an erasure correcting code. One cycle is defined as 12k bits (wherein k represents a natural number) which is an encoding output using LDPC-CC with an encoding rate of ½, and includes information and parity. From the one cycle, only the information is arranged in the output order of the encoding output to obtain 6k bit information X6i, X6i+1, X6i+2, X6i+3, X6i+4, X6i+5, . . . , X6(i+k?1) X6(i+k?1)+1, X6(i+k?1)+2, X6(i+k?1)+3, X6(i+k?1)+4, and X6(i+k?1)+5. Known information is inserted in 3k pieces of information (Xj) among the 6k bit information, so that when 3k pieces of mutually different j is divided by 3, there is a remainder of 0 regarding k pieces, there is a remainder of 1 regarding k pieces, and there is a remainder of 2 regarding k pieces, to thereby obtain the parity from the information containing the known information.

Abstract: A method of de-mapping non-binary Galois field symbols from physical layer code-words in a data communication system, in which at least one physical layer code-word includes portions mapped from more than one non-binary Galois field symbol is provided. The method includes calculating at least a provisional likelihood estimate for values of a first non-binary Galois field symbol having at least portions within a first physical layer code-word, the calculating including selecting a first number of values of a second non-binary Galois field symbol having at least portions within the first physical layer code-word, the first number forming a subset of the possible values of the second non-binary Galois field symbol.

Abstract: According to one embodiment, a wireless communications device includes a low-density parity check (LDPC) decoder configured to receive a codeword associated with a parity check H-matrix. The LDPC decoder includes multiple processing elements coupled to a memory for storing the parity check H-matrix comprising R rows and C columns. Each processing element is configured to perform LDPC decoding on different rows of the H-matrix during multiple sub-iterations. A first portion of the processing elements are configured to process certain rows in an upward direction in the H-matrix relative to other rows and a second portion of the processing elements are configured to process other certain rows in a downward direction in the H-matrix relative to the other rows.

Abstract: Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.

Abstract: A system and method for processing a block Low Density Parity Check (LDPC) code are provided. The system includes, a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part including a first section (B) including a plurality of first permutation matrices, a second section (D) including a second permutation matrix, a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, and a fourth section (E) including a fourth permutation matrix.

Abstract: A transmission system carrying out sending and receiving of OTU frames has a first transmission device carrying out the sending of an OTU frame, and a second transmission device carrying out the receiving of the OTU frame. The first transmission device calculates BIP-8 for an objective calculation range preset in the OTU frame, inserts the calculation result into the OTU frame, and sends the same. The second transmission device calculates BIP-8 from the received OTU frame for the same objective calculation range as the first transmission device, compares the calculation result with the BIP-8 sent from the first transmission device, and detects any presence of transmission error. The calculation range is set in terms of one of an area including OPU only and an area at least including an arbitrary byte of OTU/ODU overhead.

Abstract: An apparatus and method for producing error correction code and error correction decoding are provided. The method for producing error correction code includes generating an asymmetric matrix by arranging input data bits in a matrix of a predefined size and adding a zero bit column and/or a zero bit row, each of the column and the row consisting of zero bits, to the matrix; primarily encoding the asymmetric matrix by adding one or more parity bits to each row; and secondarily encoding the primarily encoded matrix by adding one or more parity bits to each column of the encoded matrix.

Abstract: This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.

Abstract: In one embodiment a variable barrel shifter includes a shifter operable to apply a cyclic shift to each of a number of portions of a data word, a pivot circuit operable to swap sections of the data word around at least one pivot point in the data word, a first multiplexer operable to select between an input of the variable barrel shifter or an output of the pivot circuit as an input to the shifter, a second multiplexer operable to select between the input of the variable barrel shifter or an output of the shifter as an input to the pivot circuit, and a third multiplexer operable to select between the output of the shifter or the output of the pivot circuit as an output to the variable barrel shifter.

Abstract: The invention relates to a method of encoding user data into codevectors and to a corresponding method of decoding codevectors into user data.

Abstract: A multiple access scheme is described. One or more encoders are configured to encode a plurality of bit streams using Low Density Parity Check (LDPC) coding. The bit streams correspond to a respective plurality of terminals. The plurality of bit streams are converted to provide a multiple access scheme for the terminals.

Abstract: Each of (n?1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n?1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.

Abstract: A method implemented in a digital subscriber line (DSL) system is described for minimizing a misdetection probability at a far-end coded message receiver during transmission of a coded message. The method comprises jointly determining, at the far-end coded message receiver, a P matrix and a modulation scheme. The method further comprises encoding a message into a coded message with a systematic linear block code, the systematic linear block code having a generator matrix [I P], where I represents a linear block code component identity matrix and P represents the determined P matrix. The method also comprises modulating the encoded message to one or more tones forming a discrete multi-tone (DMT) symbol according to the determined modulation scheme.

Abstract: A transmitter device (110T) for secure communication includes: an encoder (170) configured to apply a non-systematic error correcting code (NS ECC) to a message, thus producing encoded bits with no clear message bits; and a transceiver (720) configured to transmit the encoded bits over a main channel to a receiver. A method for secure communication includes: encoding a message with an NS ECC to produce an encoded message carrying no message bits in the clear; and transmitting the encoded message over a main channel (120). The NS ECC characteristics result in an eavesdropper channel error probability under a security threshold (320) and a main channel error probability over a reliability threshold (310), whenever an eavesdropper (140) listening on an eavesdropper channel (150) is more than distance Z (220) from the transmitter. Unreliable bits in the encoded bits render the eavesdropper unable to reliably decode messages on the main channel.

Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Abstract: A system (e.g., Fiber Channel Error Detecting Code (FC-EDC)) that maps the “standard” Hamming codes onto the bits of a 33-bit control block is provided. The system employs a “rotation” of the check positions in a two-dimensional parity-check matrix for the FC-EDC. The specification discloses a computer-implemented program to test further modifications and permutations of the “standard” distance-4 parity-check matrix to yield an FC-EDC with enhanced error-detecting properties, designed to detect the most likely errors in the known physical environment. By using a parity-check matrix with the “rotation” property, certain error-detecting properties of the parity-check matrix are ensured, and the computation time for searching for a matrix with enhanced error-detecting properties becomes much shorter.

Abstract: Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes.

Abstract: A method includes a first encoding operation associated with a first algebraic error correcting code generating a first set of first parity bits corresponding to a first set of information bits and a second set of first parity bits corresponding to a second set of information bits. A second encoding operation associated with a second algebraic error correcting code generates a first set of second parity bits corresponding to the first set of information bits and a second set of second parity bits corresponding to the second set of information bits. A third encoding operation generates a set of joint parity bits. The first set of information bits, the second set of information bits, the first set of first parity bits, the second set of first parity bits, and the joint parity bits may be stored in a data storage device as a single codeword.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: A method and apparatus are disclosed that include encoding an information word to generate a codeword using a systematic low density parity check matrix using an encoder, the low density parity check matrix comprising a first sub-matrix associated with information symbols, a second sub-matrix having a block triangular structure associated with a first subset of parity check symbols and a third sub-matrix that is invertible and associated with a second subset of parity check symbols, the encoding performed over the second sub-matrix before the third sub-matrix.

Abstract: Methods and systems for transmitting and receiving data include reverse concatenated encoding and decoding. Reverse concatenated decoding includes inner decoding the encoded stream with an inner decoder that uses a low-complexity linear-block code to produce an inner-decoder output stream, outer decoding the inner-decoder output stream with an outer decoder that uses a low-density parity-check code to produce an information stream, and iterating extrinsic bit reliabilities from the outer decoding for use in subsequent inner decoding to improve decoding performance.

Abstract: Methods and systems for reduced-complexity decoding of low-density parity-check (LDPC) information. An encoded input stream is received. The received stream is decoded with one or more reduced-complexity min-sum or a posteriori probability LDPC decoders. A v-node update rule in the reduced complexity decoder is omitted.

Abstract: One embodiment of the present invention relates to an error tolerant memory circuit having a low hardware overhead that can tolerate both single volatile soft errors and permanent errors. In one embodiment, the method and apparatus comprise a memory circuit having a plurality of memory element pairs, respectively having two memory storage elements configured to store a data unit. One or more parity generation circuits are configured to calculate a first parity bit from data written to the plurality of memory element pairs (e.g., the two memory storage elements) and a second parity bit from data read from one of the two memory storage elements in the plurality of memory element pairs. Based upon the calculated first and second parity bits, the memory circuit chooses to selectively output data from memory storage elements not known to contain an error.

Abstract: A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register.

Abstract: Techniques to support low density parity check (LDPC) encoding and decoding are described. An apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to encode or decode a packet based on a base parity check matrix and a set of lifting values. In a particular embodiment, the set of lifting values is limited to lifting values that are each a different power of two. The memory is configured to store parameters associated with the base parity check matrix.

Abstract: In one embodiment, a signal-processing receiver has an upstream processor and a low-density parity-check (LDPC) decoder for decoding LDPC-encoded codewords. The upstream processor generates a soft-output value for each bit of the received codewords. The LDPC decoder is implemented to process the soft-output values without having to wait until all of the soft-output values are generated for the current codeword. Further, the LDPC code used to encode the codewords is arranged to support such processing. By processing the soft-output values without having to wait until all of the soft-output values are generated for the current codeword, receivers of the present invention may have a lower latency and higher throughput than prior-art receivers that wait until all of the soft-output values are generated prior to performing LDPC decoding. In another embodiment, the LDPC decoder processes the soft-output values as soon as, and in the order that, they are generated.

Abstract: A receiver receives an inter-symbol correlated (ISC) signal with information symbols and a corresponding parity symbol. Values of information symbols are estimated utilizing parity samples that are generated from the parity symbols. One or more maximum likelihood (ML) decoding metrics are generated for the information symbols. One or more estimations are generated for the information symbols based on the one or more ML decoding metrics. A parity metric is generated for each of the one or more generated estimations of the information symbols. The parity metric is generated by summing a plurality of values of one of the generated estimations to generate a sum, and wrapping the sum to obtain a parity check value that is within the boundaries of a symbol constellation utilized in generating the information symbols.

Abstract: Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.

Abstract: A method includes applying an error-detecting code to first input data to generate first protected data and applying the error-detecting code to second input data to generate second protected data. The method also includes generating a first encoded codeword by encoding the first protected data using a first low density parity check (LDPC) code, and generating an output by performing a binary exclusive-or operation on the first protected data and the second protected data. The method further includes generating a second encoded codeword by encoding the output of the of the binary exclusive-or operation using a second LDPC code, and multiplexing data for transmission over a communications channel based on (i) the first encoded codeword and (ii) the second encoded codeword.

Abstract: Provided is a rate matching apparatus. The rate matching apparatus includes interleavers, dummy bit removers, a bit collector, a memory and a selector. The interleavers interleave code blocks, respectively. The dummy bit removers remove dummy bits of the interleaved code blocks, respectively. The bit collector collects code blocks with the dummy bits removed by bit units, and divides a collected data bit stream into systematic data and parity data. The memory stores the systematic data and the parity data in parallel. The selector outputs in parallel a plurality of data bits which are selected from the systematic data and parity data of the memory.

Abstract: An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.

Abstract: A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM) includes providing comparand data to the CAM, comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry. In response to asserting the match signal, the method further includes providing output data, an output parity bit, and an output complement parity bit from the RAM, using the comparand data to generate a generated parity bit, and providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit. The error indicator may indicate an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.

Abstract: A data encoding system includes an interleaving module, a generating module, and an insertion module. The interleaving module is configured to receive a data stream. The data stream includes a plurality of data blocks. The interleaving module is configured to, for each data block of a selected subset of the plurality of data blocks, swap positions of a pair of adjacent bits of the data block. The generating module is configured to (i) receive the data stream and (ii) for each of the plurality of data blocks, generate at least one corresponding error checking bit. The insertion module is configured to (i) receive the plurality of data blocks as modified by the interleaving module and (ii) generate an output data stream by inserting the at least one corresponding error checking bit into each one of the plurality of data blocks received from the interleaving module.

Abstract: A parity-check-code decoder is adapted for receiving a channel quality ratio and at least (N) bits that are to be decoded. The parity-check-code decoder treats each of the bits as a bit node, and includes: a verifying circuit that multiplies (N) bit nodes by a matrix to obtain (N-K) check nodes; a reliability-generating circuit that generates a reliability index that serves as an extrinsic check index for each of the bit nodes to transmit to the check nodes; a bit exchange circuit that generates an extrinsic bit index for each of the check nodes to transmit to the bit nodes; a check-exchange circuit that updates a plurality of the extrinsic check indices based on the extrinsic bit indices for the bit nodes to transmit to the check nodes; and a reliability-updating circuit that updates the reliability index of and determines an updated value for each of the bit nodes.

Abstract: An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.

Abstract: In recent years, researchers have found that some XOR erasure codes lead to higher performance and better throughput in fault-tolerant distributed data storage applications. However, little consideration has been given to the advantages of parallel processing or hardware implementations taking advantage of the emergence of multi-core processors. An efficient horizontal MDS-like (Maximum Distance Separable) RAID-6 scheme, called EEO, is provided which significantly improves the performance of the decoding procedure in parallel implementations with little storage overhead. EEO is the fastest and most efficient double disk failure recovering algorithm in RAID-6, at the cost of only two more parity symbols. In practice, it is very useful for application where high decoding throughput is desired.