Abstract: A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.

Abstract: Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column direction and a row direction of data groups to be transmitted through a plurality of data input/output terminals in a read operation and output the error check signals together with the data groups, and a memory controller configured to control data read/write operations of the semiconductor memory apparatus, generate error check signals by performing error check in a column direction and a row direction of data groups to be transmitted in a write operation, and provide the error check signals to the semiconductor memory apparatus together with the data groups.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector.

Abstract: Systems and methods for decoding low density parity check (LDPC) codes are provided. An input message, representing a codeword encoded using a parity check matrix, is processed and data associated with each of the layers of the parity check matrix is computed. A first layer of the parity check matrix includes a first circulant configured to be updated using the data associated with a second layer of the parity check matrix. A second circulant in the first layer of the parity check matrix, configured to be updated using the data associated with the second layer of the parity check matrix, is identified. The first and second circulants are updated using the data associated with the first and second layers of the parity check matrix.

Abstract: Low density parity check (LDPC) decoders are described utilizing a sequential schedule called Zigzag LBP (Z-LBP), for a layered belief propagation (LBP) architecture. Z-LBP has a lower computational complexity per iteration than variable-node-centric LBP (V-LBP), while being simpler than flooding and check-node-centric LBP (C-LBP). For QC-LDPC codes where the sub-matrices can have at most one “1” per column and one “1” per row, Z-LBP can perform partially-parallel decoding with the same performance as C-LBP. The decoder comprises a control circuit and memory coupled to a parity check matrix. Message passage is performed within Z-LBP in a first direction on odd iterations, and in a second direction on even iterations. As a result, a smaller parity check matrix can be utilized, while convergence can be more readily attained. The inventive method and apparatus can also be implemented for partially-parallel architectures.

Abstract: According to an aspect of an embodiment, a method of storing user data (UD) with parity data (PD) for correcting the UD in a storage apparatus comprising disk units, each of the disk units storing data in data blocks(DBs), each of the DBs storing the UD or associated PD and position information(PI) indicative of the location of the DBs, comprising: obtaining the UD, dividing the UD into UD blocks (UDBs) which are adapted to be stored in the DBs, and determining which UDBs are to be stored into which DBs, respectively; determining PI of the DBs for storing the UDBs; generating PD for a group of UDBs and associated PI by parity operation using a weighting function to the UDBs and the PI; determining PI for the PD for said group by modifying a part of the PD; and storing the group of the UDBs, associated PI, and the PD.

Abstract: Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput.

Abstract: A communications device including a low-density parity check (LDPC) encoder and a transmitter. The LDPC encoder is configured to (i) receive data, and (ii) in response to the received data, generate encoded data using a predetermined LDPC matrix, in which the predetermined LDPC matrix is specified by a predetermined base matrix. The transmitter is configured to transmit the encoded data over a communications channel.

Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.

Abstract: Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode a low density parity check code; and a decoding control section configured to control a frequency of the decoding on the basis of conditional information that is an index indicative of a communication condition that influences power consumption in the decoding section.

Abstract: In a multiple level cell flash memory data storage device, a flash memory array has a plurality of blocks, where each block is an erase unit and has a plurality of pages, and a respective block includes a plurality of groups of pages. Each group of pages in the respective block includes an assigned parity page, and each page of the respective block has a plurality of sectors, including an assigned parity sector. The storage device is operable to program and erase data on a page at a predetermined speed, and detect an error rate for each page of a block and identify a group of high error pages based on the error rates. Further, the storage device is configured to apply a speed slower than the predetermined speed in programming and erasing data on the identified high error pages.

Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.

Abstract: An iterative error correction coding (ECC) decoder is configured to operate in a first higher-power and higher-performance operating mode. At least some part of a system that includes the iterative ECC decoder is monitored. It is determining whether to switch the iterative ECC decoder from the first higher-power and higher-performance operating mode to a second lower-power and lower-performance operating mode based at least in part on the monitoring. The iterative ECC decoder is configured to operate in the second lower-power and lower-performance operating mode in the event it is determined to switch operating modes.

Abstract: This invention concerns packet recovery for real-time (live) multi-media communication over packet-switched networks like the Internet. Such communication includes video, audio, data or any combination thereof. The invention comprises forward error correction (FEC) algorithms addressing both random and burst packet loss and errors, and that can be adjusted to tradeoff the recoverability of missing packets and the latency incurred.

Abstract: Methods and apparatus for performing, using smaller, more efficient shared logic circuitry, the parity checking function and the compare function in a mutually exclusive manner in different cycles of a ternary content addressable memory are disclosed.

Abstract: This disclosure relates generally to data decoding, and more particularly to iterative decoders for data encoded with a low-density parity check (LDPC) encoder. LDPC decoders are disclosed that use reduced-complexity circular shifters that may be used to decode predefined or designed QC-LDPC codes. In addition, methods to design codes which may have particular LDPC code performance capabilities and which may operate with such decoders using reduced-complexity circular shifters are provided. The generation of quasi-cyclic low density parity check codes and the use of circular shifters by LDPC decoders, may be done in such a way as to provide increased computational efficiency, decreased routing congestion, easier timing closure, and improved application performance.

Abstract: A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

Abstract: A memory system is provided. The memory system includes a memory element that is configured to selectively output data stored to and data fetched from the memory element. An error checking station is configured to receive the data stored to and the data fetched from the memory element. The error checking station is further configured to perform error checking on the data.

Abstract: A receiving apparatus receives a low density parity check (“LCPC”) code and decode the LCPC code to provide for error check capabilities. A bit error rate (“BER”) controlling section is the frequency of the LCPC by using an index comprised of BER conditional information that indicates communication conditions affecting the power consumption at the time of decoding. The frequency is controlled on the basis of a reception interval of the low density parity check code.

Abstract: A plurality of information bits are encoded using a parity-check matrix that is equivalent to a modular code matrix. The modular code matrix is a diagonal sub-matrix structure immediately above a connection layer that includes a plurality of diverse connection layer sub-matrices, all but at most one of which are below corresponding diagonal matrix structure sub-matrices. The information bits are assembled with a plurality of parity bits produced by the encoding to provide a codeword that is exported to a medium. Preferably, all the diagonal matrix structure sub-matrices are identical. Preferably, some of the parity bits are computed using only diagonal matrix structure sub-matrices.

Abstract: A serial interface device includes multiple serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values, the serial link connections for the address values and EDC operated separately from one another; and multiple output serial links, at least a first one of the output serial links outputting data values read from memory locations corresponding to the address values, and at least a second one of the output serial links different from and operated separately from the first one outputting EDC values generated for the data values read from the memory locations.

Abstract: A method in a communication system, where a systematic code obtained by systematic encoding of information bits having dummy bits inserted and by deletion of the dummy bits from results of the systematic encoding is transmitted. On a receiving side, the deleted dummy bits are inserted into the received systematic code and then decoded. The method includes: deciding a size of dummy bits for insertion into information bits; segmenting the information bits into a number of code blocks when a bit size of the information bits is greater than a stipulated size; inserting dummy bits into each block of the segmented information bits in conformity with a dummy bit insertion pattern; performing systematic encoding of each block of the information bits into which the dummy bits are inserted, and deleting the dummy bits from the results of the systematic encoding to generate a systematic code.

Abstract: A method of creatine a CRC (Cyclic Redundancy Check) code for a data message in a data communications system includes sequentially placing portions of the data message on a bus of width W bits consisting of an integral number N of segments of width S. An initial portion of the message fills n complete segments, where n<N. The method further includes processing the initial portion of the message placed on the bus to compute a CRC while compensating for any data on the bus preceding the initial portion, and subsequently processing one or more following portions of the message placed on the bus to update the CRC. A final portion of the message is processed to update the CRC by separately processing complete segments that do not fill the bus and any bytes that do not completely fill the last segment.

Abstract: Techniques to support low density parity check (LDPC) encoding and decoding are described. In an aspect, LDPC encoding and decoding of packets of varying sizes may be supported with a set of base parity check matrices of different dimensions and a set of lifting values of different powers of two. A base parity check matrix G of dimension mB×nB may be used to encode a packet of kB=nB?mB information bits to obtain a codeword of nB code bits. This base parity check matrix may be “lifted” by a lifting value of L to obtain a lifted parity check matrix H of dimension L·mB×L·nB. The lifted parity check matrix may be used to encode a packet of up to L·kB information bits to obtain a codeword of L·nB code bits. A wide range of packet sizes may be supported with the set of base parity check matrices and the set of lifting values.

Abstract: Searching for patterns stored on a hardware storage device. A method includes, as part of a memory refresh operation, performing a read to read contents of a portion of a memory. The method further includes writing the read contents of the portion of memory back to the portion of memory. The read contents are provided to data comparison logic. Using the data comparison logic; the read contents are compared to predetermined data patterns. A determination is made as to whether or not the contents match at least one of the predetermined data patterns. When the read contents match at least one of the predetermined data patterns, a software readable indicator is provided indicating that the read contents match at least one of the predetermined data patterns. Similar embodiments may be implemented using hard drive head wear leveling operations.

Abstract: To decode a manifestation of a codeword in which K information bits are encoded as N>K codeword bits, messages are exchanged between N bit nodes and N?K check nodes. During computation, messages are expressed with a full message length greater than two bits. In each iteration, representations of at least some of the exchanged messages are stored. For at least one node, if representations of messages sent from that node are stored, then the representation of one or more of the messages is stored using at least two bits but using fewer bits than the full message length, and the representation of one other message is stored with full message length. Preferably, the messages that are stored using fewer bits than the full message length are messages sent from check nodes.

Abstract: An approach is provided for processing structure Low Density Parity Check (LDPC) codes. Memory storing edge information and a posteriori probability information associated with a structured parity check matrix used to generate Low Density Parity Check (LDPC) coded signal are accessed. The edge information represent relationship between bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge information.

Abstract: A parity-check-code decoder includes: a verifying device that multiplies (N) bit nodes by a matrix provided with (N) columns so as to obtain a plurality of check nodes; a reliability generator that generates a reliability index for each of the bit nodes in accordance with a channel; a reliability-updating device that uses the bit nodes and the check nodes to exchange message iteratively, and following each iteration, updates (N) exchange results corresponding to the (N) columns; and a recording controller that includes a separator, a quantizing determiner and a quantizer. The separator divides the matrix into at least one column group based on the characterizing signals. The quantizing determiner determines a shift signal for each column group based on the characterizing signals. The quantizer quantizes the characterizing signals according to the shift signals for subsequent output.

Abstract: A system and method is capable of performing a Low Density Parity Check (LDPC) coding operation on-the-fly without using a generator matrix. The system and method includes an input configured to receive data and an output configured to output a plurality of codewords. The system and method also includes a processor coupled between the input and the output. The processor is configured to encode the received data and produce the plurality of codewords using a plurality of parity bits. The processor creates the plurality of parity bits on-the-fly using a portion of an LDPC matrix and a protograph matrix.

Abstract: A teletext decoder is provided which is suitable for decoding a packet of teletext signal to generate a teletext. The teletext decoder includes an error judgment device for judging the accuracy of a plurality of sliced bits, and correcting an error occurrence bit in the sliced bits on the basis of a plurality of sampling points and a slicer level when the plurality of sliced bits are incorrect.

Abstract: Some embodiments of the invention shift the responsibility for creating parity and error correction blocks from the hardware or software RAID units or modules to the computer system's file system, allowing the file system's existing mechanisms of write atomicity to be used to help ensure consistency of the on-disk information throughout all or increasing portions of the information saving and/or updating cycle.

Abstract: Certain aspects of the present disclosure relate to a method for generating a single rate or multi-rate highly structured low density parity check, encoding a data stream with the generated LDPC matrix for transmission in a wireless communication system, and for efficient LDPC decoding at a receiver.

Abstract: Intended is to achieve, in a wide range of an SN ratio, throughput on the same order of that attained by a method based on puncturing and improve computational complexity of decoding processing at a high coding rate. In a communication system for transmitting an error correcting code for an error on a communication path from a transmitter to a receiver, the transmitter divides information bits of a code word to be transmitted into a plurality of blocks based on a request for retransmission of an error correcting code from the receiver, generates an error correcting code by compact-coding of one block among the plurality of blocks and transmits the generated error correcting code.

Abstract: Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit.

Abstract: An error correcting method for a memory chip is provided. The memory chip has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, and the physical pages belonging to the same physical block are individually written and simultaneously erased. The error correcting method includes sequentially writing a plurality of data into the physical pages of a first physical block and generating a parity information according to the data. The error correcting method further includes writing the parity information into one of the physical pages of the first physical block following the data and correcting the data in the first physical block according to the parity information. Accordingly, the parity information can be used for correcting error bits in the data when an error checking and correcting circuit can not correct the error bits. Thereby, the error correcting ability is enhanced.

Abstract: A control module includes an encoder module, which generates a first code word for multiple drives. A detector module, in response to detecting an error in a first drive subsequent to generation of the first code word, initiates replacement of the first drive with a second drive. The encoder module generates a second code word for the second drive. A mapping module maps physical locations of data in the drives to logical locations of the first code word, assigns a predetermined value to one of the logical locations corresponding to the first drive to identify an unused logical location, and assigns the unused logical location to the second drive based on the predetermined value. A difference module generates a third code word based on the first and second code words. The encoder module generates an updated code word for the multiple drives based on the first and third code words.

Abstract: In a communication method, a sequence of information bits is encoded into systematic bits and parity bits. The systematic bits and the parity bits are grouped in output blocks, each output block to be assigned to an address of a constellation scheme. The addresses include addresses that are more prone to error and address that are less prone to error so that the symbols are grouped such that bits in groups of consecutive bits of the sequence of information bits are not all assigned to addresses that are more prone to error.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes an error correction code block and a memory. The error correction code block performs error correction encoding for user data to generate parity data. The memory stores the user data and the parity data. The error correction code block generates parity data, including a number of bits equal to at least 2t, wherein t is a natural number, and the bits of the parity data distinguish free page data from user data that is equal to the free page data.

Abstract: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.

Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Abstract: In one embodiment, a matrix-vector multiplication (MVM) component generates a product vector based on (i) an input matrix and (ii) an input vector. The MVM component has a permuter, memory, and an XOR gate array. The permuter permutates, for each input sub-vector of the input vector, the input sub-vector based on a set of permutation coefficients to generate a set of permuted input sub-vectors. The memory stores a set of intermediate product sub-vectors corresponding to the product vector. The XOR gate array performs, for each input sub-vector, exclusive disjunction on (i) the set of permuted input sub-vectors and (ii) the set of intermediate product sub-vectors to update the set of intermediate product subvectors, such that all of the intermediate product sub-vectors in the set are updated based on a current input sub-vector before updating any of the intermediate product sub-vectors in the set based on a subsequent input sub-vector.

Abstract: Provided is a method for generating a single rate or multi-rate highly structured low density parity check, encoding a data stream with the generated LDPC matrix for transmission in a wireless communication system, and for efficient LDPC decoding at a receiver.

Abstract: An encoder structure for an error correcting code with arbitrary parity positions is presented. The invention is effective for all error correcting codes whose parity check matrix is of the Vandermonde type. In contrast to conventional encoder circuits, the parity symbols produced by this encoder are not restricted to form a block of consecutive parity symbols at the beginning or at the end of a codeword, but may be spread arbitrarily within the codeword. A general structure of the parity check matrix for such a code is found by exploiting the special Vandermonde structure of matrices. From this general parity check matrix, an expression for the evaluation of the parity symbols in terms of a polynomial with limited degree is derived. An efficient hardware implementation of the proposed encoder is suggested.

Abstract: A parity check matrix construction method for constructing a non-binary parity check matrix defining a non-binary LDPC code. In particular, a parity check matrix construction method for setting codewords able to stably give a superior decoding performance is provided. For this reason, the non-binary non-zero elements are selected so that the determinants of the partial matrices corresponding to the cycles in the parity check matrix do not become 0. Due to this, a non-binary parity check matrix able to give large weight codewords is constructed.

Abstract: Forward error correction (FEC) scheme for communications. Appropriate selection/arrangement of bits of an information bit sequence undergo one or more types of subsequent encoding to generate a coded bit sequence that may subsequently undergo appropriate processing to generate a continuous time signal to be launched within a communication channel. In some embodiments, an information bit sequence, after being partitioning into a number of information bit groups, initially undergoes a first encoding within a first encoding module thereby generating a number of redundancy/parity bit groups (e.g., e.g., each redundancy/parity bit group corresponding to one of the information bit groups). Then, after performing any desired and appropriate selection/arrangement of bits within the redundancy/parity bit groups and the information bit groups, second encoding within a second encoding module is performed thereon to generate additional redundancy/parity bits.

Abstract: Methods and apparatus for performing parity and/or ECC operations are disclosed. An example method includes determining that an opcode is being transmitted on a bus and determining if the transmitted opcode is a memory operation. In the event the transmitted opcode is a memory write operation, the example method includes calculating a parity bit for data associated with the opcode, writing the calculated parity bit to a parity table and writing the data to a memory. The example method also includes, in the event the transmitted opcode is the memory read operation, recovering data from a previously written memory, calculating a parity bit for the recovered data, recovering a previously stored parity bit for the recovered data, comparing the parity bit for the recovered data with the previously stored parity bit and, in the event the recovered data parity bit does not match the previously stored parity bit, providing an error notification.

Abstract: Verifying data integrity and parity consistency of data blocks in an array of mass storage devices includes retrieving a row parity algebraic signature and a diagonal parity algebraic signature for one or more data blocks, a row parity block and a diagonal parity block. The row parity algebraic signatures of the one or more data blocks are logically combined to generate a first result and the first result is compared to the retrieved row parity algebraic signature for the row parity block. The diagonal parity algebraic signatures of the one or more data blocks and the row parity block are logically combined to generate a second result and the second result is compared to the retrieved diagonal parity algebraic signature for the diagonal parity block.

Abstract: Disclosed are a semiconductor memory device, and a method of driving the same, and a cyclic redundancy check code generating circuit capable of performing cyclic redundancy check. A semiconductor memory device according to an aspect of the present invention includes a memory cell array, a data processing unit receiving data that is read from the memory cell array and selectively outputting at least some of the data according to ordering information, bit structure information, and burst length information, and a check code generating unit generating a cyclic redundancy check code to detect an error in the data being output, the check code generating unit generating and outputting the cyclic redundancy check code by using the read data, the ordering information, the bit structure information, and the burst length information.

Abstract: An encoding system includes a first low density parity check (LDPC) module and a second LDPC module. The first LDPC module is configured to generate a first encoded codeword by encoding a first codeword using a first LDPC code. The second LDPC module is configured to generate a second encoded codeword by encoding a second codeword using a second LDPC code. Signals based on the first encoded codeword and signals based on the second encoded codeword are transmitted over a communications channel. The first LDPC code is defined by a first parity check matrix and the second LDPC code is defined by a second parity check matrix. The second parity check matrix includes the first parity check matrix, a zero matrix, and a supplementary matrix.