Abstract: A system for providing data encoding includes: an encoder configured to encode message data with an encoding parity-check matrix having a parity part that is in lower-triangular form to generate an encoded message data, the encoded message data being for decoded by a decoder; wherein the encoding parity-check matrix is based on a decoding parity-check matrix that does not comprise any degree-1 node in a parity part of the decoding parity-check matrix; and wherein the system further comprises a non-transitory medium for storing the encoding parity-check matrix, wherein the non-transitory medium is a part of the encoder or is communicatively coupled to the encoder.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).

Abstract: A system including a first module, a second module and a third module. The first module is configured to generate a first parity check matrix. The second module is configured to append an appended matrix to the first parity check matrix to generate a resultant parity check matrix. The appended matrix includes additional elements. The third module is configured to receive user data and encode the user data based on the resultant parity check matrix.

Abstract: A low density parity check (LDPC) encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.

Abstract: According to one embodiment, an encoder generates a write data parity from write data to memory elements. A decoder corrects an error of read data from the memory elements using a read data parity for the read data and a check matrix. An inverter maintains or inverts all bits of a received input. Calculation by the decoder using the read data, the read data parity, and the check matrix produces a first result when an error is not included in the read data, a second result when an error is included in the read data, a third result when an error is not included in the read data and all bits of the read data are inverted, and a fourth result when an error is included in the read data and all bits of the read data are not inverted.

Abstract: Embodiments of ECC encoders supporting multiple code rates and throughput speeds for data storage systems are disclosed. In one embodiment, an encoder can provide for flexible and scalable encoding, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) encoding is used. The encoder can be scaled in size based on, for example, the desired encoding throughput and/or computational cycle duration. The encoder can thus be used to support multiple code rates and throughput speeds. Accordingly, encoding speed and efficiency and system performance is improved.

Abstract: Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD Radio signals, including enhanced decoding of reference subcarriers based on soft-diversity combining, joint enhanced channel state information estimation, as well as iterative soft-input soft-output and list decoding of convolutional codes and Reed-Solomon codes. These and other improvements enhance the decoding of different logical channels in HD Radio systems.

Abstract: A network coding method includes receiving a plurality of input packets each having a packet length. Encoding the plurality of input packets by applying a convolutional code across symbols in corresponding positions of the plurality of input packets obtaining a number of encoded packets. The number of encoded packets obtained being more than the number of input packets.

Abstract: A communication device or device includes a processor that generates and interprets signals that are transmitted and received via a communication interface. The processor receives an LDPC coded signal, via the communication interface, that is generated by puncturing at least one parity bit from another LDPC coded signal that is generated based on an LDPC code characterized by a first LDPC matrix. The processor operates on the first LDPC matrix to generate a second LDPC matrix by excluding at least one column and at least one row from the first LDPC matrix. The number of columns and rows excluded from the first LDPC matrix is based on the number of bits punctured from the other LDPC coded signal to generate the LDPC coded signal. The processor then decodes the LDPC coded signal using the second LDPC matrix to make estimates of information bits encoded within the LDPC coded signal.

Abstract: Methods and apparatuses are provided for transmitting and receiving in a communication system. Input information is encoded by using a first parity check matrix to generate a codeword. Additional parity bits are generated by using a second parity check matrix which is related with the first parity check matrix. The codeword is transmitted by using a first resource. The additional parity bits are transmitted by using a second resource which is different from the first resource.

Abstract: This disclosure relates to lossless data reduction on large and extremely large datasets while providing high rates of data ingestion and data retrieval. Some embodiments can generate a losslessly reduced representation of a data chunk, wherein the losslessly reduced representation includes a reference to one or more prime data elements stored in a prime data store, and optionally a description of a reconstitution program which, when applied to the one or more prime data elements results in the data chunk.

Abstract: Provided are a transmitter, a receiver and methods of padding and depadding zero bits to an L1-post signaling. The transmitter includes: a zero padder configured to divide an information word into a plurality of groups, pad zero bits to at least one of the plurality of groups by group unit, and pad additional zero bits to at least one of the plurality of groups remaining after the zero bits are padded, thereby constituting the information word for encoding the L1-post signaling; and an encoder configured to perform encoding on the information word for encoding the L1-post signaling. The zero padder pads the additional zero bits according to a predetermined criterion, starting from a front end or a back end of the at least one of the remaining groups.

Abstract: Methods for digital signal processing and transmission/reception systems utilizing the methods based on the use of LDPC codes, for example the LDPC code with a 3/5 code rate, in combination with a QAM modulation, for example the 16 QAM or 64 QAM or 256 QAM modulation. In transmission, a bit permutation (Demux) is carried out prior to the QAM constellation mapping function, and in reception, the bit permutation is carried out after the QAM constellation demapping function.

Abstract: Methods for digital signal processing and transmission/reception systems utilizing the methods based on the use of LDPC codes, for example the LDPC code with a 3/5 code rate, in combination with a QAM modulation, for example the 16 QAM or 64 QAM or 256 QAM modulation. In transmission, a bit permutation (Demux) is carried out prior to the QAM constellation mapping function, and in reception, the bit permutation is carried out after the QAM constellation demapping function.

Abstract: A communication device is configured to encode and/or decode low density parity check (LDPC) coded signals. Such LDPC coded signals are characterized by LDPC matrices having a particular form. An LDPC matrix may be partitioned into a left hand side matrix and the right hand side matrix. The right hand side matrix can be lower triangular such that all of the sub-matrices therein are all-zero-valued sub-matrices (e.g., all of the elements within an all-zero-valued sub-matrix have the value of “0”) except for those sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to the left of the main diagonal. A device may be configured to employ different LDPC codes having different LDPC matrices for different LDPC coded signals. The different LDPC matrices may be based generally on a common form (e.g., with a right hand side matrix as described above).

Abstract: A communication device is configured to encode and/or decode low density parity check (LDPC) coded signals. Such LDPC coded signals are characterized by LDPC matrices having a particular form. An LDPC matrix may be partitioned into a left hand side matrix and the right hand side matrix. The right hand side matrix can be lower triangular such that all of the sub-matrices therein are all-zero-valued sub-matrices (e.g., all of the elements within an all-zero-valued sub-matrix have the value of “0”) except for those sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to the left of the main diagonal. A device may be configured to employ different LDPC codes having different LDPC matrices for different LDPC coded signals. The different LDPC matrices may be based generally on a common form (e.g., with a right hand side matrix as described above).

Abstract: A storage system includes: a storage device including a recording medium that stores data and a device controller that executes addition processing involving a change of state of the data with respect to the data; and a storage controller that controls input and output of data for the storage device. The storage controller transmits, to the storage device, determination information that can be utilized by the device controller for determining whether or not to execute the addition processing along with input-output processing relating to input-output target data. The device controller controls execution of the addition processing with respect to the input-output target data based on the determination information transmitted from the storage controller.

Abstract: Data processing devices and data process methods that can increase tolerance for data errors. An LDPC encoder performs encoding with an LDPC code having the code length of 16200 bits and one of the six code rates of 1/5, 1/3, 2/5, 4/9, 3/5, and 2/3. The parity check matrix H of the LDPC code is formed by arranging the elements “1” of an information matrix in the column direction in 360-column cycles, the information matrix corresponding to the information length of the parity check matrix H, the information length corresponding to the code length and the code rate, the information matrix being defined by a check matrix initial value table that shows the positions of the elements “1” of the information matrix at intervals of 360 columns. The check matrix initial value table is designed for digital broadcasting intended for portable terminals, for example. The present invention can be applied to cases where LDPC encoding and LDPC decoding are performed.

Abstract: In a transmission device, a determining unit determines, for use in transmission, an LDPC encoding method corresponding to occurrence conditions of external noise from a plurality of LDPC encoding methods each having the same code length and the same code rate and being defined by a different parity check matrix, and an encoding unit generates a codeword bit sequence by encoding transmission data using the LDPC encoding method determined by the determining unit.

Abstract: Apparatuses and methods for determining soft data using a classification code are provided. One example apparatus can include a classification code (CC) decoder and an outer code decoder coupled to the CC decoder. The CC decoder is configured to receive a CC codeword. The CC codeword includes a piece of an outer code codeword and corresponding CC parity digits. The CC decoder is configured to determine soft data associated with the piece of the outer code codeword, at least partially, using the corresponding CC digits.

Abstract: The present disclosure relates to a method for detecting a parity error in a sequence of DQPSK symbols of a digital transmission system, comprising determining a first demodulated symbol r1; determining a second demodulated symbol r2; determining a first parity symbol p1; determining a second parity symbol p2; determining a super-parity symbol q1; and detecting a parity error in the sequence of DQPSK symbols by comparing a combination of the first parity symbol p1 and the second parity symbol p2 against the super-parity symbol q1, wherein a parity between two DQPSK symbols describes a phase difference between the two DQPSK symbols.

Abstract: The present disclosure includes systems and methods for acquiring a first set of information for a plurality of low density parity check (LDPC)-encoded data symbols, acquiring a second set of information for the plurality of LDPC-encoded data symbols, and selecting a window including a subset of the plurality of LDPC-encoded data symbols. The present disclosure includes acquiring a decoder schedule having information for controlling the decoder, wherein the information in the decoder schedule includes decoding instructions based on a configuration of at least one of the first set of information and the second set of information. The present disclosure further includes determining a likelihood of an error in the window using the decoding instructions in the decoder schedule, and updating the second set of information for selected data symbols of the subset based on the likelihood of an error in the window.

Abstract: A data storage device includes a non-volatile memory having a three-dimensional (3D) memory configuration. The data storage device may further include selection circuitry configured to select data for a parity operation in accordance with a parity scheme. The parity scheme may correspond to a string-based and group-based striping pattern.

Abstract: An apparatus includes a circuit configured to at least one of (i) encode first data to produce encoded data or (ii) decode second data to produce decoded data. The circuit is configured to operate according to a predetermined matrix. The predetermined matrix is represented by a two-dimensional grid of elements. Each element of the predetermined matrix labeled with a hyphen corresponds to a zero matrix. Each element of the predetermined matrix labeled with a number corresponds to a respective cyclic-permutation matrix.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: A linear feedback shift register machine capable of generating periodic sequences and having means for detecting single point errors in the generated sequences.

Abstract: A storage system has a RAID group configured by storage media, a system controller with a processor, a buffer memory coupled to storage devices and the processor by a communication network, and a cache memory coupled to the processor and the buffer memory by the network. A processor that stores first data, which is related to a write request from a host computer, in a cache memory, specifies a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device. A first device controller transmits the first data and second data based on the data before update, from the first storage device to the system controller. The processor stores the second data in the buffer memory, specifies a second storage device, and transfers the stored second data to the specified second storage device.

Abstract: A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein the processing order of the layers of the LDPC parity check matrix are rearranged during the decode process in an attempt to avoid error mechanisms brought about by the iterative nature of the LDPC belief propagation decoding process, such as stopping sets and trapping sets.

Abstract: Methods, apparatus, and fabrication processes relating to implementing cyclic redundancy checks (CRCs) in processors, such as CRC32 instructions in x86 computer architectures. A method may comprise extracting a first CRC value from a data packet, performing a carryless operation upon the data packet to determine a second CRC value, and determining that a data error is present in the data packet when the first and second CRC values do not match.

Abstract: A receiver receives an inter-symbol correlated (ISC) signal with information symbols and a corresponding parity symbol. Values of information symbols are estimated utilizing parity samples that are generated from the parity symbols. One or more maximum likelihood (ML) decoding metrics are generated for the information symbols. One or more estimations are generated for the information symbols based on the one or more ML decoding metrics. A parity metric is generated for each of the one or more generated estimations of the information symbols. The parity metric is generated by summing a plurality of values of one of the generated estimations to generate a sum, and wrapping the sum to obtain a parity check value that is within the boundaries of a symbol constellation utilized in generating the information symbols.

Abstract: In the present invention, two improved variants of the reliability-based iterative majority-logic decoding algorithm for regular low-density parity-check (LDPC) codes are presented. The new algorithms are obtained by introducing a different reliability measure for each check-sum of the parity-check matrix, and taking it into account in the computation of the extrinsic information that is used to update the reliability measure of each received bit in each iteration. In contrast to the first algorithm, the second algorithm includes check reliability that changes at each iteration. For the tested random and structured LDPC codes, both algorithms, while requiring very little additional computational complexities, achieve a considerable error performance gain over the standard one.

Abstract: Disclosed are a semiconductor memory device, and a method of driving the same, and a cyclic redundancy check code generating circuit capable of performing cyclic redundancy check. A semiconductor memory device according to an aspect of the present invention includes a memory cell array, a data processing unit receiving data that is read from the memory cell array and selectively outputting at least some of the data according to ordering information, bit structure information, and burst length information, and a check code generating unit generating a cyclic redundancy check code to detect an error in the data being output, the check code generating unit generating and outputting the cyclic redundancy check code by using the read data, the ordering information, the bit structure information, and the burst length information.

Abstract: The present data storage system employs a memory controller with embedded logic to selectively XOR incoming data with data written in the memory to generate XOR parity data. The memory controller automatically performs XOR operations on incoming data based upon the address range associated with the memory “write” request. The system provides data migration and parity generation in a simple and effective manner and attains reduction in cost and power consumption. The memory controller may be built on the basis of FPGAs, thus providing an economical and miniature system.

Abstract: A method includes accepting input including at least part of a codeword that has been encoded by an ECC defined by a set of parity check equations. The codeword includes data bits and parity bits. A decoding process is applied to the codeword using the data bits and only a first partial subset of parity bits in the input, and using only a second partial subset of equations. Upon a failure to decode the codeword using the partial subsets, the codeword is re-decoded using the data bits and all parity bits in the input, and using all equations. The set of parity check equations is defined such that any parity bit in the codeword appears in multiple equations, and any parity bit in the first partial subset of the parity bits appears in a plurality of equations in the second partial subset of the equations.

Abstract: A plurality of frame buffers of a communication device store input frames for respective flows, which are units of managing communication. A sequential scheduler and an adjustment scheduler cyclically visit the plurality of frame buffers to read a frame for external output from each frame buffer. The sequential scheduler reads one frame per a visit to each frame buffer at a speed lower than a communication speed of the communication device. The adjustment scheduler reads one or more frames per a visit to each frame buffer such that a restriction on read quantity defined by a reference value greater than the shortest frame size is imposed.

Abstract: An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

Abstract: A partial outer parity management system generates a product code based on a partial data block write to a data block and partial outer parity generated by a previous partial data block write to the data block. In one implementation, a storage device includes cache storage circuit accessible by the parity generator, the cache storage circuit being configured to cache the partial outer parity generated by the previous partial data block write to the data block in a partial outer parity cache designated for association with the product code.

Abstract: An error detection/correction system provides an electronic circuit detecting and correcting transmission errors using linear programming. Linear programming techniques are made practical for real-time error correction and decoding by dividing the linear programming problem into independent parallelizable problems so that separate independent portions of the electronic circuit may simultaneously address solutions related to individual bits and/or parity rules.

Abstract: An apparatus and method are provided for transmitting and receiving a quasi-cyclic Low Density Parity Check (LDPC) code in a multimedia communication system. In the method, a signal transmission apparatus generates a quasi-cyclic LDPC code, and transmits the quasi-cyclic LDPC code to a signal reception apparatus. The quasi-cyclic LDPC code is generated by encoding an information word vector using a child parity check matrix, generated by performing one of a scaling operation, a row separation operation, and a row merge operation on a parent parity check matrix. In the scaling operation, a size of the child parity check matrix is determined. In the row separation operation, each of rows included in the parent parity check matrix is separated. In the row merge operation, the rows included in the parent parity check matrix are merged.

Abstract: A technique for injecting errors into a codeword includes generating a codeword that includes data bits and one or more checkbits. One or more bit errors are injected into the codeword by modifying at least one of the one or more checkbits.

Abstract: It is described a bad disk block self-detection method, including: each mounted chunk is partitioned into n sub-chunks, all sub-chunks having a same size, where n is an integer not less than 2; checking information is set at a fixed location of each sub-chunk, data is stored onto locations of each sub-chunk other than the fixed location, where the checking information is parity checking information for the data; and when the data is read or written, data verification is performed based on the checking information set at the fixed location of the read sub-chunk. It is also described a bad disk block self-detection apparatus and a computer storage medium. With the described above, the bad block on the disk can be detected rapidly, and it is able to instruct data migration and disk replacement.

Abstract: A semiconductor integrated circuit includes: a first-combinational-circuit to output a state-value depending on an input signal and a parity-value of the state-value which are stored by a first-flip-flop-circuit; a first-parity-check-circuit to perform a parity check based on the state-value and the parity-value and output a first-parity-error; a second-flip-flop-circuit to store the state-value and the parity-value output by the first-combinational-circuit; a second-parity-check-circuit to perform a parity check based on the state-value and the parity-value stored in the second-flip-flop-circuit and output a second-parity-error; and a selector to, when the first-parity-error is not output but the second-parity-error is output, output the state-value stored in the first-flip-flop-circuit to the first-combinational-circuit, and when the first-parity-error is output but the second-parity-error is not output, output the state-value stored in the second-flip-flop-circuit to the first-combinational-circuit, wherei

Abstract: A plurality of columns for a check matrix that implements a distance d linear error correcting code are populated by providing a set of vectors from which to populate the columns, and applying to the set of vectors a filter operation that reduces the set by eliminating therefrom all vectors that would, if used to populate the columns, prevent the check matrix from satisfying a column-wise linear independence requirement associated with check matrices of distance d linear codes. One of the vectors from the reduced set may then be selected to populate one of the columns. The filtering and selecting repeats iteratively until either all of the columns are populated or the number of currently unpopulated columns exceeds the number of vectors in the reduced set. Columns for the check matrix may be processed to reduce the amount of logic needed to implement the check matrix in circuit logic.

Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.

Abstract: A method for encoding data bits includes computing checksum parity bits based on the data bits. A set of equations satisfied by the data bits and the checksum parity bits corresponds to a dense parity-check matrix. The dense parity-check matrix comprises sums of permutation sub-matrices.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for encoding data sets.

Abstract: A method includes, in an Error Correction Code (ECC) decoder that includes variable nodes and check nodes, receiving in a given variable node Check-to-Variable (C2V) messages from a subset of the check nodes. Magnitudes for respective Variable-to-Check (V2C) messages to be sent to the check nodes in the subset are computed based on the received C2V messages. A single sign is computed, for use in all the V2C messages to be sent from the given variable node to the check nodes in the subset. The V2C messages are sent from the given variable node to the check nodes in the subset, such that each V2C message includes a respective magnitude and the single sign.

Abstract: A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v?)) based on a coded binary word (v?). The error syndrome bit sequence (s(v?)) indicates whether the coded binary word (v?) is a code word of an error correction code (C) used for coding the coded binary word (v?). The test sequence provider provides a test bit sequence (Ti) of the circuit that is different than the error syndrome bit sequence (s(v?)), if the error syndrome bit sequence (s(v?)) indicates that the coded binary word (v?) is a code word of the error correction code (C). The evaluation circuit detects an erroneous processing of the test bit sequence (Ti) by the circuit based on a test output signal (R(Ti)?)—caused by the test bit sequence (Ti)—of the circuit.

Abstract: Systems and techniques for serial data stream operations are described. A described system includes a serial bus communicatively coupled with a memory structure to handle a serial data stream from or to the memory structure; generators configured to generate enablement signals that are associated with different bit-groups of the serial data stream, each of the enablement signals including pulses that are aligned with time-slots that are associated with a respective bit-group; logic elements configured to store internal states and produce output signals that are based on the serial data stream, the enablement signals, and the internal states, and circuitry configured to capture values. Each of the enablement signals enables a respective logic element to selectively change a respective internal state responsive to bit-values of a respective bit-group. Each of the captured values represents an output of a respective logic element that is responsive to all bit-values of a respective bit-group.