Abstract: Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput.

Abstract: Systems and methods for increasing the efficiency of data storage processes for high performance, high core number computing systems. In one embodiment, the systems of the present invention perform sequential I/O whenever possible. To achieve a high degree of sequentiality, the block allocation scheme is determined by the next available block on the next available disk. This simple, non-deterministic data placement method is extremely effective for providing sequential data streams to the spindle by minimizing costly seeks. The sequentiality of the allocation scheme is not affected by the number of clients, the degree of randomization within the incoming data streams, the logical byte addresses of incoming request's file extents, or the RAID attributes (i.e., parity position) of the block.

Abstract: A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W>=1. The architecture does not require duplication of extrinsic memory which greatly reduces decoder complexity. The size of the memory is also independent of sub-matrix degree which makes the decoder scalable for large W values.

Abstract: A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1.

Abstract: A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.

Abstract: A circuit outputs, upon receipt of data and a parity of the data, count information on the number of bits in the data represented as a base-n number (n: a natural number equal to or larger than 2) and the parity of the count information. The circuit includes a determining unit and an inverting unit. The determining unit determines that the number of bits in the data represented as a base-n number is a specific value. The inverting unit outputs, as the parity of the count information, any one of a value of the parity of the data and an inverted value of the parity depending on a result of determination by the determining unit.

Abstract: In order to generate a parity of output data from a priority encoder without increasing processing time or making the circuitry complex, the present invention a first level generator having a plurality of first component circuits arranged in parallel, into each of which one of a plurality of sets of a specific number of bits of the binary data in sequence from the most significant bit is input and each of which generates and outputs a first signal for parity generation of bit data of the specific number of bits and a second signal representing whether or not the entire bit data of the specific number of bits is “0s” or “1s”; and a second level generator generating the parity of the binary data based on the first signal and the second signal from each of said first component circuits of said first level generator.

Abstract: To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N?K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes.

Abstract: This disclosure relates generally to data decoding, and more particularly to iterative decoders for data encoded with a low-density parity check (LDPC) encoder. LDPC decoders are disclosed that use reduced-complexity circular shifters that may be used to decode predefined or designed QC-LDPC codes. In addition, methods to design codes which may have particular LDPC code performance capabilities and which may operate with such decoders using reduced-complexity circular shifters are provided. The generation of quasi-cyclic low density parity check codes and the use of circular shifters by LDPC decoders, may be done in such a way as to provide increased computational efficiency, decreased routing congestion, easier timing closure, and improved application performance.

Abstract: Systems and methods for decoding low density parity check (LDPC) codes are provided. An input message, representing a codeword encoded using a parity check matrix, is processed and data associated with each of the layers of the parity check matrix is computed. A first layer of the parity check matrix includes a first circulant configured to be updated using the data associated with a second layer of the parity check matrix. A second circulant in the first layer of the parity check matrix, configured to be updated using the data associated with the second layer of the parity check matrix, is identified. The first and second circulants are updated using the data associated with the first and second layers of the parity check matrix.

Abstract: A decoding device allowing a high-speed decoding operation. In a decoding section (215), if a degree of a check equation by a check matrix is D and the relationship between the check equation of the j+first row of the check matrix and the check equation of the jth row is shifted by n-bit, row processing operation sections (405#1 to 405#3) and column processing operation sections (410#1 to 410#3) perform the operation of a protograph in which the columns of the check matrix are delimited for each “(D+1)×N (N: natural number),” and the rows of the check matrix are delimited for each “(D+1)×N/n,” and formed as the processing unit of the row processing operation and column processing operation.

Abstract: A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The scrambled and repeated bits are input to an inner coder, which has a rate substantially close to one.

Abstract: Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with bi-directional error correction protection. In some embodiments, multiple multi-level parity cells are used to represent parity values stored in codewords of an NVM device. Other embodiments may be described and claimed.

Abstract: Error detection using parity compensation in binary coded decimal (BCD) and densely packed decimal (DPD) conversions, including a computer program product having a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving formatted decimal data in a first format, the formatted decimal data consisting of a DPD format data or a BCD format data. One or more first parity bits are generated by converting the received data into a second format of the formatted decimal data, and by determining the parity of the data in the second format. One or more second parity bits are generated directly from the received data. An error flag is set to indicate an error in the data in the second format in response to the first parity bits not being equal to the second parity bits.

Abstract: A multiple-input multiple-output (MIMO) transmitter including a scrambler and a forward error correction encoder. The scrambler is configured to receive user data and generate scrambled data in response to the user data. The forward error correction encoder is configured to generate encoded data, in response to the scrambled data, using a low density parity check (LDPC) matrix, wherein the LDPC matrix is derived from a specified base matrix.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: Low-latency programmable encoders, and more particularly, low-latency programmable encoders which use low-density parity check (LDPC) codes in combination with an outer systematic code. The LDPC encoder is programmable for any irregular circulant-based LDPC code. The code profile, block length, number of block rows, and number of block columns can vary. The LDPC encoding and the outer systematic code encoding can proceed in a parallel manner (e.g., simultaneously) instead of in a serial manner.

Abstract: One embodiment of the present invention relates to an error tolerant memory circuit having a low hardware overhead that can tolerate both single volatile soft errors and permanent errors. In one embodiment, the method and apparatus comprise a memory circuit having a plurality of memory element pairs, respectively having two memory storage elements configured to store a data unit. One or more parity generation circuits are configured to calculate a first parity bit from data written to the plurality of memory element pairs (e.g., the two memory storage elements) and a second parity bit from data read from one of the two memory storage elements in the plurality of memory element pairs. Based upon the calculated first and second parity bits, the memory circuit chooses to selectively output data from memory storage elements not known to contain an error.

Abstract: A retransmission method based on Low Density Parity Check (LDPC) and devices thereof are provided in embodiment of this present invention, so as to increase the system throughput. In the present invention, when retransmission is needed, the partial bits in the information sequence to be retransmitted are replaced by the prior information that the transmitter and the receiver both have know, with the replaced information sequence is LDPC coded, LDPC check sequence is obtained and is sent to the receiver. After receiving the LDPC check sequence, the receiver decodes the information sequence including the prior information with the LDPC check sequence. If the decoding is successful, after removing the prior information from the decoded information sequence, the receiver refills the decoded bits in a previous received information sequence, and performs decoding again with an LDPC check sequence corresponding to the previous received information sequence and obtains a complete information sequence.

Abstract: An embedded electronic device is provided. The embedded electronic device comprises a flash memory and a processor. The flash memory comprises a plurality of data storage blocks. The processor performs a parity check process to determine parity data of operation system (OS) data, wherein the parity data serves as a backup for the operation system (OS) data. The processor stores the operation system (OS) data and corresponding parity data into the data storage block of the flash memory.

Abstract: An apparatus and method for transmitting a signal in a communication system using a Hybrid Automatic Repeat reQuest (HARQ) scheme are provided. The method includes generating a codeword vector by encoding an information vector by using a first parity check matrix of Low Density Parity Check (LDPC) codes, generating a transmission vector by processing the codeword vector, and transmitting the transmission vector. When the first parity check matrix includes a plurality of square matrix columns, each square matrix includes a size of L×L, the first parity check matrix is one of p parity check matrixes stored in the signal transmission apparatus, the p parity check matrixes support different numbers of information vector square matrix columns, and each of the numbers of information vector square matrix columns indicates the number of square matrix columns corresponding to the information vector from among the plurality of square matrix columns.

Abstract: A method for determining a transport block size and a signal transmission method using the same are disclosed. When the signal transmission method constructs a transport block size combination by predetermining the transport block size, it prevents the insertion of any dummy bits in consideration of the limitation of an input bit length of an encoder during an encoding step. If a CRC is attached to the transport block and the transport block is segmented into a plurality of code blocks, the signal transmission method can establish a length of the transport block in consideration of a length of the CRC attached to each code block.

Abstract: A method for constructing LDPC (Low-Density Parity-Check) code in the mobile digital multimedia broadcast system is provided, wherein the Low-Density Parity-Check matrix of the LDPC code is iteratively constructed according to a code-table and expansion method, and the code-table is a part of the constructed Low-Density Parity-Check matrix. According to the constructing method of the present invention, the LDPC code having excellent performance of error correcting coding which is applicable to the mobile digital multimedia broadcast system.

Abstract: An encoding apparatus includes a systematic encoder that generates information bits and parity bits, both of which are transmitted selectively to a decoding apparatus. At certain points, sufficient bit data are transmitted to identify the state of the systematic encoder. The decoding apparatus partitions the received bits at these identifiable points, and processes each partition separately by predicting the information bits, modifying the predicted information bits according to the received information bits, and using the parity bits to correct errors in the resulting information bits. In video coding, this partitioning scheme can deal flexibly with multiple image formats without requiring extra decoding circuitry. With a parallel decoding apparatus, the number of decoding units operating concurrently can be changed flexibly. The error correcting capability of the decoding apparatus is also improved.

Abstract: A method in a communication system, where a systematic code obtained by systematic encoding of information bits having dummy bits inserted and by deletion of the dummy bits from results of the systematic encoding is transmitted. On a receiving side, the deleted dummy bits are inserted into the received systematic code and then decoded. The method includes: deciding a size of dummy bits for insertion into information bits; segmenting the information bits into a number of code blocks when a bit size of the information bits is greater than a stipulated size; inserting dummy bits into each block of the segmented information bits in conformity with a dummy bit insertion pattern; performing systematic encoding of each block of the information bits into which the dummy bits are inserted, and deleting the dummy bits from the results of the systematic encoding to generate a systematic code.

Abstract: Digital communication coding methods are shown, which generate certain types of low-density parity-check (LDPC) codes built from protographs. A first method creates protographs having the linear minimum distance property and comprising at least one variable node with degree less than 3. A second method creates families of protographs of different rates, all structurally identical for all rates except for a rate-dependent designation of certain variable nodes as transmitted or non-transmitted. A third method creates families of protographs of different rates, all structurally identical for all rates except for a rate-dependent designation of the status of certain variable nodes as non-transmitted or set to zero. LDPC codes built from the protographs created by these methods can simultaneously have low error floors and low iterative decoding thresholds.

Abstract: A prepended parity data encoder is loaded with sets of data and constant data, which are used for parity calculation. A shift circuit shifts each of the plural sets of data and the constant data, one bit at a time in parallel. When the constant data is output from the shift circuit, a parity generator dynamically generates prepended parity data based on the constant data and the plural sets of data.

Abstract: A data transfer method includes reading data from a NAND flash memory in pages into a first buffer, transferring a parity in the data read into the first buffer to a second buffer, after transferring the parity to the second buffer, transferring a main data in the data read into the first buffer to the second buffer, on the basis of the parity, correcting an error in the main data transferred to the second buffer, and transferring an error-corrected main data to a third buffer.

Abstract: A transmission device in a communication system where a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deletion of the dummy bits from the results of the systematic encoding is transmitted. The transmission device inserts dummy bits into information bits based on an interleaving pattern of an interleaving portion in a turbo encoder; performs systematic encoding of the information bits into which the dummy bits are inserted, and then deletes the dummy bits from the results of the systematic encoding to generate a systematic code; and transmits the systematic code. By considering the interleaving pattern, original bit positions, which, after interleaving, exists within the ranges of stipulated numbers of bits at the beginning and at the end, are determined in advance, and the dummy bit insertion portion executes control so as not to insert dummy bits into the original bit positions.

Abstract: Techniques to perform iterative decoding of concatenated low-density parity-check codes (LDPC) are described. Iterative decoding of the concatenated code is achieved by performing T common iterations, wherein a common iteration comprises t1 decoding iterations on the inner LDPC code my means of a first decoder (340) followed by t2 decoding iterations on the outer LDPC code my means of a second decoder (350) , and wherein the two decoders exchange soft-output information.

Abstract: A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.

Abstract: This invention relates generally to a packet recovery algorithm for real-time (live) multi-media communication over packet-switched networks, such as the Internet. Such multi-media communication includes video, audio, data or any combination thereof. More specifically, the invention comprises a forward error correction (FEC) algorithm that addresses both random and burst packet loss and errors, and that can be adjusted to tradeoff the recoverability of missing packets and the latency incurred. The transmitter calculates parity packets for the rows, columns and diagonals of a block of multi-media data packets using the exclusive or (XOR) operation and communicates the parity packets along with the multi-media data packets to the receiver. The receiver uses the parity packets to recover missing multi-media data packets in the block. The FEC algorithm is designed to be able to recover long bursts of consecutive missing data packets.

Abstract: An apparatus and method for transmitting and receiving data in a wireless communication is provided. The method includes determining a number of zero-padding bits, determining a number (Npad) of bit groups in which all bits are padded with zeros, padding the all bits within 0th to (Npad?1)th bit groups indicated by a shortening pattern with zeros, mapping information bits to bit positions which are not padded in Bose Chaudhuri Hocquenghem (BCH) information bits, BCH encoding the BCH information bits to generate Low Density Parity Check (LDPC) information bits, and LDPC encoding the LDPC information bits to generate a zero-padded codeword, wherein the shortening pattern is defined as an order of bit groups defined as 6, 5, 4, 9, 3, 2, 1, 8, 0, 7, 10 and 11.

Abstract: A method for data transmission in a multiple input multiple output (MIMO) system. The method for data transmission includes receiving multiple input data streams and performing low density parity check (LDPC) encoding of the input data streams utilizing a parity check matrix. The parity check matrix comprises a plurality of sub-parity check matrices for encoding respective associated ones of the input data streams and performing space time encoding for transmitting the LDPC encoded input data streams over a plurality of antennas. The performing of the LDPC encoding of the input data streams includes generating one or more connection matrices, each connection matrix for injecting information of one of the input data streams into the encoding of another one of the input data streams.

Abstract: A method for creating cyclic permutation matrices P (810), with an arbitrary size Z×Z set by a parameter Z5 and which are used to create one or more LDPC related matrices in OFDMA systems, comprising: defining an integer value Z; creating an initial matrix (810); creating a matrix (810) by using cyclic shifts to each row; repeating stage 3, up to Z?2 times as required, thus creating up to Z?2 matrices: P(o) . . . P(Z?I); creating an additional stairs matrix P(st). A method for using cyclic per-mutation matrixes P (840), with a fixed size Z×Z set by a parameter Z, and which are used to create one or more LDPC related matrices (820) in OFDMA systems, comprising: defining an integer value Z; storing in memory means an initial matrix (810) and its cyclic shifts permutations (840), thus keeping memory means matrices: P(o) . . . P(Z?I); storing an additional stairs matrix P(st) (840); using these matrices (810) to create LDPC related matrices (840) or LDPC operations.

Abstract: A method and apparatus are provided for error correction of a communication signal. To allow for retransmission of information in response to error determination with respect to a transmission of the information, the operating sampling rate for a communication channel is increased over its normal sampling rate. At the increased operating rate, retransmissions may be made while at least maintaining the overall data rate of the communication channel with respect to its normal sampling rate. The retransmissions may be conducted using automatic repeat request (ARQ) techniques. In an embodiment, operating at increased sampling rate allows for a decrease in the required signal-to-noise ratio at a given bit error rate for the communication channel.

Abstract: A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation.

Abstract: A method of low latency encoding of an input bit sequence (S0) to yield an encoded bit sequence (S), and a corresponding decoding method, said encoding method including: a first encoding step (E1) applied to bits of the input bit sequence (S0), using a first code; an interleaving step (E3) in which an interleaver interleaves the bits obtained from said first code; and a parity, second encoding step (E4) applied to the bits obtained from said interleaver, using a second code, to generate said encoded bit sequence (S). The parity, second encoding step (E4) starts after a predetermined number ? of bits have been interleaved, said predetermined number ? of bits ranging between a first lower number ?i of bits depending on one or more parameters of said interleaving step (E3) and a first higher number ?s of bits corresponding to the total number of bits to be processed during said interleaving step (E3).

Abstract: A receiving apparatus including, an LDPC decoder configured to decode both of the data signal and the transmission control signal, a data signal input buffer arranged before the LDPC decoder and configured to hold the received data signal and a transmission control signal input buffer arranged before the LDPC decoder and configured to hold the received transmission control signal, and a controller configured to select one of the data signal held in the data signal input buffer and the transmission control signal held in the transmission control signal input buffer as a signal subject to decoding and transmit the selected signal to the LDPC decoder to make the LDPC decoder decode the signal subject to decoding.

Abstract: A method and apparatus for decoding transmissions in a wireless communications network is provided. A receiver includes a receive path. The receive path includes a low density parity check (LDPC) decoder. The receiver is configured to receive encoded transmissions and perform low density parity check decoding operations using a CRISP decoder. The CRISP decoder includes a plurality of memory units, and a plurality of processors.

Abstract: Provided are a method for producing a parity check matrix for low complexity and high speed decoding, and an apparatus and method for coding a Low Density Parity Check (LDPC) code using the same. The method includes: calculating a cyclic shift value of a subblock to a matrix; and when the calculated cyclic shift values of the subblock are arrayed in the matrix, producing a parity check matrix by arraying the cyclic shift values of the subblock except ‘0 matrix’ without duplication to any one column.

Abstract: A method for generating a parity check matrix to decode a plurality of underdetermined nodes, includes the steps of: determining a plurality of specific nodes according to a predetermined parity check matrix; determining a plurality of weightings corresponding to the plurality of specific nodes; and sorting the plurality of specific nodes according to the plurality of weightings to generate the parity check matrix to store in a storage device.

Abstract: A method of encoding data using a parity check matrix is disclosed. The method of encoding data using a parity check matrix includes receiving information bit streams, and encoding the information bit streams using the parity check matrix which includes a systematic part and a parity part having a lower triangle type.

Abstract: The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors.

Abstract: Input data (1A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file 10, an error detecting code is added in an error detection calculation circuit 20, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuit 30 to record the data in a storage 40. In the reproduction, error correction in units of symbols is performed to reproduced data from the storage 40 in an error correction circuit 70, error detection processing is performed in an error detection calculation circuit 80, and then data having the integral multiple of 8 bits is recovered in a register file 90 to output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.

Abstract: This invention relates to field of cloud storage technology and especially relates to a cloud storage data access method, apparatus and system.

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract: An apparatus for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix is provided. The apparatus includes an interleaver for interleaving a descending bit-ordered codeword having a predetermined size and in accordance with a predetermined modulation scheme; and a bit mapper for mapping codeword bits constituting the interleaved codeword in accordance with a predetermined mapping scheme that takes into account degrees of the codeword bits and reliability characteristics of modulation symbol-constituting bits based on the predetermined modulation scheme.

Abstract: A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data.

Abstract: A method of encoding data into a chain reaction code includes generating a set of input symbols from input data. Subsequently, one or more non-systematic output symbols is generated from the set of input symbols, each of the one or more non-systematic output symbols being selected from an alphabet of non-systematic output symbols, and each non-systematic output symbol generated as a function of one or more of the input symbols. As a result of this encoding process, any subset of the set of input symbols is recoverable from (i) a predetermined number of non-systematic output symbols, or (ii) a combination of (a) input symbols which are not included in the subset of input symbols that are to be recovered, and (b) one or more of the non-systematic output symbols.