Masking Faults In Storage Systems Using Spares And/or By Reconfiguring (epo) Patents (Class 714/E11.084)

  • Publication number: 20110289350
    Abstract: A backup and restoration process which first attempts to recover information blocks from locally connected information handling systems executing a backup/restore service before looking to the slower access cloud store to recover data blocks.
    Type: Application
    Filed: May 18, 2010
    Publication date: November 24, 2011
    Inventors: Carlton Andrews, Clint H. O'Connor, Yuan-Chang Lo
  • Publication number: 20110289345
    Abstract: A checkpointing fault tolerance network architecture enables a backup computer system to be remotely located from a primary computer system. An intermediary computer system is situated between the primary computer system and the backup computer system to manage the transmission of checkpoint information to the backup VM in an efficient manner. The intermediary computer system is networked to the primary VM through a high bandwidth connection but is networked to the backup VM through a lower bandwidth connection. The intermediary computer system identifies updated data corresponding to memory pages that have been least recently modified by the primary VM and transmits such updated data to the backup VM through the low bandwidth connection. In such manner, the intermediary computer system economizes the bandwidth capacity of the low bandwidth connection, holding back updated data corresponding to more recently modified memory pages, since such memory pages may be more likely to be updated again in the future.
    Type: Application
    Filed: May 18, 2010
    Publication date: November 24, 2011
    Applicant: VMWARE, INC.
    Inventors: Ole Agesen, Raviprasad Mummidi, Pratap Subrahmanyam
  • Publication number: 20110289366
    Abstract: A method begins by a processing module identifying a memory loading mismatch between a first memory device and a second memory device of a dispersed storage unit, wherein the first memory device is assigned a first range of slice names and the second memory device is assigned a second range of slice names. The method continues with the processing module determining an estimated impact to reduce the memory loading mismatch and when the estimated impact compares favorably to an impact threshold, modifying the first and second ranges of slices names to produce a first modified range of slice names for the first memory device and a second modified range of slice names for the second memory device based on the memory loading mismatch and transferring one or more encoded data slices between the first and second memory devices in accordance with the first and second modified ranges of slice names.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 24, 2011
    Applicant: CLEVERSAFE, INC.
    Inventors: Andrew Baptist, Greg Dhuse
  • Publication number: 20110283136
    Abstract: The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information.
    Type: Application
    Filed: July 20, 2011
    Publication date: November 17, 2011
    Applicant: Icera Inc.
    Inventors: David Alan Edwards, Joe Woodward
  • Publication number: 20110283135
    Abstract: Embodiments are described for managing memory faults. An example system can include a memory controller module to manage memory cells and report memory faults. An error buffer module can store memory fault information received from the memory controller. A notification module can be in communication with the error buffer module. The notification module may generate a notification of a memory fault in a memory access operation. A system software module can provide services and manage executing programs on a processor. In addition, the system software module can receive the notifications of the memory fault for the memory access operation. A notification handler may be activated by an interrupt when the notification of the memory fault in the memory access operation is received.
    Type: Application
    Filed: May 17, 2010
    Publication date: November 17, 2011
    Applicant: Microsoft Corporation
    Inventors: Doug Burger, Jim Larus, Karin Strauss, Jeremy Condit
  • Publication number: 20110264951
    Abstract: Systems and methods for reducing problems and disadvantages associated with traditional approaches to data and program storage on an information handling system are provided. A method may include determining if a primary storage resource has a failure. The method may further include, in response to determining that the storage resource does not have a failure: booting from a first operating system stored on the primary storage resource, monitoring data stored to the primary storage resource to identify data to be copied to a persistent storage resource, and copying the identified data to the persistent storage resource. The method may further include, in response to determining that the storage resource has a failure: booting from a second operating system stored on the persistent storage resource, and via the second operating system, providing access to the copied identified data copied to the persistent storage resource.
    Type: Application
    Filed: April 22, 2010
    Publication date: October 27, 2011
    Applicant: DELL PRODUCTS L.P.
    Inventors: Thomas L. Pratt, Christopher A. Spencer, Munif M. Farhan, Sharon Lyn Hanson
  • Publication number: 20110264947
    Abstract: An on-line client service method for a storage apparatus includes establishing a link between a client host and the storage apparatus for detecting the current status of the storage apparatus, the client host generating a diagnostic result of the storage apparatus, the client host transmitting the diagnostic result to a far-end server, the far-end server determining whether the storage apparatus functions abnormally according to the diagnostic result. If the storage apparatus functions abnormally, the client host reloads a firmware provided by the far-end server to the storage apparatus, and determines whether the storage apparatus functions abnormally after the storage apparatus is reloaded with the firmware.
    Type: Application
    Filed: July 8, 2011
    Publication date: October 27, 2011
    Inventor: Ren-Wei Chen
  • Publication number: 20110246814
    Abstract: In certain embodiments, replicating data elements includes calculating a key value for a data element. The key value is calculated from at least a part of content of the first data element. K computing elements are automatically selected from X computing element nodes according to the key value and a mapping schema. K is a greater than 2 and less than X. The computing element nodes each include computer-readable memory embodied within one or more routers. K replications of the data element are automatically written to the computer-readable memory of the K computing element nodes.
    Type: Application
    Filed: April 2, 2010
    Publication date: October 6, 2011
    Applicant: Cisco Technology, Inc.
    Inventors: Andrei Agapi, Richard A. Payne, Robert M. Broberg, John A. DeNisco
  • Publication number: 20110202789
    Abstract: An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.
    Type: Application
    Filed: April 25, 2011
    Publication date: August 18, 2011
    Applicant: RAMBUS INC.
    Inventors: Adrian E. Ong, Naresh Baliga
  • Publication number: 20110161727
    Abstract: A solid state storage system includes a flash memory region comprising a plurality of memory blocks and a plurality of replacement blocks corresponding to error-occurred blocks when errors occur in the memory blocks; and a memory controller configured to perform a control operation to replace the error-occurred blocks with the replacement blocks, wherein the error-occurred blocks comprise correctable blocks and uncorrectable blocks, and wherein the memory controller determines whether the error-occurred blocks are the correctable blocks or the uncorrectable blocks and controls zones of the replacement blocks, replaced in correspondence to the correctable blocks, to be allocated a plurality of times.
    Type: Application
    Filed: July 19, 2010
    Publication date: June 30, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Myung Suk LEE, Jeong Soon Kwak, Kyeong Rho Kim, Yang Gi Moon
  • Publication number: 20110161726
    Abstract: In some embodiments, the invention involves a system and method relating to system recovery in a fault resilient manner by isolating errors associated with the management engine (ME) UMA memory. BIOS logs errors occurring on memory within the system. The ME UMA is invisible to the host OS, so the OS will not be notified about the errors occurring in the ME UMA range. When an error threshold has been reached for a memory unit in which ME UMA resides, ME UMA data is migrated to a previously reserved backup region of memory and the ME is notified of the new ME UMA location. The faulty memory is flagged for replacement at a next maintenance cycle. Embodiments may be applied to workstations that utilize ECC memory protection which utilize AMT (Active Management Technology) and ME UMA. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Inventors: Robert C. Swanson, Mallik Bulusu, Vincent J. Zimmer
  • Publication number: 20110154102
    Abstract: Availability of an information system including a storage system that performs remote copy between two or more storage apparatuses and a host computer using such storage system is improved. A third storage apparatus including a third volume is coupled to a first storage apparatus, a fourth storage apparatus including a fourth volume is coupled to a second storage apparatus, the first and third storage apparatuses perform remote copy of copying data stored in a first volume to the third volume, the first and second storage apparatuses perform remote copy of copying data stored in the first volume to a second volume, and the third and fourth storage apparatuses perform remote copy of copying data stored in the third volume to the fourth volume.
    Type: Application
    Filed: March 3, 2011
    Publication date: June 23, 2011
    Inventors: Hiroaki AKUTSU, Takashige Iwamura, Kenta Ninose, Yasuo Watanabe, Yasutomo Yamamoto, Yoshiaki Eguchi, Hisao Homma
  • Publication number: 20110154105
    Abstract: Some embodiments of the invention shift the responsibility for creating parity and error correction blocks from the hardware or software RAID units or modules to the computer system's file system, allowing the file system's existing mechanisms of write atomicity to be used to help ensure consistency of the on-disk information throughout all or increasing portions of the information saving and/or updating cycle.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Inventor: David Woodhouse
  • Publication number: 20110145633
    Abstract: Described are embodiments of an invention for blocking write access to memory modules of a solid state drive. The solid state drive includes a controller access module or a memory access module that controls write access to the solid state drive and the memory modules of the solid state drive. Upon determining that a memory module has failed, the failed memory module or the entire solid state memory device is configured to be read only to prevent an errant write of data over critical data. Further, a failed memory module, or solid state device memory having a failed memory module, may be replaced upon failure.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louie Arthur Dickens, Timothy A. Johnson, Craig Anthony Klein, Gregg Steven Lucas, Daniel James Winarski
  • Patent number: 7958304
    Abstract: Redundant Array of Inexpensive Disks (RAID) groups in a storage system are dynamically reconfigured by merging and splitting the RAID groups. When an indication of a change to data or system characteristics is received, disks in the RAID groups of the storage system can be reorganized to adapt to the change.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: June 7, 2011
    Assignee: Network Appliance, Inc.
    Inventors: Atul Goel, James Leong, Ratnesh Gupta
  • Publication number: 20110131446
    Abstract: To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines.
    Type: Application
    Filed: November 22, 2010
    Publication date: June 2, 2011
    Applicant: Elpida Memory, Inc.
    Inventor: Hiroto KINOSHITA
  • Publication number: 20110131444
    Abstract: This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 2, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Bruce D. Buch, Ara Patapoutian, Bengt A. Ulriksson, Bernardo Rub
  • Publication number: 20110113280
    Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.
    Type: Application
    Filed: November 10, 2009
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Valerie H. CHICKANOSKY, Kevin W. GORMAN, Suzanne GRANATO, Michael R. OUELLETTE
  • Publication number: 20110113279
    Abstract: A redundant and fault tolerant solid state disk (SSDC) includes a determination module configured to identify a first SSDC configured to connect to a flash array and a second SSDC configured to connect to the flash array. A capture module is configured to capture a copy of an I/O request received by the first SSDC from a port of a dual port connector, and/or capture a copy of an I/O request received by the second SSDC from a port of the dual port connector, and identify a write I/O request from the I/O request. A detection module is configured to detect a failure in the first SSDC. A management module is configured to manage access to a flash array by the first SSDC and the second SSDC. An error recovery and failover module is configured to automatically reassign work from the first SSDC to the second SSDC.
    Type: Application
    Filed: November 12, 2009
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian J. Cagno, John C. Elliott, Gregg S. Lucas, Andrew D. Walls
  • Publication number: 20110113281
    Abstract: A data storage system and method are disclosed. The data storage system includes a first memory, a controller, a counting module, and a checking and correcting module. Copyback operations are performed in the first memory. The controller couples the first memory to the counting module and the checking and correcting module. The counting module provides a counting operation for the copyback operations at different logic addresses of the first memory and, according to a counting result of the counting operation, determines whether a checking and correcting requirement has been satisfied by any of the logic addresses. The checking and correcting module receives data read out from the first memory, wherein the received data corresponds to a satisfying logic address, and checks, or checks and corrects the received data to correct the first memory accordingly.
    Type: Application
    Filed: May 20, 2010
    Publication date: May 12, 2011
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Bo Zhang, Honggang Chai, Liang Chen
  • Publication number: 20110106755
    Abstract: A method may include generating a list of current files stored in a user device, wherein the list of current files includes unique file identifiers, each associated with a corresponding one of the current files. The method may further include sending the list of current files from the user device to a network device and receiving a copy list from the network device in the user device. The copy list may be generated by comparing the list of current files to a list of previously copied files, and the list of previously copied files may include unique file identifiers, each associated with a different one of the previously copied files. The method may include sending the files listed in the copy list from the user device to the network device.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 5, 2011
    Applicant: VERIZON PATENT AND LICENSING, INC.
    Inventors: Jack Jianxiu Hao, Wei Xia, Joseph M. Geiger, Guanrao Chen
  • Publication number: 20110078495
    Abstract: A storage control apparatus of the present invention reduces the frequency of disk drive failures. An error management part manages the number of times errors occur in respective disk drives. A disk drive in which the number of errors meets or exceeds a threshold value is selected as a disk drive to be restarted. A restart control part commences difference management prior to restarting the disk drive targeted for restart. A difference management part manages parity group-related update locations using a difference bitmap. After commencing difference management, the restart control part restarts the disk drive in which the error was detected. This makes it possible to resolve an error caused by a firmware hangup or the like.
    Type: Application
    Filed: December 8, 2010
    Publication date: March 31, 2011
    Applicant: HITACHI, LTD.
    Inventors: Naoki Higashijima, Ikuya Yagisawa
  • Publication number: 20110060942
    Abstract: At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.).
    Type: Application
    Filed: November 11, 2010
    Publication date: March 10, 2011
    Inventor: Martin VORBACH
  • Publication number: 20110055623
    Abstract: The presented solid state storage system provides an efficient manner of processing read and write operations in a memory block that has a faulty page of memory within it. The solid state storage system includes a flash memory area and a memory controller. The memory controller stores link information into a buffer, allocates a first temporary physical block to resume operations of the bad block past the first bad page, updates and stores mapping information associated with the remaining portions of the bad block past the first bad page, and merges together those valid pages from among the bad block into a final physical block by merging together all prior successfully operated valid pages from among the bad block with any subsequently successfully operated valid pages which are associated with successful operations subsequently to the failure in the first bad page of the bad block.
    Type: Application
    Filed: December 29, 2009
    Publication date: March 3, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Young Ho KIM, Kyeong Rho KIM, Myung Suk LEE
  • Publication number: 20110047409
    Abstract: A storage device having an automatic backup function, which is connected to a host apparatus to store user data, is provided. The storage device includes a storage medium which stores the user data, and a controller which controls data writing and reading of the storage medium. The controller backs up at least a portion of the user data stored in the storage medium in an available region of the storage medium when the storage device is in an idle mode.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 24, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Wook HUR, Hae Jung LEE
  • Publication number: 20110029810
    Abstract: Systems and methods for automated failure recovery of subsystems of a management system are described. The subsystems are built and modeled as services, and their management, specifically their failure recovery, is done in a manner similar to that of services and resources managed by the management system. The management system consists of a microkernel, service managers, and management services. Each service, whether a managed service or a management service, is managed by a service manager. The service manager itself is a service and so is in turn managed by the microkernel. Both managed services and management services are monitored via in-band and out-of-band mechanisms, and the performance metrics and alerts are transported through an event system to the appropriate service manager. If a service fails, the service manager takes policy-based remedial steps including, for example, restarting the failed service.
    Type: Application
    Filed: July 7, 2010
    Publication date: February 3, 2011
    Inventor: Devendra Rajkumar Jaisinghani
  • Publication number: 20110029809
    Abstract: A distributed storage integrity system in a dispersed storage network includes a scanning agent and a control unit. The scanning agent identifies an encoded data slice that requires rebuilding, wherein the encoded data slice is one of a plurality of encoded data slices generated from a data segment using an error encoding dispersal function. The control unit retrieves at least a number T of encoded data slices needed to reconstruct the data segment based on the error encoding dispersal function. The control unit is operable to reconstruct the data segment from at least the number T of the encoded data slices and generate a rebuilt encoded data slice from the reconstructed data segment. The scanning agent is located in a storage unit and the control unit is located in the storage unit or in a storage integrity processing unit, a dispersed storage processing unit or a dispersed storage managing unit.
    Type: Application
    Filed: April 26, 2010
    Publication date: February 3, 2011
    Applicant: CLEVERSAFE, INC.
    Inventors: GREG DHUSE, ANDREW BAPTIST, ZACHARY J. MARK, JASON K. RESCH, ILYA VOLVOVSKI
  • Publication number: 20110022888
    Abstract: An information processing apparatus connecting a plurality of hard disks rebuilds data stored in one hard disk of the plurality of hard disks to another hard disk of the plurality of hard disks. The information processing apparatus is controlled in such a manner that when the information processing started, the rebuild is not resumed immediately after the information processing apparatus is started, and the rebuild is resumed after a predetermined time has elapsed.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 27, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Mikio Hama
  • Publication number: 20110010580
    Abstract: A memory apparatus includes a memory having a main memory area and a replacement area, and a memory controller having a function of issuing instructions corresponding to commands to carry out transmission and reception of data and reading of status information of the memory.
    Type: Application
    Filed: June 23, 2010
    Publication date: January 13, 2011
    Applicant: Sony Corporation
    Inventors: Kenichi Nakanishi, Keiichi Tsutsui, Junichi Koshiyama
  • Publication number: 20110004785
    Abstract: A fault-tolerant storage system is provided. The storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates the failed component. After invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting.
    Type: Application
    Filed: September 13, 2010
    Publication date: January 6, 2011
    Applicant: Hitachi, Ltd.
    Inventors: Masanori TAKADA, Shuji Nakamura, Kentaro Shimada
  • Publication number: 20100332895
    Abstract: Subject matter disclosed herein relates to remapping memory devices.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Inventors: Gurkirat Billing, Stephen Bowers, Mark Leinwander, Samuel David Post
  • Publication number: 20100332891
    Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 30, 2010
    Inventors: Thomas Brune, Michael Drexler, Dieter Haupt
  • Publication number: 20100325480
    Abstract: A redundant data storage system is provided comprising a first controller with top-level control of a first memory space and a second controller with top-level control of a second memory space different than the first memory space. The system is adapted for asynchronously reflectively writing state information by the first controller to the second memory space; alternatively the system is adapted for asynchronously reflectively writing state information by the second controller to the first memory space. A method is provided for operating the redundant data storage system by resolving any inconsistency between the existing state information and a modified state information associated with a state information change request, and for switching control in the redundant data storage system between the controllers.
    Type: Application
    Filed: August 23, 2010
    Publication date: December 23, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Ayman Mohammad Ghanem, Robert George Bean
  • Publication number: 20100325479
    Abstract: A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the memory device to a first location of a memory of the memory device is stopped. First data that remains in the register after the program failure is detected is transferred to a second location of the memory. At the second location of the memory, the first data is combined with second data from the first location of the memory that remains in the first location of the memory after the program failure is detected to reconstruct third data that was originally intended to be programmed in the first location before the program failure was detected.
    Type: Application
    Filed: August 23, 2010
    Publication date: December 23, 2010
    Inventor: Brady Keays
  • Publication number: 20100318840
    Abstract: The invention provides a method for managing writing errors for a nonvolatile memory. In one embodiment, the nonvolatile memory is coupled to a controller. First, data received from the controller is stored in a data register of the nonvolatile memory. The data stored in the data register is then written to a first memory space with a first write address according to instructions from the controller. The data stored in the data register is kept from being changed after the data is written to the first write address. When an error occurs in writing of the data to the first memory space, a rewrite command is sent from the controller to the nonvolatile memory. After the nonvolatile memory receives the rewrite command, the data stored in the data register is written to a second memory space with a second write address according to the rewrite command.
    Type: Application
    Filed: November 15, 2009
    Publication date: December 16, 2010
    Applicant: SILICON MOTION, INC.
    Inventor: Jung-Chuan Tsai
  • Publication number: 20100318843
    Abstract: A memory repair mechanism for the memories clustered across the multiple power domains and can be switched on and off independent of each other, thereby enabling low power operation. Enhancements in the shared Fuse Wrapper Architecture enable sharing of a plurality of parallel links connecting the memory blocks of each power domains to the Shared Fuse Wrapper architecture.
    Type: Application
    Filed: May 20, 2010
    Publication date: December 16, 2010
    Applicant: STMICROELECTRONICS PVT., LTD.
    Inventors: Viraj Vikram SINGH, Ashish Bansal, Rangarajan Ramanujam
  • Publication number: 20100306578
    Abstract: A message is generated by a computer operating on a dispersed data storage network indicating the inaccessibility of a plurality of data slices. A rebuilder application operates on the dispersed data storage grid and rebuilds inaccessible data slices, including those identified by the message.
    Type: Application
    Filed: December 29, 2009
    Publication date: December 2, 2010
    Applicant: CLEVERSAFE, INC.
    Inventors: VANCE T. THORNTON, JAMIE BELLANCA, DUSTIN M. HENDRICKSON, ZACHARY J. MARK, ILYA VOLVOVSKI
  • Publication number: 20100306583
    Abstract: Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition.
    Type: Application
    Filed: May 21, 2010
    Publication date: December 2, 2010
    Inventors: Yong-June Kim, Junjin Kong, Jaehong Kim, Han Woong Yoo
  • Publication number: 20100306581
    Abstract: Described embodiments provide for end-of-life (EOL) checking for NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device operative to store one or more data elements. In the illustrative implementation, the EOL data processing and storage management paradigm allows for the storage of data according using a selected EOL enforcement algorithm that can utilize current and/or historical correction levels. The NAND data storage EOL checking module can be operable to cooperate with one or more NAND data store components to execute one or more selected EOL operations to protect stored data.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 2, 2010
    Inventor: Joshua Johnson
  • Publication number: 20100306580
    Abstract: Various embodiments of the present invention provide systems and methods for data storage. As an example, storage devices are disclosed that include a plurality of memory blocks, an unreliable block identification circuit, and a partial failure indication circuit. Each of the plurality of memory blocks includes a plurality of memory cells that decrease in reliability over time as they are accessed. The unreliable block identification circuit is operable to determine that one or more of the plurality of memory blocks is unreliable, and the partial failure indication circuit is operable to disallow write access to the plurality of memory blocks upon determination that an insufficient number of the plurality of memory blocks remain reliable.
    Type: Application
    Filed: May 28, 2009
    Publication date: December 2, 2010
    Inventors: Brian D. McKean, David L. Dreifus, Robert W. Warren
  • Publication number: 20100299555
    Abstract: A management apparatus operable for protecting data on a failing storage device in a data processing system including a storage array having at least one of a plurality of storage devices. The management apparatus includes a receiver component for receiving a failure message indicating that the plurality of storage devices comprises the failing storage device. An analyzer component is in communication with the receiver component and responsive to receipt of the failure message, for analyzing the failure message. A sender component is in communication with the analyzer component. The sender component is adapted for, in response to the analyzer component determining the failing storage device, sending a zoning message, the zoning message instructing the storage array to isolate the failing storage device, and sending a protect message. The protect message instructs the storage array to protect data on the failing storage device.
    Type: Application
    Filed: March 29, 2010
    Publication date: November 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raymond JEPSON, Timothy F. McCARTHY, Roderick G.C. MOORE, Jonathan I. SETTLE, Jonathan W.L. SHORT
  • Publication number: 20100299556
    Abstract: A gaming machine includes a processor adapted to execute a program of a game; a biometric reader configured to capture first biometric data from the player, and a trusted cache. The trusted cache includes a nonvolatile memory that is configured to store the first biometric data; a context data save engine configured to save the context of the program to the nonvolatile memory and to associate the stored first biometric data with the saved context of the program upon the processor receiving a request from the player to suspend game play, and a context data recovery engine configured to recover the saved context from the nonvolatile memory and to cause continued execution of the program from the recovered saved context upon the biometric reader capturing second biometric data from the player that matches the stored first biometric data and receiving a request from the player to resume game play.
    Type: Application
    Filed: February 17, 2010
    Publication date: November 25, 2010
    Applicant: Mudalla Technology, Inc.
    Inventors: Eric F. TAYLOR, Jean-Marie Gatto, Thierry Brunet de Courssou
  • Publication number: 20100293420
    Abstract: System and method for using flash memory in a memory hierarchy. A computer system includes a processor coupled to a memory hierarchy via a memory controller. The memory hierarchy includes a cache memory, a first memory region of random access memory coupled to the memory controller via a first buffer, and an auxiliary memory region of flash memory coupled to the memory controller via a flash controller. The first buffer and the flash controller are coupled to the memory controller via a single interface. The memory controller receives a request to access a particular page in the first memory region. The processor detects a page fault corresponding to the request and in response, invalidates cache lines in the cache memory that correspond to the particular page, flushes the invalid cache lines, and swaps a page from the auxiliary memory region to the first memory region.
    Type: Application
    Filed: May 15, 2009
    Publication date: November 18, 2010
    Inventors: Sanjiv Kapil, Ricky C. Hetherington
  • Publication number: 20100281315
    Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
    Type: Application
    Filed: July 15, 2010
    Publication date: November 4, 2010
    Inventors: Pete D. Vogt, Dennis W. Brzezinski, Warren R. Morrow
  • Publication number: 20100281202
    Abstract: Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 4, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, John P. Karidis, Luis A. Lastras-Montano
  • Publication number: 20100275056
    Abstract: An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.
    Type: Application
    Filed: July 8, 2010
    Publication date: October 28, 2010
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventors: Hong Beom PYEON, Jin-Ki KIM, HakJune OH
  • Publication number: 20100251010
    Abstract: Shared storage systems and methods are provided. A particular shared storage system is a system including multiple instances of shared storage. Each of the instances of shared storage includes data and file system metadata separated from the data. The file system metadata includes location data specifying storage location information related to the data. A persistent common view is provided of local and remote files, file systems, and services in the shared storage.
    Type: Application
    Filed: March 30, 2010
    Publication date: September 30, 2010
    Applicant: The Boeing Company
    Inventors: Marc A. Peters, Dennis L. Kuehn, David D. Bettger, Kevin A. Stone
  • Publication number: 20100241898
    Abstract: Disclosed is storage system, that is, an array-type disk apparatus which is provided with an error monitor section which monitors the status of error occurrence in a disk drive and instructs initiation of mirroring between the disk drive and a spare disk drive when the number of errors occurred of the disk drive exceeds a specified value, and a mirror section which performs mirroring between the disk drive and spare disk drive. Storage system, that is, the array-type disk apparatus may be provided with an error monitor section which monitors the status of error occurrence in a disk drive and gives such an instruction as to set the status of the disk drive in a temporary blocked state, and a data restoring section which executes data restoration by reading data from the temporary blocked disk drive when reading from another disk drive constituting a disk array group is not possible during data restoration.
    Type: Application
    Filed: June 4, 2010
    Publication date: September 23, 2010
    Applicant: HITACHI, LTD.
    Inventors: Ikuya Yagisawa, Takeki Okamoto, Naoto Matsunami, Mikio Fukuoka, Toshio Nakano, Kenichi Takamoto, Akira Yamamoto
  • Publication number: 20100241897
    Abstract: In order to enable a rewrite of stored data to be omitted and to reduce a processing time of error concealment even if an error is detected in a process for sequentially storing variable-length data in a memory and the rewrite of the stored data is necessary, variable-length data from which an error is not detected is sequentially stored at and after a predetermined position in the memory, and error information that includes a restoration address that corresponds to an area in which variable-length data from which an error is detected is to be stored and that specifies variable-length data stored earliest in the memory from among data to be replaced with error concealment data is stored at a position preceding the predetermined position, when the error is detected.
    Type: Application
    Filed: March 24, 2010
    Publication date: September 23, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hirofumi Nagaoka, Yasuhiro Watanabe, Taro Hagiya
  • Publication number: 20100229030
    Abstract: A communication apparatus stores a first address in association with a second address of an apparatus which is targeted to permit or restrict processing of a received packet. The communication apparatus detects first and second addresses of a transmission apparatus which is a source of a packet received through a network, and if the detected first address of the transmission apparatus is stored, then the processing of the received packet is permitted or restricted. If the detected first address of the transmission apparatus is not stored in association with the second address of the transmission apparatus and the detected second address is stored, then the communication apparatus updates the stored first address with the detected first address.
    Type: Application
    Filed: June 11, 2008
    Publication date: September 9, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Hiroki Shouno