Abstract: Methods and systems for providing concise data for analyzing checker completeness, in the context of formal verification analysis of circuit designs. The methods and systems concisely report information useful to a human user (e.g., circuit designer or verification engineer) for efficiently determining what manual action should be taken next to resolve holes in verification coverage. The reported information can include lists of signals on which checkers can be written, which lists can be ranked, can be limited to a subset of interest signals, and can include corresponding cover items for each reported interest signal. The present systems and methods thereby improve on reporting provided to the user, permitting the user to more quickly advance a formal verification process toward full coverage of the relevant portions of a circuit design.

Abstract: Disclosed are a method and an apparatus for improving circuit health. The method includes obtaining an S-parameter plot of a circuit having an input port and an output port; determining a resonance frequency of the circuit based on the S-parameter plot; and estimating the health of the circuit based on the resonance frequency.

Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

Abstract: A method and apparatus for upgrading libraries in a source code program by evaluating libraries in the source code program for predetermined selection criteria specifying library performance limitations to identify at least a first library which does not meet the plurality of predetermined selection criteria and then identifying a first alternative library that is suitable for substitution for the first library so that the source code program may be automatically modified to replace the first library with the first alternative library, thereby generating a modified source code program having an upgraded library functionality.

Abstract: A method for designing a system on a target device includes identifying portions in the system to preserve based on comparing structural characteristics of the system with another system. Design results from the another system are reused for portions in the system that are preserved.

Abstract: A method for designing a system on a target device includes identifying portions in the system to preserve based on comparing structural characteristics of the system with another system. Design results from the another system are reused for portions in the system that are preserved.

Abstract: A light emitting and receiving apparatus includes a controller and a calculator. The controller acquires a first detection current from a light-receiving element when supplying a first drive current to a light-emitting element and acquires a second detection current from the light-receiving element when supplying a second drive current to the light-emitting element. The calculator generates a signal indicating deterioration of the light-emitting element when a reference value and an aging value satisfy a deterioration judgment condition, the aging value being a ratio between the first detection current and the second detection current. The detection accuracy of the light emitting and receiving apparatus is thereby improved.

Abstract: Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be stored in a cache. The storage can be based on entropy of variables used in the graph and subgraph problems. The subgraph problem storage cache can be searched for previously stored problems which match another problem in need of a solution. By retrieving subproblem variables, values, and information from the cache, the computational overhead of circuit design verification is reduced as problems are reused. Caching can be accomplished using an information theoretic approach.

Abstract: Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.

Abstract: Methods, systems, and computer storage media for providing detection of unsecure network policies in a network segment and automatically remediating the unsecure policies based on pre-defined network policies in a computing environment. In particular, a security maintenance manager of an access management system in the computing environment detects an unsecure network policy based on comparing an active configuration of the network segment to an expected configuration of the network segment and modifies the active configuration to at least restore restrictions of network policies of the expected configuration to the active configuration. In operation, the security maintenance manager periodically accesses an active configuration record for the network segment and compares the active configuration record to an expected configuration record for the network segment. Based on comparing the active configuration record to the expected configuration record, restrictions are remediated (e.g.

Abstract: An instantiated application includes both a runtime instantiation of an application image, and an administrative service operable to install in the instantiated application at least one security module during runtime of the instantiated application in a container. Prior to runtime, a design time agent can access the application image in a repository, examine the application image, and based on the examining, adding at least one security module to the application image prior to instantiation. During runtime, a runtime agent can query parameters of the container, such as static and dynamic variables available on the machine on which the container is running. The runtime agent processes these parameters in conjunction with predefined rules to determine an action such as starting, stopping, adding, and/or changing the security module, such as the method of packet inspection.

Abstract: Hardware simulation systems and methods for reducing signal dumping time and size of by fast dynamical partial aliasing of signals having similar waveform are provided. One example system is configured to receive, in real-time, a first signal from a producer entity; determine a first signal signature associated with the first signal; determine, in real-time, a second signal signature associated with the second signal; upon determining that the first signal signature matches the second signal signature, designate the first signal as a master signal and designate the second signal as a slave signal; and stop dumping the second signal to a storage space.

Abstract: Techniques for electromagnetic modelling of EM structures are described. Krylov subspace of a second EM structure is augmented with Eigen vectors of a first EM structure to form an augmented space. The second EM structure is a design variant of the first EM structure and the first EM structure is already EM modelled and simulated. Thereafter, Maxwell's equations for the second EM structure are solved using the augmented space.

Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

Abstract: Techniques and systems for optimizing a logic network are described. Some embodiments automatically identify scenarios where Boolean methods are best driven by truth tables, binary decision diagrams (BDDs) or satisfiability (SAT). Some embodiments use circuit partitioning techniques that are based on hash-tables and topological sorting, and that are capable of grouping nodes with high simplification likelihood and still are able to efficiently scale to large circuits. Some embodiments feature a generalized resubstitution framework based on computing, and implementing, the Boolean difference between two nodes. Some embodiments include enhancements to (i) gradient-based and-inverter-graph (AIG) optimization, (ii) heterogeneous elimination for kerneling, and (iii) revisitation of maximum set of permissible functions (MSPF) computation with BDDs.

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a reference model including a software specification and an implementation model at a register transfer level. Embodiments may also include generating one or more invariants based upon, at least in part, the reference model, wherein generating one or more invariants includes applying a semantic analysis. Embodiments may further include automatically generating at least one case splitting candidate based upon, at least in part, the one or more generated invariants.

Abstract: A method for sequential equivalence checking (SEC) of two representations of an electronic design includes selecting by a processor a plurality of cutpoints in the two representations of the electronic design, rendering the two representations of the electronic design abstracted; executing by the processor an assume-guarantee (AG) proof on the two abstracted representations of the electronic design; identifying by the processor a failed assertion indicating non-equivalence of a signal pair relating to one of the cutpoints; and performing by the processor a simulation on the two representations of the electronic design by successively inputting input stimuli of a trace corresponding to the failed assertion in a sequential order in which the input stimuli appear in the trace at inputs of the two representations of the electronic design to identify whether there is one or a plurality of additional non-equivalent signal pairs relating to other cutpoints of said plurality of cutpoints.

Abstract: A method of time budgeting an integrated circuit (IC) including acquiring a graph data structure and clock cycle requirements, where the graph data structure includes at least two identical blocks of a plurality of blocks that correspond to an identical design module. The method acquires internal and external delay values ports of each design module, and sets parameters, which include the internal and external delay values of the at least two identical blocks as equivalent for the identical blocks. The method performs optimization of the parameters of the ports of all of the blocks, and determines whether the optimized parameters of each of the ports satisfy predetermined requirements of the IC. The method outputs a final design of the IC design based on results of the optimization for manufacturing of the IC based on the final design.

Abstract: An electronic design automation (EDA) tool for executing topological and functional checks on an electronic circuit design (ECD) includes a processor and a memory that stores the ECD, graphical rules, and filter rules for executing the checks. The processor generates a test graph based on the ECD, replaces stretchable nodes with nested networks in the test graph to generate extended graphs, and decouples real edges and functional edges of each extended graph to generate real graphs and functional graphs, respectively. Based on the graphical rules, the processor executes the topological checks on an input graph of the ECD to identify real sub-graphs from the input graph that are isomorphic to a real graph. The processor further generates functional sub-graphs by combining a functional graph with each real sub-graph, and based on the filter rules, further executes the functional checks on the functional sub-graphs to identify output graphs.

Abstract: Configuring a hardware system includes providing a first data representative of a first assignment of a multitude of wires to a multitude of physical connections between a multitude of logic circuits of the hardware system, and transforming the first data into a second data representative of a second assignment of the multitude of wires to the multitude of physical connections. The transforming includes calculating a multitude of latencies each associated with a selected one of the multitude of wires, and assigning a first subset of the multitude of wires to at least one of the multitude of physical connections in accordance with a first improvement goal. The transforming causes the value of each one of the multitude of latencies that are associated with the first subset to be less than or equal to the first improvement goal, when the second data is used to configure the hardware system.

Abstract: Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. Our methods—which we call Quick Error Detection—Hardware (QED-H)—advantageously quickly detect and fix anomalies (bugs) within SoC hardware components—and in particular customized SoC hardware components that are not necessarily software programmable. Of further advantage, methods according to the present disclosure are compatible with existing Quick Error Detection (QED) techniques while being extensible to target software-programmable components as well. In sharp contrast to prior art methods, method(s) according to the present disclosure represent a new system validation methodology that builds validation checks in both software and hardware components seamlessly and systematically, thus enabling extremely quick error detection and localization for all digital components of the entire SoC advantageously producing productivity and time-to-market gains.

Abstract: A formal verification tool that verifies multiple sequentially-generated versions of a core circuit design by obtaining search path information from the formal verification solver for each property that is proven or disproven during a first formal verification session involving an earlier-generated circuit design version, and utilizing the search path information to perform search-path verification processes during a subsequent formal verification session to quickly verify the proven/disproven properties in a later-generated circuit design version. Each property's search path information includes counterexample traces or proof artifacts identifying the search operations utilized to achieve a corresponding counterexample or proof object that proves/disproves the property. Search-path verification involves applying the stored search path information to the later-generated circuit design version, and determining if the same counterexample or proof object is achieved.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve decision tree execution. An example method includes retrieving, with a processor, a decision tree logic expression in a sum-of-products (SOP) form, the decision tree logic expression consuming a first duration to evaluate a dataset, eliminating, with the processor, redundant variables of the decision tree logic expression by transforming the decision tree logic expression into a product-of-sums (POS) form, and evaluating, with the processor, the data set with the decision tree logic expression in the POS form, the decision tree logic expression in the POS form consuming a second duration to evaluate the data set that is less than the first duration.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine that a first sequence of signal transition representations of a first signal of the first module comprises a null sequence. The first module of a register level circuit design comprises a second module, the first module and the second module arranged in a hierarchical order. The tool can determine a second sequence of signal transition representations of a second signal of the second module. Signal transition representations of the first signal are for propagation from the first module to the second module using the second signal. The tool can extract a non-null sequence for the first sequence based on the second sequence to generate an extracted first sequence.

Abstract: Embodiments include systems and methods for automatic timing-sensitive circuit extraction for statistical timing margin analysis of custom designs. A timing-sensitive circuit extractor system can take pre- or post-layout netlists for integrated circuits and can automatically generate a timing-sensitive netlist. For example embodiments can generate a connectivity graph from the netlist and can traverse the graph with constraints defined according to measurement nodes to extract the timing-sensitive circuit. Memory timing checks and corresponding stimuli can generally be pre-defined, and a test-bench generator can generate appropriate parameters, stimuli, etc. Statistical simulations can then be performed to quickly generate results, which can be post-processed to obtain timing margin distributions and to flag out design errors.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine whether module instances of a register level circuit design share a common usage, each instance being associated with a mapping. Two instances share a common usage if a sequence of signal transition representations received by the first instance can be mapped using a first mapping to the same common sequence of signal transition representations as a mapping of another sequence of signal transition representations received by the second instance using a second mapping. A result sequence of signal transition representations was generated by a previous propagation of the common sequence through the common usage. If the two instances share the common usage, the result sequence is mapped to an output sequence for the second instance using the second mapping.

Abstract: Methods and systems for checking the integrity of a system on chip (SOC) are described. The SOC can include a controller and one or more registers. Register value(s) from the register(s) can be obtained at a first time to generate a first set of register values. Process(es) of the SOC are executed at a second time after the first time. Register values can again be obtained from the registers at a third time after the second time to generate a second set of register values. The first set of register values can be compared with the second set of register values. Based on the comparison, an operating mode of the SOC can be adjusted. The SOC integrity verification system and method can be used in safety and/or monitoring application(s), such as ASIL applications. For example, the system and method can be used in partial or fully autonomous (self-driving) automotive systems.

Abstract: In order to automatically determine a structural member that is included in a structure and has flat surfaces, an input unit is configured to input three-dimensional point group data of the structure, a flat surface extraction unit is configured to extract the flat surfaces of the structure based on the three-dimensional point group data, a grouping unit is configured to group the flat surfaces into flat surface groups based on an angle of each of the flat surfaces with respect to a reference direction and a distance between the flat surfaces, a connection relationship extraction unit is configured to extract a connection relationship between the grouped flat surface groups, and a determination unit is configured to determine the structural member that the structure is constructed from based on the extracted connection relationship.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing clones for an electronic design. These methods and systems identify a schematic design of an electronic design and a set of cloning rules, configurations, or settings for implementing clones for the electronic design. These methods and systems then generate a plurality of synchronous clones in a layout of the electronic design based in part or in whole upon the set of cloning rules, configurations, or settings, without parsing the electronic design or a portion thereof.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing a floorplan with virtual hierarchies and figure groups for an electronic design. These techniques identify a plurality of layout circuit component designs in a layout and identify or create a figure group at a virtual hierarchy for the plurality of layout circuit component designs. The figure group can be modified into a modified figure group in response to a request for a modification of the figure group. At least one layout circuit component design of the plurality of layout circuit component designs can then be reinstalled into the modified figure group to fulfill the request for modification of the figure group.

Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

Abstract: A method for determining a sparse Gaussian process model to be carried out in a solely hardware-based model calculation unit includes: providing supporting point data points, a parameter vector based thereon, and corresponding hyperparameters; determining or providing virtual supporting point data points for the sparse Gaussian process model; and determining a parameter vector Qy* for the sparse Gaussian process model with the aid of a Cholesky decomposition of a covariant matrix KM between the virtual supporting point data points and as a function of the supporting point data points, the parameter vector based thereon, and the corresponding hyperparameters, which define the sparse Gaussian process model.

Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

Abstract: Methods and systems for dynamic real-time overlay include identifying positional and dimensional characteristics of an image of a device under test (DUT). Characteristics of the image are correlated with a design layout of the DUT using a processor to determine a size, field of view, and position for the design layout to match the image. The design layout and the image are overlayed, such that both are superimposed and visible simultaneously.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine whether module instances of a register level circuit design share a common usage, each instance being associated with a mapping. Two instances share a common usage if a sequence of signal transition representations received by the first instance can be mapped using a first mapping to the same common sequence of signal transition representations as a mapping of another sequence of signal transition representations received by the second instance using a second mapping. A result sequence of signal transition representations was generated by a previous propagation of the common sequence through the common usage. If the two instances share the common usage, the result sequence is mapped to an output sequence for the second instance using the second mapping.

Abstract: A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature of the data representative of the subcomponent and determining a difference of the current signature and the banked signature.

Abstract: A method for equivalence checking includes obtaining a first and a second representation for a semiconductor design and applying a set of inputs to both representations. The outputs of the first representation are compared to the outputs of the second representation. If a mismatch is found, the starting states for the first and second representations are evaluated using a model checker to see if they are reachable from a known legal state such as reset state for that representation. If both of the starting states are reachable, the mismatch is a real mismatch providing a counter-example of the equivalence of the two representations. If one or both of the starting states are unreachable, the mismatch is a spurious mismatch and the model checker can be used to generate an invariant to preclude those starting states in future iterations of the equivalence checker.

Abstract: This application discloses an electronic design automation tool configured to identify combinational loops in a word-level netlist, and then modify the word-level netlist based on the presence of the combinational loops. The electronic design automation tool can analyze the word-level netlist to identify a portion of the word-level netlist having at least one characteristic associated with a combinational loop, translate the identified portion of the word-level netlist into a bit-level circuit representation, and utilize the bit-level circuit representation to determine whether the identified portion of the word-level netlist implements the combinational loop. The electronic design automation tool can modify the word-level netlist by replacing the identified combination loop in the word-level netlist with a description of a different circuit, such as a loop buffer, or annotate the presence of the identified combinational loop in the word-level netlist.

Abstract: One exemplary process for animating hair includes receiving data representing a plurality of hairs and a plurality of objects in a timestep of a frame of animation. A first tree is populated to represent kinematic objects of the plurality of objects and a second tree is populated to represent dynamic objects of the plurality of objects based on the received data. A first elasticity preconditioner is created to represent internal elastic energy of the plurality of hairs based on the received data. Based on the first tree and the second tree, a first set of potential contacts is determined between two or more hairs of the plurality of hairs or between one or more hairs of the plurality of hairs and one or more objects of the plurality of objects. Positions of the plurality of hairs are determined based on the first set of potential contacts and the first elasticity preconditioner.

Abstract: A method, system or computer usable program product for model checking a first circuit model including determining whether the first circuit model is functionally equivalent to one of a set of prior circuit models stored in persistent memory, and in response to determining functional equivalence, utilizing a processor to provide test results for the functionally equivalent prior circuit model.

Abstract: A device receives a conflicted file, with a structured data format, that includes a conflict marker that does not comply with the structured data format. The conflict marker identifies first edited information and second edited information included in the conflicted file. The first edited information and the second edited information comply with the structured data format, and include information that has been modified in different versions of a shared file to create the conflicted file. The device detects that the conflicted file includes the conflict marker, and identifies, based on the detected conflict marker, the first edited information and the second edited information. The device determines that at least one of the first edited information or the second edited information is to be provided to the application for processing, and provides, based on the determining, the first edited information or the second edited information to the application for processing.

Abstract: A switching module can route packets between a network fabric and a local network, both of which form a closed network such as a vehicular network. The switching module provides local network management functions, and handles packet transfers between the local network and the network fabric. The switching module uses network information, which can include information about packet content type and network topology, to determine a packet's priority, and an appropriate switching protocol to use for processing and routing packets.

Abstract: Systems, methods, and apparatus for modeling and analyzing a physical system comprising a plurality of components. In some embodiments, a component type of a component of the plurality of components may be used to access a dataset from a plurality of datasets. The dataset may include a representation of at least one partial differential equation. A model of the component may be constructed based at least in part on the accessed dataset and at least one parameter relating to a physical characteristic of the component, and may be used to compute at least one output value based on at least one input value.

Abstract: A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.

Abstract: One method implementation disclosed includes detecting matching leaf cells that have functionally identical designs (optionally, similar designs) and assigning matching names for the matching leaf cells to replace original, non-matching names. Optionally, digests can be calculated for the leaf cells and used to detect similarities and/or differences. The matching names are propagated to at least some higher-level cells in the hierarchical design, in place of the original names. The method can further include calculating digests for at least some of the higher level cells after the propagating of the matching names into the higher level cells. Various design matching technologies can be used in combination with cell renaming and new name propagation, not limited to use of digests. Dependency chains can be calculated to improve propagation of names through the hierarchy.

Abstract: In particular embodiments, a method includes accessing a first binary decision diagram (BDD) representing data streams from sensors, selecting portions from the first BDD, constructing a second BDD representing the selected portions and a third BDD representing the non-selected portions, determining sizes of the first, second, and third BDDs, and if the size of the first BDD is less than a sum of the sizes of the second and third BDDs, then storing the first BDD, else storing the second and third BDDs.

Abstract: A diagnosis device including a storage unit configured to store first circuit configuration information, a circuit unit configured to configure a first plurality of circuits based on the first circuit configuration information and a second plurality of circuits based on second circuit configuration information, and a processor configured to update the first circuit configuration information to the second circuit configuration information and configured to diagnose all circuits newly added by the second circuit configuration information of the second plurality of circuits.

Abstract: In one or more embodiments, a caching apparatus includes functionality to persist evaluation results associated with pcells in a design across sessions of an EDA application as well as across design libraries. The caching apparatus may create and maintain a mirror cache in a design library with only subMasters referenced by the design library. The contents of a central cache file or a mirror cache in the design library are examined for an evaluation result. If the evaluation result is not found in the central cache file, the evaluation result may be retrieved from the mirror cache if present.

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.

Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.