Abstract: The junction comprising a stack of at least two magnetic layers, a first layer, for example a soft magnetic layer with controllable magnetization, and a second layer, for example a hard magnetic layer with fixed magnetization, the magnetization of the soft layer being described by a uniform magnetic moment, the dynamic behavior of the junction being modeled by an equivalent electrical circuit comprising at least two coupled parts: a first part representing the stack of the layers, through which a current flows corresponding to the polarized current flowing through said layers whose resistance across its terminals depends on three voltages representing the three dimensions of the magnetic moment along three axes, modeling the tunnel effect; a second part representing the behavior of the magnetic moment, comprising three circuits each representing a dimension of the magnetic moment by the three voltages, each of the three voltages depending on the voltages in the other dimensions and on the voltage across the t

Abstract: Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.

Abstract: This disclosure describes a method illustrated in FIG. 7 to prepare re-architected digital logic designs for sequential equivalence checking. This method initially begins with a description of an electrical design module that includes a plurality of ports, and a description of an electrical reference model that comprises a hierarchy of one or more reference modules where each said reference module comprises a plurality of internal signals. In addition, this method includes a configuration file with additional initial information. The method then processes 100 a configuration file. Then, the method 105 computes one or more output files. Finally, the method 110 writes the output files.

Abstract: In a method for increasing coverage convergence during verification of a design for an IC, symbolic elements can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Simulation semantics can be modified and local multi-path analysis can be provided to expand symbolic property collection and symbolic element propagation. Modifying simulation semantics can include transformation of conditional statements, flattening of conditions, avoidance of short circuiting logic, and/or symbolic triggering of events. Symbolic elements are propagated through the design and the test bench during multiple simulation runs to collect symbolic properties. Coverage information from the multiple simulation runs is analyzed to identify coverage points to be targeted. For each identified coverage point, the constraints resulting from the collected symbolic properties are solved to generate directed stimuli for the design.

Abstract: A method and system for sub-circuit pattern recognition in integrated circuit design is disclosed. In one embodiment, a method for recognizing a pattern circuit in a target circuit, includes encoding the pattern circuit and the target circuit by processing a first netlist of the pattern circuit and a second netlist of the target circuit, generating a cross-linked data structure based on attributes and connectivity information of at least two devices and at least one net from the first netlist, and identifying an instance of the pattern circuit in the target circuit based on an associative mapping between the pattern circuit and a sub-circuit of the target circuit using a device integer array and a net integer array. Each of the first netlist and the second netlist is based on the at least two devices and the at least one net connecting the at least two devices.

Abstract: Differences between block interfaces of a partitioned logic block in two floorplans of an integrated circuit can be determined by comparing an image of pins of a partitioned logic block in a first floorplan of the integrated circuit with an image of pins of the partitioned logic block in a second floorplan of the integrated circuit. The second floorplan can represent a new floorplan design resulting from a change to an integrated circuit design represented by the first floorplan. If no differences exist between pins of the partitioned logic block in the first and second floorplans, information representing the partitioned logic block in the second floorplan can be substituted with information representing the partitioned logic block in the first floorplan.

Abstract: A method of forming a device is disclosed. The method includes providing at least one original artwork file having front end and back end information. The original artwork file includes an original artwork file format. A modified artwork file corresponding to the original artwork file is provided in a first modified artwork file format. The modified artwork file contains back end information. The method also includes checking to ensure that the original and modified artwork files are consistent.

Abstract: A method for preparing an IC design that has been modified to be formally verified with a reference IC design. Because some formal verification tools cannot handle the complexity often associated with sequential equivalence checking at the top level of a circuit, the modified IC design may be instantiated into a number of different design versions, each having different levels of modification complexity. In addition, the reference IC design and the modified versions may be decomposed into a datapath and control path. The reference IC design and each of the modified IC design versions may also use wrappers to encapsulate various levels of hierarchy of the logic. Lastly, rather than having to verify each of the modified versions back to the reference IC design, the equivalence checking may be performed between each modified IC design version and a next modified IC design version having a greater modification computational complexity.

Abstract: A logic verification apparatus for verifying a logic circuit includes a line recognition unit that recognizes signal lines in the circuit based on design information regarding the circuit as a starting point; a decoder recognition unit that recognizes an area including an AND gate that outputs a certain logical value and an inverter as a decoder circuit area based on the design information, and determines a logical value of an input signal inputted to the recognized decoder circuit area when a logical value of the starting point has a specific logical value; and a determination unit that determines whether a logical configuration of the recognized decoder circuit area is correct based on the number of input signals and a combination of logical values of input signals between the recognized decoder circuit areas.

Abstract: A method for verifying functional equivalence between a reference integrated circuit (IC) design and a modified version of the reference IC design includes simulating a reference IC design using a simulation stimulus on a test bench and saving the simulation output. The reference IC design corresponds to an IC design model having visibility to comprehensive internal device state. The method may also include simulating a modified version of the reference IC design using the same simulation stimulus on the same test bench, and saving the modified version simulation output. In addition, the simulation outputs of the reference IC design and the modified version are compared to create a comparison result. Lastly, the method may include determining whether the modified version of the reference IC design is functionally equivalent to the reference IC design based upon the comparison result.

Abstract: A computer-readable recording medium stores a design support program causing a computer to perform: detecting a data path and a clock path corresponding to the data path making up a partial circuit in a circuit-under-design; selecting an object cell from cells on the data path and the clock path detected in the detecting; replacing the object cell selected in the selecting with a cell having a function substantially identical to and characteristics different from the object cell; acquiring a plurality of types of characteristic information related to the partial circuit based on the data path and the clock path after the object cell is replaced in the replacing; determining whether the types of the characteristic information acquired in the acquiring is in violation of restrictions; and outputting a determination result determined in the determining.

Abstract: An electronic design automation (EDA) tool to validate representations of a design is disclosed. Reference and compared representations of the design are intended to respond to stimulus in the same way, but at different levels of abstraction. The reference and compared representations are simulated, at some point, to each generate waveform signals and measured results. Simulation can be with the same tool or different tools. The same or different testbench can be used on the reference and compared representations in the simulation. A design representation validation function compares the two sets of generated waveform signals and compares the two sets of measured results to identify any violations. The measured results and/or waveform signals could be loaded from previous simulations and just validated within the validation tool.

Abstract: One embodiment of a method for verifying functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating includes selecting a first one of a first plurality of internal state elements in the design and a corresponding first one of a second plurality of internal state elements in the clock-gated design, wherein an input to the first one of the first plurality of internal state elements serves as a first comparison point and an input to the corresponding first one of the second plurality of internal state elements serves as a second comparison point, and the design is to be compared against the clock-gated design at the first comparison point and the second comparison point and generating a test bench that identifies the first comparison point and the second comparison point as a set of comparison points.

Abstract: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.

Abstract: A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.

Abstract: Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.

Abstract: Methods and systems are provided for reducing an original circuit design into a simplified circuit design by merging gates that may not be equivalent but can be demonstrated to preserve target assertability with respect to the original circuitry design. A composite netlist is created from the simplified netlist and the original netlist. The composite netlist includes a number of targets that imply the existence of a target in the simplified netlist and a corresponding target in the original netlist. The implications are verified and then validated to ensure the simplified circuit design is a suitable replacement for the original circuit design.

Abstract: Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.

Abstract: A mechanism is provided for simplifying a netlist before computational resources are exceeded. For each of a set of suspected equivalences in a proof graph of a netlist, a determination is made as to whether equivalence holds for at least one of an equivalence or an equivalence class by identifying whether the equivalence or equivalence class is either affecting or non-affecting. Responsive to the equivalence or equivalence class being affecting, a proof dependency is recorded as an edge in a proof graph. For each node in the proof graph, a determination is made as to whether the node has a falsified dependency. Responsive to the node failing to have a falsified dependency, identification is made that all dependencies are satisfied and that the equivalences represented by the node in the proof graph are sequential equivalences. The netlist is then simplified by consuming the sequential equivalences.

Abstract: A circuit design supporting apparatus includes: an observation portion specifying section configured to specify a first portion with a high improvement effect of analysis easiness in failure analysis of an integrated circuit as an observation portion; and an element substitution performing section configured to substitute an element arranged in the observation portion by an analysis target element to which a failure analysis apparatus can appropriately conduct the failure analysis based on a data of the observation portion.

Abstract: Methods and systems initiate a simulation of an integrated circuit design. The simulation produces data that will exist in latches of the integrated circuit design when a device manufactured according to the integrated circuit design is operating. The methods and systems evaluate same-state latches associated with different portions of the simulation. If two of the same-state latches have the same state, given the same inputs and environmental conditions, the method and systems terminate a first portion of the simulation associated with a first of the same-state latches, but allow a second portion of the simulation associated with a second of the same-state latches to proceed.

Abstract: Systems and methods for mapping state elements of digital circuits for equivalence verification are provided.

Abstract: In a first aspect, a first method of designing a circuit is provided. The first method includes the steps of (1) providing a model of an original circuit design including a latch; (2) providing a model of a modified version of the original circuit design, wherein the modified version of the original circuit design includes a set of latches associated with the latch of the original circuit design and voting logic having inputs coupled to respective outputs of latches in the latch set; and (3) during Boolean equivalency checking (BEC), injecting an error on at most a largest minority of the inputs of the voting logic to test the voting logic function.

Abstract: A method of producing a hierarchical power information structure for a circuit design, the method comprising traversing a circuit design hierarchy from a top design level to a bottom design level to identify any intermediate design levels, associating identified power nets with ground nets to produce one or more power domains, producing one or more power domains using the identified power nets and ground nets, identifying an instance of one or more special cells that are associated with a power related property and creating constructs for the special cells in the hierarchical power information structure, generating power rules for the intermediate level design using the special cell constructs, mapping higher design level power domains to lower design level power domains within the intermediate design level, and storing the power domains and power rules as power intent within an information structure associated with a schematic for the intermediate level design.

Abstract: A computer-readable, non-transitory medium stores therein a verification support program that causes a computer to execute a procedure. The procedure includes first detecting a state change in a circuit and occurring when input data is given to the circuit. The procedure also includes second detecting a state change in the circuit and occurring when the input data partially altered is given to the circuit. The procedure further includes determining whether a difference exists between a series of state changes detected at the first detecting and a series of state changes detected at the second detecting. The procedure also includes outputting a determination result obtained at the determining.

Abstract: This invention provides a system and method for correcting gate-level simulation commences by identifying unknown values (Xs) that are falsely generated during the simulation of a given trace for a design netlist. Then, a sub-circuit of the design netlist is determined for each false X that has inputs of real Xs and an output of a false X. Finally, simulation correction code is generated based on the sub-circuit to eliminate false Xs in simulation of the design netlist. The original design netlist can then be resimulated with the simulation repair code to eliminate false Xs. This allows gate-level simulation to produce correct results.

Abstract: A mechanism is provided for verifying a register-transfer level design of an execution unit. A set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system. The result checker compares the two results and, responsive to a mismatch in the results, a failure of the test case is indicted, the verification of the test case is stopped, and all data associated with the test case is output from the buffer for analysis.

Abstract: A method for determining simultaneous switching noise for multiple Input/Output (I/O) standards is provided by calculating incremental noise for the multiple I/O standards by considering a cumulative amount of noise contributed by previously assigned pins. In another embodiment, the number of pins being placed is considered rather than the cumulative amount of noise. When considering the cumulative amount of noise the I/O noise from corresponding I/O standards are characterized and a greater contributor is identified so that the I/O standard associated with the greater contributor can be assigned.

Abstract: According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the layout-versus-schematic errors, generates a graphical representation of the layout netlist and a graphical representation of the schematic netlist, displays an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist and then, highlights the identified layout-versus-schematic errors that are present.

Abstract: A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.

Abstract: A method is provided for identifying use of a proprietary circuit layout. A representation of a layout of a circuit is input and the locations of a set of predetermined physical features of the circuit are identified. This set of locations is then compared with a previously generated characteristic pattern file, the characteristic pattern file comprising a representation of relative locations of a set of these predetermined physical features in the proprietary circuit layout. If the set of locations matches the relative locations of the characteristic pattern file, then an output is generated indicating that use of the proprietary circuit design has been found.

Abstract: A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.

Abstract: In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Exemplary hardware code can include the hardware description language (HDL) code and/or the hardware verification language (HVL) code. Symbolic properties, which are derived from propagating the symbolic variables and symbolic expressions through the design and the test bench during the multiple simulation runs, can be collected. Coverage information from the multiple simulation runs can be analyzed to identify coverage points to be targeted. At this point, for each identified coverage point, the constraints resulting from the collected symbolic properties can be solved to generate directed stimuli for the design. These directed stimuli can increase the coverage convergence.

Abstract: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.

Abstract: This invention (900) described a method that generates and uses a test bench for verifying an electrical design module in a semiconductor manufacturing against an electrical reference model containing a sub-circuit that matches the electrical design module. The invention includes providing (902) a description of an electrical design module that includes a plurality of ports. In addition, the invention includes providing (904) a description of an electrical reference model. The invention further includes providing and or creating (92) one or more implicit defines for the reference modules that appear in hierarchy of the electrical reference model. And, the invention includes providing (906) a description file that includes one or more instance definitions. The invention parses (91) the hierarchy of the electrical design model and then processes (96) the description file. The invention then writes (97) the test bench.

Abstract: Two circuits, an original and a modified, are being recognized, with the original circuit having a first logic and the modified circuit having a second logic. The second logic contains at least one desired logic change relative to the first logic. An equivalence line is detected in the original circuit such that the first and second logic are equivalent from the circuit inputs to the equivalence line. At least one point of change is located amongst the logic gates that are neighboring the equivalence line. The points of change are accepted as verified if an observability condition is fulfilled. The observability condition is checked within a Boolean Satisfiability (SAT) formulation. Substitute logic for the verified points of change is derived using SAT and Boolean equation solving techniques, in such manner that the first logic becomes equivalent to the second logic.

Abstract: In one embodiment, the invention is a moment-based characterization waveform for static timing analysis. One embodiment of a method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform includes using a processor to perform steps including: computing one or more moments of the timing waveform and defining the characterization waveform in accordance with the moments.

Abstract: A method for formally verifying the equivalence of an architecture description with an implementation description. The method comprises the steps of reading an implementation description, reading an architecture description, demonstrating that during execution of a same program with same initial values an architecture sequence of data transfers described by the architecture description is mappable to an implementation sequence of data transfers implemented by the implementation description, such that the mapping is bijective and ensures that the temporal order of the architecture sequence of data transfers corresponds to the temporal order of the implementation sequence of data transfers, and outputting a result of the verification of the equivalence of the architecture description with the implementation description.

Abstract: With various implementations of the invention, test sequences are generated using a pairwise methodology. The generated test sequences are checked using a constraint solver to determine if the test sequences satisfy a set of constraints. In some implementations, the uncovered pairs for a particular input are checked using the constraint solver to determine if any pairs violate the constraints. Any pairs found to violate the constraints can be excluded from the test set. With some implementations, the uncovered pairs are sorted such that the sum of every three consecutive elements is odd.

Abstract: A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

Abstract: A method, computer program product, and apparatus for processing a wiring diagram is provided. Information associated with a number of components in the wiring diagram is identified. A scaling factor between a first format for the wiring diagram and a second format used by a software application configured to use wiring diagrams in the second format is identified. The scaling factor is applied to the information identified as being associated with the number of components in the wiring diagram to form processed information.

Abstract: A method, system, and computer program product are disclosed for generating a pattern signature to represent a pattern in an integrated circuit design. In one approach, the method, system and computer program product transform pattern data, two dimensional data for the pattern, into a set of one dimensional mathematical functions, compress the set of one dimensional mathematical functions into a single variable function, compress the single variable function by calculating a set of values for the single variable function, and generate a pattern signature for the pattern from the set of values.

Abstract: A method and system are provided for optimizing migrated implementation of a system design. In certain applications, a source hierarchical structure system and a target hierarchical structure system are provided, the hierarchy is abstracted out, intrinsic parameters are encoded and compared between source hierarchical structure and target hierarchical structure to arrive at an optimized change order list for transforming/migrating the source hierarchical structure system to the target hierarchical structure system.

Abstract: A design verification method is disclosed. A computer searches for a path in accordance with a connection relationship between blocks by referring to a netlist stored in a storage part based on terminal information concerning a verification of a circuit which is formed by the blocks. Then, the computer changes an abstraction level of an operation of an out-of-path block which is a block outside the path and is searched for from the blocks described in the netlist.

Abstract: Methods of modeling a transistor are provided. The method includes the steps of (a) extracting reference mobility values of a channel layer of a transistor including a gate electrode, a source region and a drain region using a reference gate voltage, a reference drain current and a reference drain voltage, (b) fitting a mobility function including model parameters on the reference mobility values to extract the model parameters, and (c) putting the extracted model parameters into a drain current modeling function to calculate a drain current flowing through the channel layer between the drain region and the source region under a bias condition defined by an arbitrary gate voltage applied to the gate electrode and an arbitrary drain voltage applied to the drain region. Related apparatuses are also provided.

Abstract: A method, system, and computer program product for improved model checking for verification of a state transition machine (STM) are provided. A hardware design under test and a property to be verified are received. A level (k) of induction proof needed for the verification is determined. A circuit representation of the property using the hardware design under test for k base cases is configured for checking that the circuit representation holds true for the property for each of the k base cases, and for testing an induction without hypothesis by testing whether the property holds true after k clock cycles starting from a randomized state, where induction without hypothesis is performed by omitting a test whether the property holds true for the next cycle after the property holds for k successive cycles. The induction proof of the property using the hardware design under test by induction without hypothesis is produced.

Abstract: A method, system, and computer program product for verification of a state transition machine (STM) are provided in the illustrative embodiments. The STM representing the operation of a circuit configured to perform a computation is received. A segment of the STM is selected from a set of segments of the STM. A set of properties of the segment is determined. The set of properties is translated into a hardware description to form a translation. The segment is verified by verifying whether all relationships between a pre-condition and a post condition in the translation hold true for any set of inputs and any initial state of a hardware design under test. A verification result for the segment is generated. Verification results for each segment in the set of segments are combined to generate a verification result for the STM.

Abstract: An electronic device and method for inspecting electrical rules of circuit boards includes selecting at least two design files that record electrical rules of the circuit boards and searching the electrical rules in the selected design files using preset parameter keywords. Same electrical rules of the selected design files are acquired by comparing the electrical rules in the selected design files. The same electrical rules and corresponding parameter values are input to a comparison table, and the comparison table is output.

Abstract: A mechanism is provided for simplifying a netlist before computational resources are exceeded. For each of a set of suspected equivalences in a proof graph of a netlist, a determination is made as to whether equivalence holds for at least one of an equivalence or an equivalence class by identifying whether the equivalence or equivalence class is either affecting or non-affecting. Responsive to the equivalence or equivalence class being affecting, a proof dependency is recorded as an edge in a proof graph. For each node in the proof graph, a determination is made as to whether the node has a falsified dependency. Responsive to the node failing to have a falsified dependency, identification is made that all dependencies are satisfied and that the equivalences represented by the node in the proof graph are sequential equivalences. The netlist is then simplified by consuming the sequential equivalences.

Abstract: A mechanism is provided for simplifying a netlist before computational resources are exceeded. For each of a set of suspected equivalences in a proof graph of a netlist, a determination is made as to whether equivalence holds for at least one of an equivalence or an equivalence class by identifying whether the equivalence or equivalence class is either affecting or non-affecting. Responsive to the equivalence or equivalence class being affecting, a proof dependency is recorded as an edge in a proof graph. For each node in the proof graph, a determination is made as to whether the node has a falsified dependency. Responsive to the node failing to have a falsified dependency, identification is made that all dependencies are satisfied and that the equivalences represented by the node in the proof graph are sequential equivalences. The netlist is then simplified by consuming the sequential equivalences.