Equivalence Checking Patents (Class 716/107)
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Publication number: 20150143308Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. At least one of the violation monitors comprises a violation information detector and a threshold controller. The violation information detector is arranged to detect one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determine information representing the respective violation, wherein detecting the one or more violations comprises comparing a simulated parameter against a threshold. The threshold controller is arranged to determine the threshold for the respective violation rule in dependence on a temporal characteristic of the associated violation.Type: ApplicationFiled: September 13, 2012Publication date: May 21, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Mehul Shroff, Peter Abramowitz, Xavier Hours
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Patent number: 9038010Abstract: The present disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer databases for a plurality of tiers within a multi-tiered integrated chip. The layer databases respectively identify design layers within an associated tier. A DRC (design rule checking) deck is then generated, which defines one or more individual design layer definitions as a function of a plurality of layer databases, so that the one or more individual design layer definitions are defined for a plurality of tiers. One or more design rules for the one or more individual design layer definitions are defined within the DRC deck. Since the individual design layer definitions are defined as functions of the plurality of layer databases, the design rules apply to the plurality of tiers.Type: GrantFiled: October 21, 2013Date of Patent: May 19, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yao-Jen Chuang, Nien-Yu Tsai, Wen-Ju Yang
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Patent number: 9038007Abstract: A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.Type: GrantFiled: February 3, 2012Date of Patent: May 19, 2015Assignee: Altera CorporationInventors: Peter Boyle, Iliya G. Zamek
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Patent number: 9032346Abstract: Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.Type: GrantFiled: May 19, 2011Date of Patent: May 12, 2015Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Raymond A. Filippi, Paul Soh, Hui May Tan
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Patent number: 9032347Abstract: A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.Type: GrantFiled: May 3, 2013Date of Patent: May 12, 2015Assignee: Cadence Design Systems, Inc.Inventor: Donald J. O'Riordan
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Patent number: 9026964Abstract: A method for modeling a circuit comprising storing a plurality of design variable ranges for a circuit component in a non-transient electronic data memory. Performing transistor-level simulations at a plurality of sample points for the circuit component to generate a plurality of design variable samples for the circuit component. Storing a neural network architecture in the non-transient electronic data memory that models the plurality of design variable samples for the circuit component. Storing a performance metric metamodel and a circuit parameter metamodel generated using Verilog-AMS.Type: GrantFiled: March 12, 2014Date of Patent: May 5, 2015Assignee: University of North TexasInventors: Saraju P. Mohanty, Elias Kougianos, Geng Zheng
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Patent number: 9026979Abstract: An analysis support apparatus includes a processor that is configured to acquire circuit data that indicates plural elements within a circuit and a node to which at least two elements are connected among the elements, and determine, based on the acquired circuit data and by referring to a memory unit that correlates and stores for each of the elements, the type of the element and information that indicates whether the phase of a signal is reversed when the signal passes through the element, whether the phase of the signal is reversed when the signal that passed through a given node among a plurality of nodes within the circuit returns to the given node; and an output unit that outputs information that indicates the given node when the processor determines that the phase of the signal is not reversed.Type: GrantFiled: February 11, 2014Date of Patent: May 5, 2015Assignee: Fujitsu LimitedInventors: Hiroyuki Sato, Satoshi Matsubara
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Publication number: 20150121325Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation.Type: ApplicationFiled: May 31, 2012Publication date: April 30, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Xavier Hours, Pascal Caunegre, Christophe Oger, Mehul Shroff
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Patent number: 9021409Abstract: A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation data; extract domain-specific information about the design for variables of interest; execute a data mining algorithm with the simulation data and the domain-specific information, to generate a set of candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information, the candidate assertions being likely invariants; conduct formal verification on the design with respect to each candidate assertion by outputting as invariants the candidate assertions that pass verification; iteratively feed back into the algorithm a counterexample trace generated by each failed candidate assertion, each counterexample trace including at least one additional variable in the design not previously input into the data mining algorithm, to thus increase coverage of a state space of theType: GrantFiled: March 29, 2012Date of Patent: April 28, 2015Assignee: The Board of Trustees of the University of IllinoisInventors: Shobha Vasudevan, David Sheridan, Lingyi Liu
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Publication number: 20150106775Abstract: A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature of the data representative of the subcomponent and determining a difference of the current signature and the banked signature.Type: ApplicationFiled: December 3, 2014Publication date: April 16, 2015Inventors: MICHAEL KRASNICKI, YUE DENG
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Patent number: 9009635Abstract: A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.Type: GrantFiled: May 3, 2013Date of Patent: April 14, 2015Assignee: Cadence Design Systems, Inc.Inventor: Donald J. O'Riordan
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Patent number: 8997034Abstract: Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed.Type: GrantFiled: July 30, 2013Date of Patent: March 31, 2015Assignee: Synopsys, Inc.Inventors: Ying-Tsai Chang, Yu-Chin Hsu
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Patent number: 8997030Abstract: An approach is provided in which a model verification system partitions one of a design specification's circuit design properties into multiple unsolved cases. The model verification system then performs property checking on one of the unsolved cases against a corresponding circuit design model, which results in a property checked solved case and a subset of unsolved cases. In turn, the model verification system performs sequential equivalence checking on one or more of the subset of unsolved cases by checking their sequential equivalence against the property checked solved case. As a result, the model verification system stores the cases as sequentially equivalent solved cases and verifies of a portion of the design specification against a portion of the circuit design model.Type: GrantFiled: October 28, 2013Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Krishnan K. Kailas, Hari Mony
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Patent number: 8984459Abstract: Methods and apparatus of performing layout-versus-layout (LVL) comparison are disclosed. A layout may be in various formats such as GDSII or OASIS, for different circuits, and represented by a basic layout element, a hierarchical cell or a plurality of independent cells in various layers. A basic layout element, a hierarchical cell, and a layout with a plurality of independent cells may have a signature generated according to the embodiment methods. The signature of a basic layout element may be generated based on values of a center and a circumference, and a hashed trace value generated by a hash function of a trace of the basic layout element. The signature of a hierarchical cell can be generated recursively. A signature of a first layout may be compared to a signature of a second layout to determine whether the first layout matches the second layout.Type: GrantFiled: May 4, 2012Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Huang Chen, Yin-Chuan Chen
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Publication number: 20150074625Abstract: The verification apparatus for a semiconductor integrated circuit verifies a logic equivalence before and after modification to the circuit by replacing a memory with a divisional memory model that agrees with the memory in number of input and output pins and verifying logics at an input and an output thereof.Type: ApplicationFiled: March 10, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Naoyuki KAWABE, Tetsuaki UTSUMI
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Publication number: 20150074624Abstract: An approach is provided in which a model verification system partitions one of a design specification's circuit design properties into multiple unsolved cases. The model verification system then performs property checking on one of the unsolved cases against a corresponding circuit design model, which results in a property checked solved case and a subset of unsolved cases. In turn, the model verification system performs sequential equivalence checking on one or more of the subset of unsolved cases by checking their sequential equivalence against the property checked solved case. As a result, the model verification system stores the cases as sequentially equivalent solved cases and verifies of a portion of the design specification against a portion of the circuit design model.Type: ApplicationFiled: October 28, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: Krishnan K. Kailas, Hari Mony
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Publication number: 20150074626Abstract: A determining method includes obtaining terminal information indicating a first object terminal that is among terminals included among partial circuits and subject to determination of whether the first object terminal is an open terminal; obtaining for each terminal, connection information and first attribute information indicating an attribute of any one among an input terminal and an output terminal; generating, by a computer, for each terminal, second attribute information indicating an attribute opposite to the attribute indicated by the first attribute information; and determining, by the computer, whether a state of the first object terminal indicated by the terminal information becomes a high-impedance state, by simulating on the basis of the connection information and the second attribute information, a state of each terminal when a value of a terminal among the terminals and indicated as an output terminal by the second attribute information, is set at a first specified value.Type: ApplicationFiled: August 21, 2014Publication date: March 12, 2015Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Eiichi NIMODA, Natsumi Saito
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Publication number: 20150074627Abstract: A semiconductor device design method includes extracting voltage data associated with at least one electrical component in a layout of a semiconductor device and based on a result of a simulation of an operation of the semiconductor device. Based on location data of the at least one electrical component, the extracted voltage data is incorporated in the layout to generate a modified layout of the semiconductor device. One or more operations of the method are performed by at least one processor.Type: ApplicationFiled: November 13, 2014Publication date: March 12, 2015Inventors: Mu-Jen HUANG, Chih Chi HSIAO, Wei-Ting LIN, Tsung-Hsin YU, Chien-Wen CHEN, Yung-Chow PENG
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Patent number: 8977996Abstract: A design apparatus generates an optimal design condition by design space exploration. The apparatus including a source code parsing (301) which parses source code and generates a parse tree, a cluster generation task (302) which generates clusters based on the parse tree, each of the clusters including a group of source codes which can operate independently, a log file task (303) which generates a log file based on a structure of the cluster, and a comparison task (304) which compares a first log file of a previous cluster with a second log file of a current cluster and re-uses previous exploration result based on a comparison result, the first log file being obtained from a previous design space exploration, the second log file being generated from a current operation.Type: GrantFiled: October 28, 2010Date of Patent: March 10, 2015Assignee: NEC CorporationInventor: Benjamin Carrion Schafer
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Patent number: 8954908Abstract: A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy. Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis. Statistical device model variation is calculated as if all such variation is due to changes in threshold voltage, even though other physical phenomena are known to contribute. Threshold voltage variation is modeled as a function of statistical variation, device size, and working bias condition. Circuit simulation is faster when the full internal device model parameter set is not rebuilt for every Monte Carlo analysis iteration. Embodiments are compatible with both conventional SPICE and newer Fast SPICE simulations.Type: GrantFiled: July 10, 2013Date of Patent: February 10, 2015Assignee: Cadence Design Systems, Inc.Inventors: Hongzhou Liu, Jushan Xie, Michael Tian, An-Chang Deng
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Patent number: 8954909Abstract: A system and methods are provided for verifying a hardware design for an electronic circuit. The method may include: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in terms of signals and logical operations performed on the signals; creating an abstraction model from the set of design constraints, where the abstraction model abstracts one or more of the logical operations in the set of design constraints by replacing the abstracted logical operations with uninterpreted functions; and property checking the abstraction model in relation to one or more design properties. When a violation in the electronic circuit is detected by the property checking step, the feasibility of the violation is then checked and, if the violation is deemed infeasible, the abstraction model is refined.Type: GrantFiled: December 3, 2013Date of Patent: February 10, 2015Assignee: The Regents of the University of MichiganInventors: Zaher Andraus, Karem A. Sakallah, Mark Liffiton
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Publication number: 20150040086Abstract: A method for simulating a circuit includes running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit, and running a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype.Type: ApplicationFiled: July 31, 2014Publication date: February 5, 2015Inventors: Helena Krupnova, Yogesh Goel
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Patent number: 8943457Abstract: An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.Type: GrantFiled: November 24, 2008Date of Patent: January 27, 2015Assignee: NVIDIA CorporationInventors: Amit Dinesh Sanghani, Punit Kishore
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Patent number: 8935651Abstract: In one embodiment of the invention, a method of logic synthesis is disclosed. The method includes generating a plurality of design architecture alternatives for circuit logic of a data path cluster; saving the plurality of design architecture alternatives; and evaluating the plurality of design architecture alternatives in response to design constraints to select a preferred design architecture.Type: GrantFiled: December 28, 2007Date of Patent: January 13, 2015Assignee: Cadence Design Systems, Inc.Inventors: Tsuwei Ku, Samir Agrawal, Jean-Charles Giomi
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Publication number: 20150012899Abstract: A method for deriving an equivalent circuit model of a capacitor which makes it possible to derive, with high accuracy and with ease, an equivalent circuit model having characteristics in accordance with a direct current voltage applied to a capacitor. Characteristic values of predetermined resistive elements and capacitive elements forming an equivalent circuit model of a capacitor change in response to a DC bias voltage being applied to the capacitor, and the change is attributable to the material of a dielectric forming the capacitor. However, by multiplying the characteristic values of the resistive elements and the capacitive elements held while the DC bias voltage is not applied by a dimensionless coefficient in accordance with an application rule, the characteristic values of the resistive elements and the capacitive elements are corrected to values in accordance with the voltage of the DC bias voltage applied to the capacitor.Type: ApplicationFiled: September 19, 2014Publication date: January 8, 2015Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Seiji HIDAKA, Atsushi SAKURAGI
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Patent number: 8930864Abstract: A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts.Type: GrantFiled: October 3, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Debjit Sinha, Eric J. Fluhr, Stephen G. Shuma, Natesan Venkateswaran, Chandramouli Visweswariah, Michael H. Wood, Vladimir Zolotov
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Patent number: 8930862Abstract: A system, method, and computer program product for converting a design from edge-triggered docking to two-phase non-overlapping clocking is disclosed. The method includes the steps of replacing an edge-triggered flip-flop circuit that is coupled to a combinational logic circuit with a pair of latches including a first latch circuit and a second latch circuit and determining a midpoint of the combinational logic circuit based on timing information. The second latch circuit is propagated to a midpoint of the combinational logic circuit and two-phase non-overlapping clock signals are provided to the pair of latches.Type: GrantFiled: March 6, 2013Date of Patent: January 6, 2015Assignee: NVIDIA CorporationInventor: William J. Dally
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Patent number: 8924913Abstract: A method of displaying a schematic diagram of an integrated circuit design is disclosed. The integrated circuit design includes a plurality of logic blocks and the schematic diagram may include a plurality of connections between respective pairs or groups of the logic blocks. The method includes identifying a plurality of interconnect lines that is adapted to schematically illustrate the plurality of connections. Selected interconnect lines out of the plurality of interconnect lines is identified. Portions of the selected interconnect lines may be channeled through a global connection line on the schematic diagram. The global connection line may be a graphical line that spans from one edge of the schematic diagram to another.Type: GrantFiled: June 20, 2013Date of Patent: December 30, 2014Assignee: Altera CorporationInventors: Denis Chuan Hu Goh, Choi Phaik Chin, Goet Kwone Ong
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Patent number: 8924912Abstract: A computer-implemented method to debug testbench code of a testbench associated with a circuit design by recording a trace of call frames along with activities of the circuit design. By correlating and displaying the recorded trace of call frames, the method enables users to easily trace as execution history of subroutines executed by the testbench thereby to debug the testbench code. In addition, users can trace source code of the testbench code by using the recorded trace of call frames. Furthermore, users can debug the testbench code utilizing a virtual simulation, which is done by post-processing records of the virtual simulation stored in a database.Type: GrantFiled: July 30, 2013Date of Patent: December 30, 2014Assignees: Synopsys, Inc., Synopsys Taiwan Co., Ltd.Inventors: Chia-Ling Ho, Jian-Cheng Lin, Jencheng Wang
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Patent number: 8914758Abstract: A design is verified by using equivalence checking to compare a word-level description of the design to a bit-level description of the design. A word-level data flow graph (DFG) based on the word-level description and a bit-level DFG is obtained. Structural analysis is used to reduce the graphs and partition them into smaller portions for the equivalence checking. The analysis includes searching the bit-level DFG to find partial-product encoding and removing redundancy from the bit-level DFG. A reference model with architectural information from the bit-level DFG is created based on the word-level DFG. The reference model is reduced and equivalence checked against the bit-level DFG to determine if the word-level description is equivalent to the bit-level description.Type: GrantFiled: May 28, 2013Date of Patent: December 16, 2014Assignee: Synopsys, Inc.Inventors: Sudipta Kundu, Carl Preston Pixley
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Publication number: 20140359545Abstract: A design is verified by using equivalence checking to compare a word-level description of the design to a bit-level description of the design. A word-level data flow graph (DFG) based on the word-level description and a bit-level DFG is obtained. Structural analysis is used to reduce the graphs and partition them into smaller portions for the equivalence checking. The analysis includes searching the bit-level DFG to find partial-product encoding and removing redundancy from the bit-level DFG. A reference model with architectural information from the bit-level DFG is created based on the word-level DFG. The reference model is reduced and equivalence checked against the bit-level DFG to determine if the word-level description is equivalent to the bit-level description.Type: ApplicationFiled: May 28, 2013Publication date: December 4, 2014Applicant: Synopsys, IncInventors: Sudipta Kundu, Carl Preston Pixley
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Patent number: 8904320Abstract: A design description for verification includes a set of constraints on random variables within the design description. The set of constraints includes at least one multiplication constraint involving at least two random variables. A computer-based tool obtains designs and analyzes the design description to find the set of constraints and identify the multiplication constraint. The computer-based tool then performs factorization to solve for the multiplication constraint and to determine a set of potentially valid factoring values for the random variables used in the multiplication constraint. The design problem is then solved by the computer-based tool using the factoring values. If two multiplication constraints involve a common variable, the factorization finds a set of common factoring values between the two multiplication constraints to use for the common variable.Type: GrantFiled: March 13, 2013Date of Patent: December 2, 2014Assignee: Synopsys, Inc.Inventors: Vijay Anand Korthikanti, Dhiraj Goswami
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Patent number: 8904321Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, using at least one computing device, an electronic design and associating, using the at least one computing device, one or more identifiers with each constraint solver call utilized in a simulation of the electronic design. The method may further include automatically generating, using the at least one computing device, a coverage model for one of more constraints associated with the electronic design, the coverage model being based upon, at least in part, the one or more identifiers.Type: GrantFiled: November 6, 2012Date of Patent: December 2, 2014Assignee: Cadence Design Systems, Inc.Inventors: Daniel Asher Cohen, John LeRoy Pierce, Petr William Spacek
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Patent number: 8893069Abstract: A computer-implemented method is disclosed for layout pattern or layout constraint reuse by identifying sub-circuits with identical or similar schematic structure based on a topology comparison strategy. The selected sub-circuit is transformed into a topology representing the relative positions among the instances of the selected sub-circuit. Based on the topology, one or more sub-circuits with identical or similar topologies in a predefined scope of a schematic are recognized and identified. Accordingly, the layout or the layout constraint of the selected sub-circuit is copied and associated to each of the identified sub-circuits. Furthermore, once the sub-circuits are identified, they can be listed on a user interface with notations to allow users to confirm each of the identified sub-circuits respectively.Type: GrantFiled: October 6, 2012Date of Patent: November 18, 2014Assignees: Synopsys, Inc., Synopsys Taiwan Co., Ltd.Inventors: Yu-Chi Su, Ming-I Lai, Hsiao-Tzu Lu
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Patent number: 8893066Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.Type: GrantFiled: December 27, 2012Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Sheng Chen, Tsun-Yu Yang, Wei-Yi Hu, Tao Wen Chung, Jui-Feng Kuan, Yi-Kan Cheng
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Patent number: 8887112Abstract: A computer-implemented method, computerized apparatus, and computer program product for test validation planning. The computer-implemented method, performed by a processor, comprising: having a test validation activity to be performed to validate results of two or more tests of a test suite; and automatically determining, by a processor, a subset of the two or more tests for which to perform the test validation activity; whereby avoiding performing duplicate validation activities. Optionally, for each test of the test suite a valuation of a set of functional attributes is available, and a subset of the functional attributes is deemed as relevant functional attributes with respect to the test validation activity. In such an embodiment, said determining is based on the valuation of the relevant functional attributes.Type: GrantFiled: November 14, 2012Date of Patent: November 11, 2014Assignee: International Business Machines CorporationInventors: Rachel Tzoref-Brill, Itai Segall, Aviad Zlotnick
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Patent number: 8881074Abstract: A tool for rewriting hardware design hardware design language (HDL) code is arranged for receiving HDL code (2) expressing a hardware design of a digital circuit. The tool comprises means (4) for generating a representation (6) of the syntax of the received HDL code, the representation containing a plurality of nodes. The tool further comprises means (3) for determining modifications to the representation of the syntax whereby at least one node is added to or removed from the representation and computation means (9) for generating a modified version (10) of the received HDL code using the received HDL code and modifications to the received HDL code, the modifications determined from the modified representation of the syntax.Type: GrantFiled: October 12, 2009Date of Patent: November 4, 2014Assignee: Sigasi NVInventors: Philippe Paul Henri Faes, Hendrik Richard Pieter Eeckhaut
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Patent number: 8881078Abstract: A method is provided for identifying use of a proprietary circuit layout. A representation of a layout of a circuit is input and the locations of a set of predetermined physical features of the circuit are identified. This set of locations is then compared with a previously generated characteristic pattern file, the characteristic pattern file comprising a representation of relative locations of a set of these predetermined physical features in the proprietary circuit layout. If the set of locations matches the relative locations of the characteristic pattern file, then an output is generated indicating that use of the proprietary circuit design has been found.Type: GrantFiled: February 6, 2013Date of Patent: November 4, 2014Assignee: ARM LimitedInventors: Albert Li Ming Ting, Shun-Piao Su
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Patent number: 8881075Abstract: An assertion-based verification tool for circuit designs includes an effective measurement of assertion density for any given generated set of assertions. A register-transfer level (RTL) description of an integrated circuit (IC) is used to compute a set of predicates. Then, determination is made as to the number of predicates that are satisfiable on the given set of assertions received respective of the RTL description. Thereafter, simulation traces for the RTL are received and the number of predicates satisfiable on the simulation traces is computed. A figure of merit of assertion density is determined from the ratio of the respective numbers of predicates. The set of assertions may be modified as required to satisfy a predetermined threshold value of assertion density, to assure that a circuit is rigorously tested by the verification tool.Type: GrantFiled: March 4, 2013Date of Patent: November 4, 2014Assignee: Atrenta, Inc.Inventors: Yuan Lu, Yong Liu, Nitin Mhaske
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Publication number: 20140317584Abstract: A method for formal fault detection in a design model includes providing a plurality of faults which are individually activatable in the design model, and providing a plurality of properties for the design model wherein each property of the plurality of properties is valid if none of the plurality of faults is activated. The method further includes selecting a property of the plurality of properties, and determining, by a formal property checker, whether activation of one fault of the plurality of faults causes the selected property to fail. If the formal property checker finds a particular fault which, when activated, causes the selected property to fail, determining that the selected property is capable to detect the particular fault, and if the formal property checker does not find any particular fault which, when activated, causes the selected property to fail, determining that the selected property is not capable to detect any fault of the plurality of faults.Type: ApplicationFiled: April 23, 2013Publication date: October 23, 2014Inventor: Holger Busch
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Patent number: 8850374Abstract: A method of reducing parasitic mismatches comprises generating a first net list file from a first layout through a resistance-inductance-capacitance (RLC) extraction mechanism using a first simulation tool, performing a V/I test on a network through a second simulation tool, determining whether a mismatch exists based upon a result of the V/I test and modifying a connection trace of the network to generate a second layout.Type: GrantFiled: November 6, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Char-Ming Huang, Hui-Yu Lee
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Publication number: 20140282316Abstract: A design description for verification includes a set of constraints on random variables within the design description. The set of constraints includes at least one multiplication constraint involving at least two random variables. A computer-based tool obtains designs and analyzes the design description to find the set of constraints and identify the multiplication constraint. The computer-based tool then performs factorization to solve for the multiplication constraint and to determine a set of potentially valid factoring values for the random variables used in the multiplication constraint. The design problem is then solved by the computer-based tool using the factoring values. If two multiplication constraints involve a common variable, the factorization finds a set of common factoring values between the two multiplication constraints to use for the common variable.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: SYNOPSYS, INC.Inventors: Vijay Anand Korthikanti, Dhiraj Goswami
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Patent number: 8839165Abstract: Methods determine temperature and voltage relationships for integrated circuit library elements to produce a continuous temperature-voltage function. Some of the library elements can be used or combined to form an integrated circuit design. Further, the performance characteristics for integrated circuit chips produced according to the integrated circuit design can be defined, such performance characteristics include an operating temperature range, etc. The continuous temperature-voltage function is applied to the performance characteristics to determine a plurality of temperature/voltage combinations for the integrated circuit chips. Each of the temperature/voltage combinations comprises an operating voltage for each operating temperature within the operating temperature range of the integrated circuit chips. Next, the integrated circuit chips are produced according to the integrated circuit design. The temperature/voltage combinations are recorded in memory of the integrated circuit chips.Type: GrantFiled: January 25, 2013Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Jeanne P. Bickford, Eric A. Foreman, Mark W. Kuemerle, Susan K. Lichtensteiger
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Patent number: 8832638Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.Type: GrantFiled: February 28, 2013Date of Patent: September 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Jeong, Chang-Woo Ko, Ki-Jae Song, Hun-Kyo Seo
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Publication number: 20140250414Abstract: An assertion-based verification tool for circuit designs includes an effective measurement of assertion density for any given generated set of assertions. A register-transfer level (RTL) description of an integrated circuit (IC) is used to compute a set of predicates. Then, determination is made as to the number of predicates that are satisfiable on the given set of assertions received respective of the RTL description. Thereafter, simulation traces for the RTL are received and the number of predicates satisfiable on the simulation traces is computed. A figure of merit of assertion density is determined from the ratio of the respective numbers of predicates. The set of assertions may be modified as required to satisfy a predetermined threshold value of assertion density, to assure that a circuit is rigorously tested by the verification tool.Type: ApplicationFiled: March 4, 2013Publication date: September 4, 2014Applicant: Atrenta, Inc.Inventors: Yuan Lu, Yong Liu, Nitin Mhaske
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Patent number: 8826205Abstract: A method for producing a verified design of a digital to analog converter (DAC) starts with providing an HDL representation of the DAC. Numerical values of the analog output signal as a function of the representation of the DAC for a range of numerical values of the digital input signal are simulated with a simulator. A model is used for converting the simulated numerical values of the analog output signal to numerical values of an equivalent model signal in the same digital format as the input signal. A comparator compares the numerical values of the input signal and the model signal and determines differences greater than a defined tolerance.Type: GrantFiled: August 13, 2013Date of Patent: September 2, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Cheng Wang, Chao Liang, Geng Zhong
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Patent number: 8826219Abstract: Disclosed herein are methods and devices used for the physical design validation of integrated circuits. One method used for the physical design validation of integrated circuits includes comparing the original circuit netlist of an integrated circuit and the layout data of the integrated circuit and assigning labels to the input and output terminals of the components in the integrated circuit based on the results of the comparison.Type: GrantFiled: October 28, 2010Date of Patent: September 2, 2014Assignee: Synopsys, Inc.Inventor: Chiu-Yu Ku
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Patent number: 8813005Abstract: Approaches for testing a module of a circuit design include tagging flip-flops in a netlist of the module with respective path names of the flip-flops from a hardware description language specification of the module. In simulating with the netlist, event data are captured to a first file. A process determines whether or not event data in the first file matches event data in a second file of event data. In response to a difference determined between the first file and the second file, an earliest occurrence of an event in the first file having an associated signal value of a first signal that does not match an associated signal value of a corresponding event in the second file is determined. The one of the plurality of flip-flops that output the first signal is determined, and the respective path name of the one flip-flop is output.Type: GrantFiled: September 3, 2013Date of Patent: August 19, 2014Assignee: Xilinx, Inc.Inventors: Khang K. Dao, Kyle Corbett
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Patent number: 8813007Abstract: One embodiment provides a system, comprising methods and apparatuses, for simplifying a set of assumptions for a circuit design, and for verifying the circuit design by determining whether the circuit design satisfies a set of assertions when the simplified set of assumptions is satisfied. During operation, the system can simplify the set of assumptions by identifying, for an assertion in the set of assertions, a first subset of assumptions which, either directly or indirectly, shares logic with the assertion. Furthermore, the system can modify the first subset of assumptions to obtain a second subset of assumptions which either over-approximates or under-approximates the first subset of assumptions. Then, the system can refine the second subset of assumptions to either prove or falsify the assertion.Type: GrantFiled: April 17, 2009Date of Patent: August 19, 2014Assignee: Synopsys, Inc.Inventor: Ashvin M. Dsouza
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Patent number: 8806401Abstract: A system and methods for reasonable formal verification provides a user with coverage information that is used for verification signoff. The coverage is calculated based on formal analysis techniques and is provided to the user in terms of design-centric metrics rather than formal-centric metrics. Design-centric metrics include the likes of a number of reads from or writes to memories and a number of bit changes for counters, among many others. Accordingly, a setup for failure (SFF) function and a trigger the failure (TTF) function take place. During SFF formal analysis is applied in an attempt to reach a set of states close enough to suspected failure states. During TTF formal analysis is applied, starting from the SFF states, to search for a state violating a predetermined property. If results are inconclusive the user is provided with a design-centric coverage metric that can be used in signoff.Type: GrantFiled: March 27, 2013Date of Patent: August 12, 2014Assignee: Atrenta, Inc.Inventors: Mohamad Shaker Sarwary, Maher Mneimneh