Abstract: In the field of functional verification of digital designs in systems that use an abstraction for portions of a circuit design to perform the verification proof, a tool is described for resolving inconsistencies between the design and abstractions for the design. The tool provides information to a user about intermediate steps in the verification process. In response, the user may provide insight about the design to allow the tool to adjust the verification analysis of the design. The information provided to the user, including possible conflicts between the design and its abstractions, may include visualization techniques to facilitate the user's understating of any inconsistencies.

Abstract: A verification support apparatus that verifies operation of a circuit includes a receiving unit, a detecting unit, and a determining unit. The receiving unit receives implementation description data of the circuit. Based on the implementation description data, the detecting unit detects a functional block that is in the circuit and includes an external input terminal that receives an external input signal. Based on a detection result of the detecting unit, the determining unit determines the functional block to verify an abnormal-event operation. The abnormal-event operation is an operation that differs from an operation implementing a function of the circuit.

Abstract: Disclosed are exemplary finite difference methods for electromagnetically simulating planar multilayer structures. The exemplary finite difference methods simulate multilayer planes by combining the admittance matrices of single plane pairs and equivalent circuit models for such single plane pairs based on multilayer finite difference approximation. Based on the methods, coupling between different layers through electrically large apertures can be modeled very accurately and efficiently.

Abstract: The equivalence of two or more constraint files of an integrated circuit (IC) design are checked. The comparison is performed between files at the same stage of design, files that correspond to different stages of the design flow, or between top-level and block-level constraint files.

Abstract: Methods and systems are provided for dynamically generating a hint set for enhanced reachability analysis in a sequential circuitry design that is represented by a Binary Decision Diagram (BDD). After determining a ranking of the BDD variables, they are sorted in the order of the ranking. The ranking is used to select some of the variables for use in creating hints for more efficiently performing the reachability analysis in a creating an equivalent sequential circuitry design.

Abstract: A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instances of a logic operation having same properties; for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation.

Abstract: A system for initializing hardware of a computer system includes a board support package (BSP) (20) and a ROM monitor (30). The BSP includes: a basic initialization module (21) for initializing a CPU, a Flash, etc.; an advanced initialization module (22) for initializing serial ports, an Ethernet, etc., for configuring parameters related to system operation and an interrupt service program; a function library (23) for storing various functions for performing configuration and modification of parameters of the hardware; and a boot loader (24) for determining whether parameters of the hardware need to be configured, and for booting an operating system or the ROM monitor based on the determination. The ROM monitor includes a command line editor (31) for inputting commands by users, a command translator (32) for translating the commands into computer-readable instructions, and a function invoking module (33) for invoking functions from the function library based on the instructions.