Abstract: A computer-implemented method to debug testbench and the associated circuit design by recording a trace of call frames along with the activities of the circuit design. By correlating and displaying the recorded call frames, the method enables users to easily trace the execution history of the subroutines and debug the testbench code. In addition, users can trace the source code of the testbench by using the trace of call frames. Furthermore, users can debug with a virtual simulation, which is done by post-processing the simulation records stored in a database.

Abstract: Embodiments of a method for detecting potential areas of inductive coupling in a high density integrated circuit design are described. The inductance mitigation process first converts the inductive analysis into a density problem. The density of wires within a region that may switch within a portion of the system clock are compared to the density of wires will not switch within that same time. Regions of the chip that have a high ratio of density of switching wires versus non-switching wires are determined to have the potential of an inductive coupling problem. Additional grounded metal is added into the problematic regions of the chip to improve the switching versus non-switching wire density.

Abstract: A method and systems are provided for screening and rapid evaluation of routed nets in a post-layout circuit environment, such as in the design of printed circuit boards. A portion of nets are selected for determination of associated signal quality factors. Signal channels containing one or more selected nets are then built. A reference input stimulus is propagated along each of the signal channels in a frequency based simulation for generating characteristic responses of the selected nets' signal channels. A signal channel quality factor is obtained for each signal channel based upon its characteristic response. The signal channels and their nets are then comparatively analyzed according to corresponding signal channel quality factors to selectively identify any aberrant nets warranting supplemental evaluation for faults.

Abstract: Methods of measuring a mean-to-target (MTT) based on pattern area measurements are provided including providing a design pattern. A plurality of design pattern measurements are measured for calculating an area of the design pattern based on a shape of the design pattern. A series of calculation measurements are calculated by continuously substituting a same variation into the design pattern measurements, and calculating a series of calculation areas corresponding respectively to the calculation measurements to generate a database including the calculation measurements and the calculation areas. An actual pattern is formed using the design pattern and an area of the actual pattern is measured. A calculation area corresponding to the area of the actual pattern is selected from the database and calculation measurements corresponding to the calculation area are selected. A difference between the design pattern measurements and the calculation measurements is calculated and the difference is set as an MTT.

Abstract: This invention (900) described a method that generates and uses a test bench for verifying an electrical design module in a semiconductor manufacturing against an electrical reference model containing a sub-circuit that matches the electrical design module. The invention includes providing (902) a description of an electrical design module that includes a plurality of ports. In addition, the invention includes providing (904) a description of an electrical reference model. The invention further includes providing and or creating (92) one or more implicit defines for the reference modules that appear in hierarchy of the electrical reference model. And, the invention includes providing (906) a description file that includes one or more instance definitions. The invention parses (91) the hierarchy of the electrical design model and then processes (96) the description file. The invention then writes (97) the test bench.

Abstract: An engineering change order (ECO) modifying an IC having spare cell instances is implemented by converting active cell instances implementing portions of the IC to be deleted into additional spare cell instances, by creating a technology independent behavioral model of portions of the IC to be added, by selecting spare cell instances to implement the behavior model, and by routing nets to the selected spare cell instances in a way that minimizes a number of metal layers of the IC that are modified.

Abstract: There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

Abstract: One embodiment of the present invention provides a system that performs sequential equivalence checking between integrated circuit (IC) designs. During operation, the system receives a first IC design and a second IC design. Each of the first and second IC designs includes a top design level and a bottom design level, and the bottom design levels include one or more sub-blocks within the corresponding top design levels. The system then verifies if each of the sub-blocks in the bottom design level of the first design is conditionally equivalent to a corresponding sub-block in the second design. Note that two designs are conditionally equivalent if the two designs can become sequentially equivalent by adding registers on the input and output ports of the two designs. The system additionally verifies if the top design level of the first design is conditionally equivalent to the top design level of the second design and if the first design is temporally equivalent to the second design.

Abstract: Methods and systems are provided for sequential netlist reduction through trace-containment for a circuitry design netlist by first identifying a cut of the netlist and enumerating a set of mismatch traces. Perform time-bounded unfolding of a cofactored version of the cut to reflect the sequential cofactor for a specific input i and temporal uncorrelation constraints for the set of inputs ‘J’. Determine whether there is trace containment by performing equivalence checking with respect to the cut of the netlist under temporal uncorrelation constraints for the set of inputs ‘J’. In response to detecting trace containment, simplify the netlist by merging the input ‘i’ to a constant.

Abstract: Methods and apparatuses to automatically determine conditions at hierarchical boundaries of a hierarchical circuit design and to use the determined conditions in hierarchical optimization and verification. In one embodiment, a hierarchical block is optimized and transformed during design synthesis using one or more lemmas at the boundary of the hierarchical block. For example, the lemmas are automatically generated to specify range information for input boundary nodes. The lemmas are also used for the equivalence checker to perform hierarchical equivalence checking. Equivalence of hierarchical blocks is individually checked, in view of the lemmas. Thus, based on the lemmas, optimizations across hierarchical boundaries can be performed, while the hierarchical structure of the design is preserved so that equivalence checking of hierarchical circuit designs can still be based on the equivalence of individual hierarchical blocks.

Abstract: This disclosure describes a method illustrated in FIG. 7 to prepare re-architected digital logic designs for sequential equivalence checking. This method initially begins with a description of an electrical design module that includes a plurality of ports, and a description of an electrical reference model that comprises a hierarchy of one or more reference modules where each said reference module comprises a plurality of internal signals. In addition, this method includes a configuration file with additional initial information. The method then processes 100 a configuration file. Then, the method 105 computes one or more output files. Finally, the method 110 writes the output files.

Abstract: This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled 200. The semiconductor design is partitioned 202 and associated input constraints 204. The edits are further grouped 206 and ordered 208. The invention also discovers a set of dependencies of the logic edits 210 and checks that the ordering of groups obeys the dependencies 212. Each group of edits is further submitted to formal verification 214 and any input constraints assumed for any partitions are verified in their enclosing partition 216. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints 218.

Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

Abstract: During compilation of a user logic design in a first type of programmable logic device (e.g., an FPGA), a log is kept of at least certain steps where choices are made. When that logic design is migrated to another type of programmable logic device (e.g., a mask-programmable logic device) the logged steps are taken into account to make sure that the same choices are made, so that the target device is functionally equivalent to the original device.

Abstract: A designing method is provided for designing an electric circuit including a clock output circuit for delivering a clock signal and a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal. The method includes, as a method for designing the wirings for clock transmission to have a predetermined length, a first step of connecting wirings between each of the processing circuits and an arbitrary point (as a “first point”) so that the wirings have substantially the same length (as a “first length”), and a second step of connecting the first point to the clock output circuit by a single wire having the length that is obtained by subtracting the first length from the predetermined length. Thus, lengths of the wirings for transmitting the clock signal to the plurality of circuits are adjustable while the entire length of the wirings is minimized.

Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

Abstract: A computer readable medium, system and associated method is provided for designing an integrated circuit with inserted loops. The method comprises the steps of inserting a loop with tagged wire segments and/or vias in a fully routed and DCR clean integrated circuit; performing a DRC; and fixing DRC violations by removing tagged wire segments and/or vias which contribute to a violation.

Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

Abstract: A method of verifying a circuit for use in an apparatus for verifying a circuit operation indicated by circuit information, the circuit including a plurality of logic circuits and at least one connection line between the logic circuits, the method includes: obtaining information of a plurality of pieces of asynchronous circuits from the circuit information; determining information of asynchronous circuits of a first type and a second type stored in a library; extracting information of an asynchronous circuit of a third type including the asynchronous circuits of the first type and the second type; and extracting verification information associated with the information of the asynchronous circuit of the third type, for verifying the circuit.

Abstract: A method includes determining whether or not a statement in a design has any functionality. The functionality includes impact on the operation of the design. Also included in the invention is an impact checker to determine the impact of portions of the design on the operation of the design.

Abstract: A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.

Abstract: A method, system and computer program product for automated use of uninterpreted functions in sequential equivalence checking. A first netlist and a second netlist may be received and be included in an original model, and from the original model, logic to be abstracted may be determined. A condition for functional consistency may be determined, and an abstract model may be created by replacing the logic with abstracted logic using one or more uninterpreted functions. One or more functions may be performed on the abstract model. For example, the one or more functions may include one or more of a bounded model checking (BMC) algorithm, an interpolation algorithm, a Boolean satisfiability-based analysis algorithm, and a binary decision diagram (BDD) based reachability analysis algorithm, among others.

Abstract: An apparatus and methods for the production of satisfiability reports are provided. In an exemplary embodiment, a method of producing a report is provided. The method includes generating a complete assignment for a CNF formula, deriving first second sets of clauses that are unsatisfied by the reference point, making decision assignments, performing BCP then recomputing the second set of clauses. One feature of this embodiment is that it provides for efficient solutions for SAT problems. Other embodiments provide apparatus and software products that implement the disclosed methods. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: Method and apparatus for translating a verification process having recursion for implementation in a logic emulator are described. Examples of the invention relate to a method, apparatus, and computer readable medium for translating a verification process for implementation in a hardware emulator of a logic verification system. A recursive task called by the verification process is identified. A copy of the recursive task is incorporated into the verification process. Interface registers are instantiated for the recursive task. Control flow transfer points are defined in the verification process. Calls of the recursive task are converted in the verification process to constructs for accessing the interface registers and transferring control flow among the control flow transfer points. The verification process is reorganized to describe a finite state machine (FSM) configured for implementation in the hardware emulator.

Abstract: Structured ASIC circuitry that is intended to be functionally equivalent to a programmed block of FPGA circuitry (e.g., a programmed FPGA LUT) is verified for such functional equivalence by using the specification (logical or physical) for the structured ASIC circuitry as a starting point for an FPGA design project. If the design project results in the same FPGA circuitry as it was intended that the structured ASIC circuitry would be functionally equivalent to, the structured ASIC circuitry has been verified and can be added to one or more libraries of structured ASIC modules that are available for use in providing structured ASIC products that are functionally equivalent to programmed FPGA products.

Abstract: A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.

Abstract: Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers (snapshot registers) to receive snapshots of the register input signals, wherein the additional registers provide register initial condition signals for use in a simulation of at least a portion of the design circuitry. Other embodiments are described.

Abstract: In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.

Abstract: In one embodiment, a method comprises retaining at least a portion of simulation results corresponding to a first simulateable partition from a previous simulation time; and using the simulation results for a second simulateable partition (or the first simulateable partition) at a current simulation time if the second simulateable partition is equivalent to the first simulateable partition and one or more input stimuli to the second simulateable partition at the current simulation time are approximately the same as the input stimuli to the first simulateable partition at the previous simulation time. Computer accessible media storing instructions that implement the method are also contemplated.

Abstract: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.

Abstract: A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The name of the deleted flip-flip is added to the name of the flip-flop to which it is merged. The apparatus compares all of the names of the flip-flops and pairs the flip-flops by name. From the input pin of each of the paired flip-flops, logic cones are defined and using these logic cones, comparison of and verification between the reference circuit and the implemented circuit is performed.

Abstract: Techniques are present for designing of integrated circuits. Both custom design data and synthesized digital design data are received and merged into a design database in an automated process. The design database is then made accessible to layout tools so that the layout tools may operate upon it. These layout tools can include, but are not limited to, custom tools, digitals, or a combinations of these.

Abstract: Embodiments include a system and method for generating RTL description of an electronic device provided for a design test and a test bench environment to drive stimulus into the electronic device, identifying at least one register to be verified during the design test, authoring a property list including a plurality of properties, wherein each property includes a cause and an effect, creating a new property instance upon receiving an enqueue cause, transitioning a property instance from a waiting state to a pending state based on a dequeue cause, advancing property instances from the pending state to an active state and then to an expired state based on a defined time window, creating a current solution space including a plurality of solutions, wherein each of the plurality of solutions includes a list of unused active effects, inserting property instances into each of the plurality of solutions when the property instance enters to active state, pruning solutions from the current solutions space which have no

Abstract: A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into the replicated portion. The circuit may also include trigger logic and clock control logic to enable execution of the replicated portion of the circuit to be paused when a trigger condition occurs. The compiled representation of the circuit may be programmed into a hardware device. A debugger may then be invoked. One or more triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of inputs that led to the trigger condition are recorded.

Abstract: One set of illegal vector sequences is manually generated for a circuit design and a symbolic simulator is used to automatically generate another set of illegal vector sequences for the circuit design. For verification purposes, the relationship between the manually generated set and the automatically generated set is determined. Prior to determining this relationship, one or both of the sets are simplified. One simplification technique includes replacing pairs of illegal vector sequences that are the same except at one bit position with a more general illegal vector sequence representative of both illegal vector sequences of the pair.

Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification components. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and OPC verification and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

Abstract: A method to validate data used in a design of a semiconductor product currently in a partially fabricated state is disclosed. The partially fabricated state having a plurality of layers up to and including a first conductive layer. The method generally includes the steps of (A) adding a second conductive layer from a user specification to an application set, the application set having a plurality of resources that define the semiconductor product, (B) validating a new resource in the user specification against the resources in the application set, (C) adding the new resource to the application set upon passing the validating and (D) propagating the new resource throughout a description of the semiconductor product, the description being stored in a computer-readable medium.

Abstract: A verification method for verifying an asynchronous circuit includes producing a netlist based on circuit information at a register transfer level, extracting delay information and an asynchronous circuit section in which circuits operating with different clock signals are coupled to each other from the netlist, processing the delay information to extend a malfunction generating period in the asynchronous circuit section, and executing verification of the asynchronous circuit based on the delay information having been processed.

Abstract: The present invention relates to a method for optimizing power/ground pads in a power/ground distribution network. A power/ground distribution network is created for each of multiple voltage domains and a load current source of each node of the power/ground distribution network is modeled in consideration of the actual shapes and areas of functional blocks. A local optimization method is developed to solve problems generated when a conventional optimization method is applied to optimization of power/ground pads in a bump shape used for a flip chip, and a combination of global optimization and local optimization is applied to layouts using bump bonding, which is discriminated from the conventional optimization method restrictively applicable to layouts using wire bonding.

Abstract: Method, apparatus, and computer readable medium for performing electrical rule checks (ERCs) on a circuit design are described. In one example, a hierarchy of cell instances is created from a schematic database for the circuit design. The hierarchy is traversed to produce master nets. Each of the master nets is associated with shorted nets in the circuit design. The hierarchy is traversed to produce ERC nets. Each of the ERC nets is associated with effectively shorted nets in the circuit design. At least one pair of the effectively shorted nets is effectively shorted across a transistor. At least one ERC is performed on the circuit design using the master nets and the ERC nets.

Abstract: One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation.

Abstract: A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design. The logic verification tool determines whether a valid solution is generated, and, if not, replaces the design with the reduced design. Until a valid solution is generated, the logic verification tool iteratively performs the selecting, reducing, determining and replacing steps.

Abstract: Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.

Abstract: A method is provided to improve the usability of Design-For-Testability Synthesis (DFTS) tools and to increase the design process productivity. The method comprises receiving a list of testability and design impact analysis functions, to be performed on the circuit, also referred to as a device under test (DUT). The impact analysis leads to the creation of logical transformations, which can be selected by a user with one or more available transformation methods from a list including, but not limited to, boundary scan test logic insertion, scan test logic insertion, memory BIST (built-in-self-test) logic insertion, and logic BIST logic insertion, and scan test data compression insertion logic insertion.

Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.

Abstract: An apparatus for analyzing circuit specification description design has a circuit specification description inputting section that analyzes and obtains information of a related signal, information of the maximum number of cycles in the related signal, and a definite value in a site defined in the circuit specification description for the related signal contained in a circuit specification description, a data base generating section that generates signal variation data indicating time-series signal variation, wherein a definitive value is set in the site defined in the circuit specification description and a predetermined flag is set in a site where the value is not defined in the signal variation data, and a waveform diagram data outputting section that outputs waveform diagram data for displaying the time-series signal variation in a form of a waveform diagram on the basis of the definite value and the predetermined flag set in the data.

Abstract: A method for prototyping and validating a customer's electronic system design (ESD) with design data is proposed. The design data is partitioned into hierarchical design elements (HDEs) plus their respective test benches. The ESD couples with customer's customer peripheral devices CPDs via their peripheral interface terminals PITs thus forming interconnected hierarchical system elements (HSEs) interacting with one another according to a functional validation specification. The HSEs form numerous system hierarchy levels (SHLs). The method includes: a) Providing a reprogrammable logic device (RPLD) with an RPLD-interface and programmable external interfaces PXIFs respectively connected to the PITs. b) Providing a simulation software tool. c) Disabling all PXIFs via RPLD-interface. (For each disabled PXIF, identifying HDEs connected to the PXIF and appending their test benches with stimuli and responses to form appended test benches.

Abstract: Disclosed herein is a semiconductor chip including at least two processing apparatuses which comply with the same interface specifications and which differ in internal structure, wherein at least one of the processing apparatuses is constituted functionally to replace at least one processing apparatus.

Abstract: Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.

Abstract: A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the identified voltage condition. The method further includes coding a pseudo layer associated with an integrated circuit layout of the circuit schematic in accordance with content of the assigned pseudo diode, and verifying consistency between the circuit schematic and the corresponding integrated circuit layout by extracting the pseudo layer from the integrated circuit layout and comparing information of the pseudo layer to the assigned pseudo diode in the circuit schematic.