Abstract: A mechanism is provided for simplifying a netlist before computational resources are exceeded. For each of a set of suspected equivalences in a proof graph of a netlist, a determination is made as to whether equivalence holds for at least one of an equivalence or an equivalence class by identifying whether the equivalence or equivalence class is either affecting or non-affecting. Responsive to the equivalence or equivalence class being affecting, a proof dependency is recorded as an edge in a proof graph. For each node in the proof graph, a determination is made as to whether the node has a falsified dependency. Responsive to the node failing to have a falsified dependency, identification is made that all dependencies are satisfied and that the equivalences represented by the node in the proof graph are sequential equivalences. The netlist is then simplified by consuming the sequential equivalences.

Abstract: A method for designing a system on a target device is disclosed. A first netlist with a first set of functionally invariant boundaries (FIBs) is generated after performing extraction during synthesis of a first version of the system in a first compilation. One or more of the FIBs is invalidated from the first set after performing optimizations during synthesis in the first compilation resulting in a second netlist with a second set of FIBs. A third netlist with a third set of FIBs is generated after performing extraction during synthesis of a second version of the system having a changed portion in a second compilation. Connectivity of matching nodes from the first netlist and the third netlist reaching FIBs is traversed to identify equivalent nodes associated with identical regions. The identical region in the third netlist is replaced with an optimized synthesized region from the second netlist.

Abstract: Mechanisms are provided in a design environment for array concatenation. The design environment comprises one mechanism to concatenate arrays with enable- and address-compatible ports, thereby reducing the number of arrays in a netlist. The design environment comprises another mechanism to migrate read ports from one array to another based upon compatible enable-, address-, and data-compatible write ports, thereby reducing the number of arrays in a netlist. The design environment comprises yet another mechanism to eliminate unnecessary arrays.

Abstract: A system and method are provided for verifying implementation of a logic core in a complete bitstream. A logic core bitstream is extracted from the complete bitstream. The logic core bitstream is compared to a reference bitstream of the logic core for a target device. In response to no discrepancy in the comparison of the logic core bitstream and the reference bitstream, a data value is stored indicating that the logic core implementation contained in the complete bitstream is verified.

Abstract: In a method of detecting metal line failures for a full-chip, a first net-list is converted to a second net-list. The first net-list includes first information related to elements and metal lines, and the second net-list includes second information susceptible to direct current analysis. Current densities of the metal lines are calculated by performing the direct current analysis on the second net-list. Defective metal lines among the metal lines are detected based on the current densities of the metal lines.

Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

Abstract: A circuit design apparatus for designing an LSI including a memory circuit for storing data and an error protection circuit for performing an error protection over the data stored in the memory circuit on the basis of design information, the circuit design apparatus includes: an extracting unit for extracting information of configuration of the memory circuit with error protection circuit from the design information; and a circuit arrangement controller for determining whether to insert a check circuit for supplying a check signal into the memory circuit to verify the error protection circuit on the configuration information.

Abstract: Methods are provided for performing depth-first searches of concrete models of systems using control flow information of the system for improved reachability analysis. The concrete model's control structure and dependencies are extracted and an over-approximated (conservative) abstract control model is created. The abstract control model simulates the concrete model during model checking. Model checking the abstract control model produces execution traces based on the control paths of the concrete model. These execution traces may be used to guide a state space search on the concrete model during invariant checking to determine satisability of one or more selected invariants of the system.

Abstract: One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation.

Abstract: The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header/cell portions, by separate handling of comments, by functionally significant/non-significant data, by whitespace/non-whitespace, and by layer within a unit of design data.

Abstract: A multi-mode redundancy removal method is provided. In this method, after accessing the design, a full-scale redundancy removal using fault simulation can be started. When a predetermined period for performing the full-scale redundancy removal has reached a first cut-off, then the method can determine a location for temporary outputs of the design, create the temporary outputs, and perform a localized redundancy removal up to the temporary outputs. An optimized design based on the full-scale redundancy removal and the localized redundancy removal can be output.

Abstract: A verification apparatus includes a reference circuit-side point extraction unit that extracts a point where the input value of a signal changes due to a logic change in a reference circuit in a state before and after the logic change, based on information regarding a signal that has changed due to the logic change in the reference circuit; a circuit to be verified-side point extraction unit that extracts a point where the input value of a signal changes due to a logic change in a circuit to be verified in a state before and after the logic change, based on information regarding a signal that has changed due to the logic change in the circuit to be verified; and a verification script generation unit that generates a verification script with use of the points extracted by the reference circuit-side point extraction unit and the circuit to be verified-side point extraction unit.

Abstract: An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of magnitude faster than gate level simulation. Moreover, design bugs associated with multi-cycle paths are more easily corrected during RTL simulation compared to waiting until the gate level simulation.

Abstract: Timing behaviors associated with constraints of circuits are compared to identify mismatches between circuit configurations. Aggregate sets of timing constraints associated with timing nodes are determined for timing paths between start points and end points. Precedence rules are applied to aggregate sets of timing constraints by applying precedence rules to interacting timing constraints. Aggregate sets of constraints for corresponding timing nodes are matched to determine if timing constraint mismatches exist between circuits. If aggregate timing constraints associated with start point, end point pairs are found to match, reconvergent points between the start point and end points are analyzed to see if aggregate constraints of timing nodes connected to reconvergent/divergent points match if timing exception matches are involved. Graph traversal algorithms allow efficient computation of aggregate timing constraints for timing nodes.

Abstract: A system and method for constructing a clock tree based on replica stages is described. The system and method may comprise determining a size of an input buffer for driving a load capacitance of the output buffer based on a fanout, determining a wire width and a wire length based on the size of the output buffer, the fanout and a replica stage mathematical model, and connecting the output buffer and the corresponding input buffer to a conductor routed on one or more predetermined metal layers and having the wire length and the wire width. The conductor is placed within ground shields having a fixed width.

Abstract: A method for managing simulation includes modifying a design for a system to allow for a path pulse filter to filter a pathpulse delay, on a signal transmitted to a component, that is greater than an IOpath delay.

Abstract: In a routing design method for designing routing of a SiP having first and second routing portions that are connected to each other via bonding wires, whether a DRC error of the first or second routing portion is present or not is determined and the DRC error is selected when the DRC error is present. A plurality of nets associated with the selected DRC error are specified and the routes of the specified nets are removed. Then, bonding wire allocations of the specified nets are changed. Further, the specified nets are rerouted so as not to cause a DRC error and whether the rerouting result is accepted or not is determined.

Abstract: A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.

Abstract: Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.

Abstract: A system and associated data structure that can be utilized within a chip design platform to define the structure of an MBIST architecture. A system for generating a memory built in self test (MBIST) design file in described, including a tool for processing an organization file (Org File), wherein the Org File includes lines of code that dictate a structure of the MBIST design file and conform to a data structure defined by the tool; wherein said data structure provides an infrastructure to describe: associations between MBIST components at a design level; associations between MBIST components and hierarchical test ports at the design level; and a serial order of daisy chains among MBIST components within the design level.

Abstract: A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process.

Abstract: A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and one or more additional tokens into the converted asynchronous circuit. The circuit is initialized with a desired additional number of tokens placed in the asynchronous circuit, or a desired number of tokens are inserted at an input before taking tokens from an output.

Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

Abstract: A device is provided with a unit that stores shape and state characteristics of connectors, their electric characteristics, a judging equation to judge whether their connections are good or not, and information defined in script; and a unit that stores information defined in script of transfer functions to transfer the electric characteristics and the judging equation along a cable, wherein the connection consistency of the cable to connect connectors of the components is checked by analyzing characteristics of each connector, and scripts of the judging equation and the transfer functions; and a suitable cable candidate is selected and a processing is achieved by making use of scripts and an algorism unified for connectors and cables with various characters.

Abstract: A redundant logic circuit detection method includes storing unit-logic-circuit information, waveform data and a limiting condition in a storage section. The unit-logic-circuit information indicates a plurality of unit-logic-circuits synthesized based on logic design information. The waveform data indicates a logic simulation result with respect to the plurality of unit-logic-circuits. The limiting condition defines a comparison condition of the waveform data. The method selects a first unit-logic-circuit from the plurality of unit-logic-circuits. The method detects a second unit-logic-circuit having a substantially identical sequence of the waveform data to the first unit-logic-circuit based on the limiting condition. The method outputs the first unit-logic-circuit and the second unit-logic-circuit as redundant circuit information.

Abstract: A static formal verification tool is used to test properties for a circuit design, where the properties are written in a verification language, such as SystemVerilog, that allows local variables. The use of local variables presents implementation challenges for static formal verification tools because it requires multiple instances of the local variables to be tracked during the verification process. To deal with local variables, the static formal verification tool translates a property containing local variables into an optimized, statically allocated data structure that does not need multiple representation of different instances of the local variables. The formal verification is then performed using the data structure. This reduces the verification complexity and makes the size of the problem representation predictable.

Abstract: In designing an integrated circuit on a die having a set of die bumps, a method to generate a set of lumped circuit parameter values associated with the set of die bumps, based upon distances between the set of die bumps and the center of the die, the method also based upon a sample-data distribution function of a die bump distance variable and a sample-data distribution function of a lumped circuit parameter variable. Other embodiments are described and claimed.

Abstract: A apparatus for analyzing a delay in path between flip-flops, including: a calculator that performs delay calculation and generates a delay calculation result on wiring and layout of logic circuits; a analyzer that performs delay analysis for each delay calculation results, and generates delay analysis results for paths by adding delay of logic elements and flip-flops, and by multiplying the sum calculated by a scattering coefficient; a sorter that stores delay analysis results for paths, thereby generating a maximum delay sorting result; a probability calculator that generates probability density functions for paths on a condition by performing processing in which a path is selected from paths in order of maximum delay on the maximum delay sorting result, and a probability density function is generated for the path selected between the flip-flops; and a value calculator that performs maximum value calculation for the probability density functions for all the paths.

Abstract: Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal paths based on computed parameter values for the corresponding metal path. A reliability analysis for the circuit is performed based on the apportioning. In an embodiment, metal paths which predominantly carry currents with an average value less than a threshold are excluded from being considered as contributors to EM degradation.

Abstract: A layout verification device according to the present invention includes a layout verification unit that outputs a first error graphic corresponding to an area where there is an inconsistency with a design rule in a first layout pattern, and includes a target error graphic setting unit that sets a processing target area including the first error graphic, an error graphic search unit that searches a second error graphic included in a processing target area of a second layout pattern where verification by the layout verification unit has already been performed, and an error graphic equivalence judgment unit that judges that the first error graphic and the second error graphic are non-equivalent when a second target vertex coordinate of the second error graphic does not match any one of a plurality of peripheral vertex coordinates set in grid intersections adjacent to the first target vertex coordinate of the first error graphic.

Abstract: A computer-implemented method for verifying a design includes representing a verification directive, which pertains to the design and includes a local variable, by a finite state machine. The state machine includes multiple states, with transitions among the states, transition conditions associated with the transitions, and procedural blocks, which correspond to the transitions and define operations to be performed on the local variable when traversing the respective transitions. The finite state machine is executed by traversing the transitions in accordance with the respective transition conditions and modifying the local variable in accordance with the respective procedural blocks of the traversed transitions, so as to verify the design with respect to the verification directive.

Abstract: Embodiments of methods and apparatus for optimization of verification of a chip design are disclosed. In various embodiments, a method for reducing a number of points to be verified during a verification process is disclosed, the method comprising selecting a first and a second verification point of a model of an integrated circuit design, determining whether the first and second verification points are isomorphic, and outputting the result of the determining to enable the first and second verification points being verified by verifying only a selected one of the first and second verification points in case the first and the second verification points are isomorphic. Additional variants and embodiments may also be disclosed and claimed.

Abstract: A method is disclosed of determining a likelihood of failure of a circuit made in accordance with a circuit design based on at least one variable derived from measurements of a fabricated component or component combination included in the circuit design. Also disclosed is a processor configured to perform the method and a computer-readable medium storing method instructions.

Abstract: A method and mechanism is disclosed for identifying connected shapes and objects in an electrical design. The entire hierarchical design does not have to be flattened to perform the operation of identifying connected objects for a specific object. Instead of unfolding the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes need to be unfolded to perform the search.

Abstract: A computer readable storage medium includes executable instructions to identify a path in target source code. Constraints associated with the path are extracted. The constraints are converted to a Boolean expression. The Boolean expression is processed with a Boolean satisfiability engine to identify either a feasible path or an infeasible path. A feasible path is statically analyzed, while an infeasible path is not statically analyzed.

Abstract: A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions). The receiver model can then use different capacitance values to generate different portions of the model receiver signal, thereby enabling more accurate matching of actual receiver signal timing characteristics. For example, a two-capacitance receiver model can be generated by using the first capacitance value to match the delay characteristics of an actual receiver, and by using the second capacitance (in light of the use of the first capacitance) to match the slew characteristics of that actual receiver. Because typical EDA timing analyses focus mainly on delay and slew (and not the detailed profile of circuit signals), a two-capacitance receiver model can provide a high degree of accuracy without significantly increasing cell library size and computational complexity.

Abstract: An integrated circuit modeling method 100 implementable on computer, which has an executable software model 145 having modules 140 of reusable functional cores 105 coded in a high level language and a virtual platform of the integrated circuit employable in an architecture exploration step 115. A modeling library of modules coded in high level languages and hardware level languages are provided and instantiated according to user input in a functional verification step 120 having a co-simulation environment, with interface code 170 between modules automatically generated by an interface generator 130 based on a two dimensional data array of hardware specification inputs 205, the interface code 170 further interfacing with wrappers engaged between high and hardware level language modules.

Abstract: A computer implemented method and system for converting schematic diagrams. The method includes accessing a first set of schematic diagrams, wherein the schematic diagrams represent an integrated circuit design to be realized in physical form. A plurality of a first type of circuit elements in the first set are converted into a second type of circuit elements. The conversion is implemented in accordance with a set of conversion rules. A second set of schematic diagrams representing the integrated circuit design and including the second type of circuit elements are then output.

Abstract: A system and method is disclosed for converting an existing circuit description from a lower level description, such as RTL, to a higher-level description, such as TLM, while raising the abstraction level. By changing the abstraction level, the conversion is not simply a code conversion from one language to another, but a process of learning the circuit using neural networks and representing the circuit using a system of equations that approximate the circuit behavior, particularly with respect to timing aspects. A higher level of abstraction eliminates much of the particular implementation details, and allows easier and faster design exploration, analysis, and test, before implementation. In one aspect, a model description of the circuit, protocol information relating to the circuit, and simulation data associated with the lower level description of the circuit are used to generate an abstract model of the circuit that approximates the circuit behavior.

Abstract: An improved method for performing a formal verification of a property in an electronic circuit design comprises: specifying at least one safety property in the electronic circuit design at a register-transfer level, setting boundaries of a logic cone to a start level according to a configurable structural design criterion, extracting the logic cone from the electronic circuit design based on the at least one specified safety property and the set boundaries, executing a formal verification tool on the logic cone to verify the at least one specified property, extending the boundary of the logic cone according to a configurable structural design criterion and performing the extracting and executing on the new logic cone, if the verification result does not satisfy the at least one safety property.

Abstract: Some embodiments of the present invention provide techniques and systems for determining whether a high-level model (HLM) for a circuit design is equivalent to a register-transfer-level (RTL) model for the circuit design. During operation, a system can identify a set of checkpoints. Each checkpoint can be associated with a characteristic function defined over the states of a finite-state-machine (FSM) representation of the HLM, a characteristic function defined over the states of an FSM representation of the RTL model, and an invariant defined over a set of variables in the HLM and a set of registers in the RTL model. Next, the system can generate a set of invariant proof problems, wherein each invariant proof problem corresponds to a transition between two checkpoints in the set of checkpoints. The system can then determine whether the HLM is equivalent to the RTL model by solving the set of invariant proof problems.

Abstract: Methods and systems are provided for dynamically generating a hint set for enhanced reachability analysis in a sequential circuitry design that is represented by a Binary Decision Diagram (BDD). After determining a ranking of the BDD variables, they are sorted in the order of the ranking. The ranking is used to select some of the variables for use in creating hints for more efficiently performing the reachability analysis in a creating an equivalent sequential circuitry design.

Abstract: A method, system and computer program product for integrating implication-based analysis and equivalent gate analysis to maintain transitive reduction in an implication graph over a sequence of graph operations. One or more gates of a design are identified that are equivalent in all reachable states. Equivalent gates are assigned to an equivalence class when all gates within the equivalence class are equal. During the implication-based analysis the system determines when one or more implication paths are associated with the one or more equivalence classes, and an implication is generated at the implication path associated with the equivalence classes. A transitively reduced graph is received depicting the implications and equivalence classes of the design. When one or more operations are assigned to the transitively reduced graph, the graph is automatically adjusted to maintain transitive reduction.

Abstract: A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.

Abstract: A design approach provided according to an aspect of the present invention consolidates the constraint files of respective modes into consolidated information and performs place-and-route using such consolidated information. The resource requirements may be reduced as result. Another aspect of the present invention provides a programmatic approach to consolidating timing constraint files of different timing modes into consolidated information.

Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. Provision is made for applying the method to logic designs implemented in programmable logic integrated circuit devices.

Abstract: Embodiments in the present disclosure pertain to domain translators. A domain translator converts a variable from one domain to a different domain. Domains include, but are not limited to, voltage, current, frequency, phase, delay, and duty-cycle. In particular, domain translators enable conversion between standard voltage and current domains commonly used by circuit simulators to other domains such as frequency, phase, delay, duty-cycle, etc., so that linear analysis can be performed on a wide range of circuits that exhibit linear behavior in domains other than voltage and current.

Abstract: A circuit board analyzer includes a storage unit for storing mesh position information on an analyzed mesh-division model and extracted circuit constants in relation to each other; a division-model configuration unit for dividing the layout of a circuit board into meshes to configure a new mesh-division model; an identical-mesh determination unit for making a comparison between mesh position information on the new mesh-division model and mesh position information on the analyzed mesh-division model to determine identical meshes that have identical mesh position information; and a circuit-constant extraction unit for performing analytical processing based on the new mesh-division model to extract new circuit constants and reusing, as a new circuit constant associated with the identical meshes, an extracted circuit constant that is related to the mesh position information on the identical meshes.

Abstract: A method for performing verification is disclosed. The method includes selecting a set of gates to add to a first localization netlist and forming a refinement netlist. A min-cut is computed with sinks having one or more gates in the refinement netlist and sources comprising one or more inputs of an original netlist and one or more registers registers of the original netlist which are not part of the refinement netlist. A final localized netlist is obtained by adding one or more gates to the refinement netlist to grow the refinement netlist until reaching one or more cut-gates of the min-cut.

Abstract: The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.