Abstract: A method includes providing a symbolic power distribution network (PDN) map for a PDN of an circuit design including at least a first mesh that includes a plurality of map nodes; modeling at least one parasitic component that is provided on a branch of the symbolic PDN map and a pair of current sources that are provided at two respective map nodes of the symbolic PDN map; providing a matrix equation based on an interrelated conduction behavior among the parasitic component and the pair of current sources, wherein the matrix equation includes a current source term representing the pair of current sources and an unknown variable term representing a voltage level of at least a map node of the symbolic PDN map; and based on the matrix equation, expanding the unknown variable term in a frequency-domain as a sum of plural mathematical components while keeping the current source term intact.

Abstract: An input device includes an input surface having a first axis and a second axis, and force sensor electrodes. The force sensor electrodes have non-uniform distances between adjacent force sensor electrodes along the first axis.

Abstract: The described techniques implement an electronic design with transistor level satisfiability models by identifying a plurality of channel connected components of an electronic design for sensitization. These techniques further determine a set of transistor level satisfiability (SAT) models for the plurality of channel connected components of the electronic design and transform the plurality of channel connected components into a set of conjunctive normal form (CNF) formulae using at least the set of transistor level SAT models. The plurality of channel connected components of the electronic design may be sensitized at least by determining one or more satisfying assignments with the set of CNF formulae. These techniques may also generate transistor level satisfiability (SAT) logic models and transistor level SAT state models for a circuit component based in part or in whole upon design specifications and one or more characteristics of the circuit component.

Abstract: The present invention relates to a computer module testability problem detection method defined: on the one hand, by first code instructions in a modeling language representing blocks, divided up into one or more components, and relationships between the blocks and/or the components, and on the other hand, by second code instructions in a textual language representing a list of specifications that are each associated with a capability and define at least one information flow at the capability.

Abstract: Disclosed herein are embodiments of systems and methods for a deterministic modeling of integrated clock gate (ICG) activity in a vectorless power analysis of a synthesized integrated circuit (IC) design. The systems and methods may generate a priority list of the ICGs based on the slack values of the outputs of the ICGs calculated from a static timing analysis (STA). The system and method may further receive one or more priority inputs from the user and select the ICGs to be activated during power analysis based on the priority list and the priority inputs from the user. The systems and methods may propagate a set of state stimuli through the output cones of the selected ICGs and calculate the current through and power consumed by circuit devices in the output cones based on the state propagation and global data activity.

Abstract: Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. Using the processor, the netlist can be modified by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element.

Abstract: The present disclosure relates to an error resilient scheme for a signal processing device configured to perform iterative processing on clocked input data and to provide output data. The signal processing device includes a computation circuit comprising at least one computation unit circuit configured to perform one computation in each iteration on the clocked input data and to provide or generate processed data, and a selection circuit configured to provide as the output signal either the processed data or the clocked input data, depending on a control signal representative of a set-up timing error detected in an input data.

Abstract: According to one aspect, embodiments of the invention provide a CDC simulation system comprising a timing analysis module configured to receive a circuit design, analyze the circuit design to identify at least one CDC, and generate a report including information related to the at least one CDC, a CDC simulation module configured to communicate with the timing analysis module and to receive the report from the timing analysis module, and a test bench module configured to communicate with the CDC simulation module, to receive the circuit design, and to operate a test bench code to simulate the operation of the circuit design, wherein the CDC simulation module is further configured to edit a top level of the test bench code, based on the received report, such that the test bench module is configured to identify timing violations in the circuit design due to the at least one CDC.

Abstract: A device may receive a merchant query including first merchant data associated with a first merchant. The first merchant data may be provided, as input, to a merchant matching model associated with a merchant data structure, the merchant matching model having been trained to determine a measure of confidence that input merchant data corresponds to an existing merchant in the merchant data structure. The device may receive, as output from the merchant matching model, a measure of confidence that the first merchant data corresponds to a second merchant, the second merchant being associated with second merchant data stored in the merchant data structure. The device may also determine, based on the measure of confidence, that the first merchant corresponds to the second merchant. Based on the determination, the device may obtain the second merchant data from the merchant data structure and perform an action based on the second merchant data.

Abstract: Integrated circuit design computing equipment may perform register moves within a circuit design. When moving the registers, counter values may be maintained for non-justifiable elements. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that is used to generate a sequence for resetting the circuit design. The adjustment value may be bound by a user-specified maximum value. The user-specified maximum value may constrain logic/physical synthesis transforms and local/global retiming operations. If the counter value for a non-justifiable element is equal to the user-specified maximum value, then all future forward retiming across that element is prevented. If the maximum counter value is less than the user-specified maximum value, the user may optionally shorten the reset sequence.

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine two or more input sequences of signal transition representations associated with an input net of an indicated component in an RTL circuit design, where the two or more input sequences of signal transition representations are associated with a mode element. Each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). The mode element indicates a selection between two or more output sequences of signal transition representations. It is determined, based on the indicated component and the mode element, two or more output sequences of signal transition representations derived from the input sequence(s) of signal transition representations.

Abstract: A method for designing a system on a target device includes placing the system on the target device. A netlist retiming is performed on the placed system. A clock allocation and a clock region optimization are performed utilizing information from the placing and the netlist retiming.

Abstract: Parallelizing operations for implementing a circuit design can include dividing, using a processor, the circuit design into a plurality of partitions, wherein each partition is stored as a separate file, for each partition, generating, using the processor, a timing arc file specifying boundary delays for the partition, and generating, using the processor, a partition design file specifying interfaces of the partitions. Using the processor, a plurality of processes executing in parallel can be initiated. Each process is adapted to operate on a selected partition using the partition design file and the timing arc files for the other partitions to generate an updated file for the selected partition.

Abstract: A method for simulating an integrated circuit design is provided. The method includes executing a characterization tool over a first portion of a parameter space of a circuit design to form a netlist associated with the first portion of the parameter space. The method also includes forming a first sub-netlist from the netlist, selecting, for the first sub-netlist, a condition from at least one of a process, a voltage, or a temperature condition, and at least one parameter from the first portion of the parameter space. The method further includes executing a simulation of the first sub-netlist in a selected solver mode using the condition and the at least one parameter, and incorporating a result of the simulation in a circuit performance report, wherein the result is associated with the condition, with the at least one parameter, and with the first sub-netlist.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In accordance with aspects of the present disclosure, a computer-implemented method for statistical static timing analysis of an integrated circuit is provided. The method may comprise identifying a timing parameter that contributes to a delay calculation. The method may further comprise determining, by a processing device, whether the identified timing parameter significantly impacts the delay calculation. The method may also comprise, responsive to determining that the identified timing parameter does not significantly impact the delay calculation, avoiding a sensitivity calculation for the identified timing parameter.

Abstract: A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path in the circuit design, the adding being performed in accordance with at least a first design rule. The multitude of partial-paths start at a first location. The method further includes comparing each of the multitude of partial-paths to each other when the multitude of partial-paths end on a common second location different from the first location, and saving one of the multitude of partial-paths that leads to a shortest first path. The method further includes eliminating one of the multitude of partial-paths that are not selected to lead to the shortest first path.

Abstract: A quantum circuit and method for Schur transform includes: a first quantum register including n quantum systems initialized to an initial state of “0”, where n is an integer and represents a number of quantum systems; a second quantum register including m quantum systems initialized to the initial state of “0”, where m is an integer and represents a required workspace; a first quantum circuit that operates on only the first register and performs a block diagonalization of the n quantum systems into permutation modules; a second quantum circuit that operates on both registers and block diagonalizes each of the permutation modules using a QFTPermMod operation; and one or more quantum output registers coupled to the second quantum circuit for holding a basis for the Schur transform.

Abstract: The method includes identifying, by one or more computer processors, a first container with first software stack and a valid multipath configuration, wherein the first software stack is a first path of the valid multipath configuration. The method further includes creating, by one or more computer processors, a second container, wherein the second container has the same rules as the first container. The method further includes creating, by one or more computer processes, a second software stack in the second container, wherein the software stack is a redundant software stack of the first software stack. The method further includes creating, by one or more computer processors, a second path from the first container to the second software stack, wherein the second path bypasses the first software stack.

Abstract: A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.

Abstract: Disclosed approaches for processing a circuit design targeted to a programmable integrated circuit (IC) include inputting the circuit design to a programmed processor. Each path of the circuit design specifies a plurality of circuit elements of the programmable IC. For each circuit element specified in a path of the plurality of paths the processor looks up in a memory a mean delay associated with the circuit element, looks up a sigma factor associated with the circuit element, and looks up a delta factor associated with the circuit element. The processor determines a delay of the path as a function of the mean delay, sigma factor, and delta factor of each circuit element in the path.

Abstract: Disclosed is an improved approach to implement selective transformations of circuit components for performing verification. The approach looks at the observability of components to downstream properties to determine whether transformations are needed. The verification system leverages the knowledge about the behavior of the domains/components to identify only a subset of components that really need to undergo transformation.

Abstract: An example method for determining test conditions for at-speed transition delay fault tests on semiconductor devices is provided and includes analyzing scan patterns for testing a circuit of a device-under-test (DUT), identifying paths in the circuit activated by the scan patterns, determining behavior of the paths at different test corners, generating a histogram for each scan pattern representing a distribution of paths exhibiting worst-case behavior at corresponding test corners, generating an ordered set of scan pattern-test corner combinations based on the histogram, selecting a threshold for the ordered scan pattern-test corner combinations based on quality metrics, generating an ordered test set including the ordered scan pattern-test corner combinations with the selected threshold, and feeding the ordered test set to a test instrument, the test instrument testing the DUT according to the ordered test set, the tests being performed at the test corners listed above the selected threshold.

Abstract: A device is configured to receive delay information associated with a model including a set of model elements and one or more delay elements. The delay information may identify a model element, of the set of model elements, and a quantity of delay to be associated with the model element. The model may be associated with a total quantity of delay. The device is configured to determine accumulated delay information based on the model, and to determine a set of retiming values associated with the set of model elements. The device is configured to redistribute the one or more delay elements associated with the model, based on the set of retiming values, to satisfy the quantity of delay to be associated with the model element, and to maintain the total quantity of delay associated with the model. The device is configured to provide the redistributed model.

Abstract: Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for all instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: Disclosed are systems, methods, and computer-readable storage media for adaptive telemetry based on in-network cross domain intelligence. A telemetry server can receive at least a first telemetry data stream and a second telemetry data stream. The first telemetry data stream can provide data collected from a first data source and the second telemetry data stream can provide data collected from a second data source. The telemetry server can determine correlations between the first telemetry data stream and the second telemetry data stream that indicate redundancies between data included in the first telemetry data stream and the second telemetry data stream, and then adjust, based on the correlations between the first telemetry data stream and the second telemetry data stream, data collection of the second telemetry data stream to reduce redundant data included in the first telemetry data stream and the second telemetry data stream.

Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, producing an integrated circuit layout for multiple instances of a circuitry element, wherein interface components in one instance of said circuitry element communicate with complementary interface components in an adjacent instance of said circuitry element, said interface components being identical between said multiple instances; said producing step comprising: for one instance of said circuitry element, generating an integrated circuit layout for said one instance of said circuitry element on the basis of timing parameters of said complementary interface components with which said one instance communicates in use; detecting timing characteristics of said interface components of said one instance of said circuitry element; applying said detected timing characteristics as said timing parameters of said complementary interface components; and repeating said generating step.

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. A clock node of the first flip-flop is connected to receive a first clock signal and a clock node of the second flip-flop is connected to receive a second clock signal. The propagation delay from the first flip-flop through the level-sensitive latch to the second flip-flop is smaller than the skew between the first clock and the second clock, thereby presenting a hold time violation. A level-sensitive latch control circuit is configured to prevent the hold time violation by providing a pulsed clock signal to a clock node of the one level-sensitive latch circuit.

Abstract: Systems and methods for time-multiplexed synchronous logic provide an enhanced time delay multiplexing (TDM) scheme that includes soft TDM logic generated by computer-aided design (CAD) tools to actualize a circuit design with improved density. The CAD tools can be used to utilize inherent regularity to devise time multiplexing user logic. The CAD can generate soft TDM hardware to realize a circuit design with improved density.

Abstract: A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine whether module instances of a register level circuit design share a common usage, each instance being associated with a mapping. Two instances share a common usage if a sequence of signal transition representations received by the first instance can be mapped using a first mapping to the same common sequence of signal transition representations as a mapping of another sequence of signal transition representations received by the second instance using a second mapping. A result sequence of signal transition representations was generated by a previous propagation of the common sequence through the common usage. If the two instances share the common usage, the result sequence is mapped to an output sequence for the second instance using the second mapping.

Abstract: A data transmission system and a transmission method thereof are provided. The data transmission system includes a first electronic apparatus and a second electronic apparatus. The first electronic apparatus includes a first clock pin and a first data pin. The second electronic apparatus includes a second clock pin and a second data pin. In a connecting detection mode, the first electronic apparatus transmits a first detection signal to the first clock pin and drives the first data pin to a reference logic level. The second electronic apparatus transmits a second detection signal to the second clock pin and drives the second data pin to the reference logic level. The first electronic apparatus determines whether the first and the second electronic apparatuses are connected to each other according to whether at least one of signals on the first clock pin and on the first data pin is varied or not.

Abstract: Approaches for processing a circuit design include determining pin slack values for pins of the circuit elements in the circuit design. A processor selects a subset of endpoints based on pin slack values of the endpoints being in a critical slack range and determines startpoints of the circuit design that are in respective critical fanin cones. For each endpoint of the subset, the processor determines an arrival time from each startpoint in the respective critical fanin cone and determines for each startpoint-endpoint pair, a respective set of constraint values as a function of the respective arrival time from the startpoint. The processor generates a graph in the memory circuit from the startpoint-endpoint pairs. First nodes in the graph represent the startpoints and second nodes in the graph represent the endpoints, and values in the respective set of constraint values are associated with edges that connect the nodes.

Abstract: Aspects of the disclosed technology relate to techniques of inserting stress-enhancing filler cells for leakage reduction. Stress analysis is first performed to identify devices with large leakage current in a layout design. An optimization zone in a row of cells that contains one or more of the devices with large leakage current is then determined. Stress-enhancing filler cells are inserted into the optimization zone to replace some or all of the one or more filler cells while placement of the cells in the optimization zone is adjusted based on a leakage reduction analysis.

Abstract: A method is disclosed that includes establishing an intellectual property (IP) bank, an application bank, and a technology bank; selecting valid configurations from the IP bank for corresponding IPs and at least one subsystem based on the application data, for generating in response to a user-defined requirement, by a model generator, a performance, power, area and cost (PPAC) model of the valid configurations; based on the PPAC model, creating at least one architecture comprising at least one of the corresponding IPs, and at least one of the valid configurations for the at least one of the corresponding IPs; and, estimating, by a PPAC explorer assessing the technology bank, at least one of a performance value, a power value, an area value and a cost value for a fabrication of the at least one architecture by simulating available fabrication process technology based on the technology bank.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in a register transfer level circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to one or more possible signal states. Determining the input sequence of signal transition representations includes determining that a subsequence of the input sequence of signal transition representations indicates at most one transition within the subsequence of the input sequence.

Abstract: Certain aspects direct a distributed Intelligent Platform Management Interface (D-IPMI) system. The system includes a computing device and a distributed management device. The distributed management device includes a first management device and at least one second management device physically separated from each other. A stack interface connects the first management device and the second management device to perform an internal communication between the first management device and the second management device. The first management device may be used to perform time critical functions related to the computing device, and the second management device may be used to perform non-critical functions. For example, the first management device may perform system power control of the computing device, monitor system components and obtaining system information of the computing device, and perform system communication with the computing device.

Abstract: Embodiments of the invention relate to a configurable register file for inclusion in ASIC and other integrated circuit designs such as those based on metal configurable standard cell (MCSC) technology. According to certain general aspects, configurable register files provided by the present embodiments improve area, power and routing efficiencies and flexibility over conventional approaches such as hard memory macros and RTL designs. In embodiments, a configurable register file is implemented as a soft macro constructed from metal configurable standard cell (MCSC) base cells. According to certain aspects, unlike a hard memory macro, width and depth are not fixed and can be configured or programmed to any desired dimension or configuration. In some embodiments, a bit array of a configurable register file is comprised of register file bit cells. In other embodiments, a bit array of a configurable register file is comprised of ROM bit cells.

Abstract: Apparatuses, methods, and systems for automatically commissioning lighting controls using sensing parameters of the light controls are disclosed. One embodiment includes a building control system. The building control system includes a plurality of sensors, a plurality of lights associated with the plurality of sensors, and a controller. The controller is operative to receive sense signals from the plurality of sensors, and generate a graph based on the sensed signals, wherein the graph includes nodes that represent light locations, and edges that represent distances between the lights. For an embodiment, the controller further operative to performing inexact graph matching between a floor plan graph and the sensor graph, thereby automatically commissioning the plurality of lights based on the sensed signals of the plurality of sensors.

Abstract: Aspects relate to a computer implemented method for timing analysis and pessimism removal of an integrated circuit. The computer implemented method includes performing, using a processor, a static timing analysis of the integrated circuit and generating timing data, generating a light weight path signature of a path using the generated timing data, performing common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information, and storing, in a storage medium, the light weight path signature and the corresponding CPPR information. The method also includes generating a timing report using the light weight path signature and the corresponding CPPR information, wherein the timing report includes full path details generated using at least the light weight path signature, and reporting the timing report with full path details and corresponding CPPR information.

Abstract: A system and method perform global routing during integrated circuit fabrication. The method includes performing a design change in a portion of an integrated circuit design using a processor, determining whether the design change requires rerouting, and requesting a global routing lock based on determining that the design change requires the rerouting. The method also includes a router providing control of the global routing lock to one of two or more of the threads that request the global routing lock, and performing global routing for all of the two or more of the threads in parallel. A physical implementation of the integrated circuit design is obtained.

Abstract: A method, system, and computer program product to perform parallel multi-threaded common path pessimism removal in integrated circuit design include constructing, using a processor, a thread-specific graphical representation (TSGR) relating to each data node and clock node pair and performing processes in parallel for each TSGR. The processes include determining initial arrival times at the data node and the clock node, computing initial test slack based on the initial arrival times at the data node and the clock node, identifying fan-out nodes among the additional nodes, each fan-out node being an origin of at least two of the edges in the two or more paths to the clock node, generating one or more tags based the fan-out nodes, determining adjusted arrival times based on the one or more tags, and computing adjusted test slack based on the adjusted arrival times.

Abstract: A system and method tests for functional equivalence prior to automatically retiming a high-level specification. An Intermediate Representation (IR) includes one or more graphs or trees based on the high-level specification. A functional equivalence (FE) analyzer determines whether one or more components in the graph meet certain value and state conditions and thus is a candidate for retiming. A scheduler can use components that fail FE as a retiming boundary.

Abstract: One aspect of the invention provides a including: (a) placing N×N max size buffers at an (n?1)st level of one of the voltage domains i until a maximum slew slewmax within the voltage domain i exceeds a defined slew threshold; (b) calculating maximum insertion delay values for all cases for each of the voltage domains; (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j: (i) adding a max size buffer to all voltage domains except voltage domain j; and (ii) repeating steps (b) and (c); (d) reducing buffer sizes for each of the voltage domains; (e) recalculating maximum insertion delay values; and (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.

Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.

Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.