Abstract: The present patent document relates to a method and apparatus for more efficiently simulating a circuit design (DUT), making use of a hardware functional verification device such as a processor-based emulator. A set of linked databases are compiled for the DUT, one for hardware emulation (without timing information for the DUT) and one for software simulation (including timing information) that remain synchronized during runtime. The compiled design is run in a hardware emulator during an initialization/configuration phase and the state saved. The state is then swapped to a software simulator where timing information, such as SDF timing, may be honored during the second part of the run and the user's test bench stimuli applied to the design.

Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.

Abstract: An apparatus includes: a storage unit configured to provide a device design; a control unit configured to analyze the device design for a multi-cycle exception, generate a multi-cycle exception profile, and generate a checker based on the multi-cycle exception profile for a test bench for a simulation version of the device design.

Abstract: A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation data; extract domain-specific information about the design for variables of interest; execute a data mining algorithm with the simulation data and the domain-specific information, to generate a set of candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information, the candidate assertions being likely invariants; conduct formal verification on the design with respect to each candidate assertion by outputting as invariants the candidate assertions that pass verification; iteratively feed back into the algorithm a counterexample trace generated by each failed candidate assertion, each counterexample trace including at least one additional variable in the design not previously input into the data mining algorithm, to thus increase coverage of a state space of the

Abstract: A first signal is transmitted through a first path. A computing device determines a signal propagation time of the first signal. The computing device transmits a second signal through a second path, wherein the second path includes the second signal traversing across at least one interconnecting structure. The computing device determines a signal propagation time of the second signal. The computing device determines a propagation time difference between the signal propagation time of the first signal and the signal propagation time of the second signal. The computing device adjusts a clock based on the determined propagation time difference.

Abstract: A method analyzes RTL code to determine congestion of a logic design without completing a synthesis phase of a chip design process. The method can include receiving RTL code, and identifying a statement in the RTL code. The method can include determining that the statement in the RTL code corresponds to a structured device group in a component library, wherein the structured device group includes logic devices configured to occupy an area in a predefined spatial arrangement and with predetermined connectivity between the logic devices. The method can include determining congestion associated with the structured device group by performing operations including determining a congestion figure. The method can also include providing, based on the congestion figure, an indication of the congestion associated with the structured device group.

Abstract: An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing an interface for showing information of the layout result and adjusting a plurality of lines of the layout circuit.

Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.

Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.

Abstract: A lumped aggressor model is used to simulate multiple aggressor nets acting on a victim net. By lumping the aggressor nets together into a single input port, a single voltage excitation may be applied to the input port to simulate the model during static timing analysis. However, a record of each individual aggressor net and several associated attributes for each aggressor net is maintained such that the individual lumped aggressor nets may still be modeled as separate contributions to the attack on the victim net.

Abstract: A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path and a load on the first transmission path between the first interface port and a specific circuit element in the netlist file; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and calculating a first signal transmission time of the first transmission path out according to the interface circuit file.

Abstract: Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional statement and inferring one or more potential clock domains for logic associated with the identified statements.

Abstract: In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.

Abstract: In one approach for improving timing in an electronic circuit design having a finite state machine (FSM), control bit logic is generated based on next state logic of the FSM that generates current state bits of the FSM. The control bit logic and a control state bit are added to operate in parallel with the next state logic and the current state bit registers, and the output signal from the control bit register replaces selected logic in logic downstream from the FSM and current state bit registers. If a worst case delay is improved with the design having the control bit logic and control state bit, the modified circuit design is saved for evaluating other possible timing improvements. Otherwise, the modification is discarded.

Abstract: Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order, wherein an output pin of a driver gate is electrically coupled to an input pin of the gate. Next, the embodiment can determine a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design. The embodiment can then downsize the gate based on the maximum delay value, wherein said downsizing comprises inputting the maximum delay value in a closed-form expression. Timing margin computation can be used to ensure that timing violations are not worsened when the embodiment recovers area from non-timing-critical regions of the circuit design.

Abstract: A timestamp generator generates a timestamp value having a predetermined number of most significant bits and a predetermined number of least significant bits. The least significant bits are transmitted to a client via a parallel data bus. The most significant bits are transmitted to the client sequentially via a series data bus. Each client receives the parallel least significant bits and the series most significant bits and assembles a complete time stamp value.

Abstract: A system having a function block execution framework. Function blocks may be for use in a control system design. These blocks may be selected from a library of a function block engine. Selected function blocks may be executed for operational purposes. They may be continuously executed by a processor to maintain operational status. However, since a function block engine and a resulting system of function blocks may be operated with battery power, executions of function blocks may be reduced by scheduling the executions of function blocks to times only when they are needed. That means that the processor would not necessarily have to operate continuously to maintain continual execution of the function blocks and thus could significantly reduce consumption of battery power.

Abstract: A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage.

Abstract: A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

Abstract: A method for using computing equipment to perform timing analysis on an integrated circuit design includes identifying a timing arc of the integrated circuit design. The timing arc may be a clock path or a data path in the integrated circuit design. A probability of the timing arc may be obtained and an aging effect for the timing arc may be calculated. The aging effect of the timing arc is calculated based on the probability. The timing arc may include maximum and minimum delays that are adjusted based at least partly on the calculated aging effect on the timing arc.

Abstract: Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches.

Abstract: An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.

Abstract: A timing analysis method applied for a non-standard cell circuit, includes: identifying at least a first register and a second register from the circuit; calculating at least one path delay of at least one path between the first register and the second register; calculating a first register clock delay from a first clock source to a first register clock input terminal of the first register; calculating a second register clock delay from a second clock source to a second register clock input terminal of the second register; and determining whether timing violation takes place in respect of the second register according to the path delay, the first register clock delay, the second register clock delay, and a first register delay of the first register.

Abstract: Effective timing and power characterization flows are described for asynchronous circuits. Verification can be provided for both relative-timing constraints as well as performance (e.g., throughput) targets using commercially-standard STA tools. Fully-automated scripts are developed that verify all relative timing assumptions (e.g., isochronic forks) as well as the gate-level performance of any circuit designed with these templates. Library characterization can be utilized and asynchronous logic cells not found in standard-cell libraries, such as dual-rail domino logic and dynamic C-elements with staticizers, can be characterized in terms of both their timing and power. These values are a function of both input slew and output load and are preferably captured in an industry standard format, such as the Liberty™ file format, before being compatible with commercial STA tools.

Abstract: Re-budgeting connections includes detecting a budget event for a circuit design and, responsive to detecting the budget event, calculating, using a processor, a delta for a selected combinatorial circuit element of the circuit design using an incoming slack and an outgoing slack of the selected combinatorial circuit element. Using the processor, a delay budget for a connection of the selected combinatorial circuit element is adjusted using the delta responsive to detecting the budget event.

Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

Abstract: Reducing jitter in a circuit design includes selecting a plurality of circuit elements of a circuit design clocked using a first clock signal and assigning, using a processor, the plurality of circuit elements to different ones of a plurality of groups according to a balancing criterion. The circuit elements assigned to a first group of the plurality of groups are clocked using the first clock signal. The circuit elements assigned to a second group of the plurality of groups are clocked using a second clock signal different from the first clock signal.

Abstract: A method of designing a circuit, an apparatus and a structural analysis tool are disclosed. In one embodiment, the structural analysis tool includes: (1) a structural analyzer configured to apply a structural rule to the circuit design in a design environment of said design process having valid timing data and (2) a structural assessor configured to generate structural data of the circuit design based on application of the structural rule by the structural analyzer.

Abstract: A set of nets in an integrated circuit design, having a timing margin and traverse routing tiles, are identified. The set of nets are assigned a utilization metric based on the traversed routing tiles. A set of sparse nets are determined from the set of nets, based on the utilization metric of each net in the set of sparse nets. One or more target nets are selected from the set of sparse nets, based on the timing margin of the target nets. The target nets may be modified.

Abstract: Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of the final clusters are compatible with the amount of resources that will be used to process the design data.

Abstract: The present patent document relates to a method and apparatus for enabling direct memory access into a target memory subsystem of an electronic system modeled in dual abstractions while maintaining coherency. The portions of the memory subsystem shared between the first abstraction and the second abstraction are shadowed in both abstractions, allowing either abstraction to coherently access memory written by the other. Flags associated with memory pages of the memory subsystem are set to indicate which abstraction has most recently updated the memory page. Where the first abstraction is SystemC using TLM2, DMI access may be selectively enabled to facilitate faster access from SystemC, and DMI access disabled when an access from the second abstraction is detected in order to invoke coherency procedures. This allows coherency to be maintained and may enable faster software code execution where most access are DMI accesses from SystemC.

Abstract: Technology for relative timing characterization enabling use of clocked electronic design automation (EDA) tool flows is disclosed. In an example, a method can include a EDA tool identifying a relative timing constraint (RTC) of a cell in a circuit model between a point of divergence (pod) event and two point of convergence (poc) events, wherein the two poc events include a first poc event (poc0) and a second poc event (poc1). The EDA tool can generate a maximum target delay for a first poc event path between the pod event and the first poc event. The EDA tool can generate a minimum target delay for a second poc event path between the pod event and the second poc event. The EDA tool can then optimize the circuit model using the maximum target delay and the minimum target delay.

Abstract: The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation.

Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

Abstract: Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.

Abstract: A method for designing a system on a target device includes performing timing analysis at an intermediate node on a data path from a source to a destination to determine whether rise and fall skew of components on the data path could result in data not being sampled at the destination.

Abstract: A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts.

Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

Abstract: In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (qk) by minimizing a residual of a delay equation.

Abstract: A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing analysis steps includes identifying cells on and in parallel with a signal path that are driven by a same signal and determining an output transition time and a delay using the characterization data for the cell. The correcting steps includes providing further characterization data for some of the cells; correcting the output transition time for some of the cells by increasing the output transition time by an amount dependent upon the Miller capacitance for the cell and using the correction to the output transition time to correct an input transition time for a next cell; and calculating a time taken for a data signal to travel along the signal path from the delay times.

Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Abstract: A method for performing latency optimization on a system design to be implemented on a target device includes inserting a variable latency indicator in the system design at a place where latency can be varied. The system design includes pipeline registers at the place where the variable latency indicator is inserted. Latency optimization is then automatically performed on the system design, during a computer aided design flow performed by an electronic Design Automation (EDA) tool, by varying the number of the pipeline registers at the variable latency indicator to obtain optimized latency without affecting system performance of the system design.

Abstract: Systems and techniques for creating a circuit abstraction are described. During operation, an embodiment can identify a set of side loads based on a set of timing paths. According to one definition, a side load of a timing path is a circuit element that is not on the timing path (i.e., the timing path does not pass through the circuit element), but whose input is electrically connected to an output of at least one circuit element that is on the timing path. Next, the embodiment can creating the circuit abstraction by retaining circuit elements and nets on each timing path in the set of timing paths, and retaining an identifier for each side load in the set of side loads. The circuit abstraction can then be used to update timing information during one or more stages of an electronic design automation flow.

Abstract: A method comprising placing elements in a layout, performing clock tree synthesis, and performing routing. The method further comprising, in parallel with one of the clock tree synthesis or the routing, performing a footprint based optimization, substituting a footprint equivalent element in a path based on a timing slack of the path.

Abstract: The present disclosure describes a memory block manager. In some aspects a request is transmitted to a model of an IP block at a randomized time and a response is received from the model of the IP block useful to characterize behavior of the IP block when fabricated. In other aspects a response to a request is transmitted to a model of an IP block at a randomized time and a communication is received from the model of the IP block useful to characterize behavior of the fabricated IP block when fabricated.

Abstract: An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a plurality of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a stacked transistor to provide delay to the rising or falling edge of the gate. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure includes a CMOS device having a first transistor with a first input, a pair of stacked transistors having a second input, and an output.

Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.

Abstract: In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.

Abstract: A method of sensitizing a sequential circuit is described. This sensitizing generates stimuli to drive any circuit output to a predetermined value or transition. The method includes creating a directed graph of the sequential circuit. Nodes of the graphs can be topologically sorted. In one embodiment, feedback loops in the directed graph can be removed before topologically sorting the nodes. Final vectors for the sequential circuit can be generated based on the sorted nodes. Notably, the final vectors are expressed only by primary inputs to the sequential circuit. Using only primary inputs in the final vectors accurately replicates the sequential circuit under test, thereby ensuring accurate timing, power, and noise arcs are measured.