Abstract: A method for controlling crosstalk between multiple noise generating wiring tracks and a quiet wiring track by determining a parallel common run length and determining the number of threshold lengths into which the maximum parallel common run length is divided. The space between the quiet wiring track and each wiring track of the noise generating wiring tracks is determined. Multiple metal wiring track structures on one metal wiring level of and multiple metal wiring track structures on another metal wiring level of an integrated circuit that are formed as segments that have various distances between the metal wiring track structures of one wiring level and multiple metal wiring track structures of the other wiring level to form a stair-step or ladder structure that controls individually the spacing applied between multiple active noise wiring track structures and one quiet wiring track structure.

Abstract: Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

Abstract: A charging assistant system that assists charging for use of an accelerator unit, which is one or more accelerators, includes an operation amount obtaining unit, an acceleration rate estimation unit, and a use fee determination unit. For each of one or more commands input into the accelerator unit, the operation amount obtaining unit obtains the amount of operation related to execution of the command from a response output from the accelerator unit for the command. For the one or more commands input into the accelerator unit, the acceleration rate estimation unit estimates an acceleration rate on the basis of command execution time that is time required for processing of the one or more commands, and one or more amounts of operation obtained for the one or more commands respectively. The use fee determination unit determines a use fee of the accelerator unit on the basis of the estimated acceleration rate.

Abstract: The independent claims of this patent signify a concise description of embodiments. A method is provided for parallel simulation using synchronization during simulation. The method comprises executing a plurality of threads in parallel, identifying a first event block and a second event block of a circuit design, calculating a minimum delay (minDelay) based on a current simulation time, scheduled times for execution of the first event block and the second event block, and causal delays (CausalDelay) of the first event block and the second event block, and scheduling a next synchronization point based on the minimum delay, the next synchronization point being a next simulation time at which the plurality of threads synchronize to a common clock. This Abstract is not intended to limit the scope of the claims.

Abstract: An electronic device is provided. The electronic device includes a processor, and a memory storing an application program supporting a task and a database including a first path rule for performing the task. The first path rule includes a plurality of first states of the electronic device. The memory stores instructions that cause the processor to receive a voice command making a request for performing the task to transmit the voice command to an external server, to receive a second path rule including a plurality of second states of the electronic device for performing the task to execute the plurality of second states included in the second path rule, in response to the reception of the second path rule, and when an error occurs during the execution of the plurality of second states, to execute at least part of the plurality of first states included in the first path rule.

Abstract: Disclosed are methods, systems and devices for distribution of a timing signal among operational nodes of a circuit device comprising one or more circuit dies. In one implementation, a timing signal distribution network may transmit a timing signal to one or more operational circuit nodes formed on a circuit die and a clock circuit may generate a first clock signal for transmission as the timing signal to the one or more operational circuit nodes. A switch circuit may apply a second clock signal for transmission as the timing signal in lieu of the first clock signal if the circuit die is integrated at least one of the one or more other circuit dies. In another implementation, timing signals received at timing signal terminals of at least two of two or more of operational circuit nodes may be synchronized independently of the timing signal distribution network.

Abstract: Disclosed is a method and apparatus that takes timing information associated with a plurality of inputs to a cell, such as an AND-gate, within an integrated circuit (IC) design, store the timing information in a timing information register (TIR) associated with an index identifying the source of the timing information and track the source of the timing information for a predetermined number of cells through the index. The timing information in the TIRs is merged upon the index indicating that the timing information has been tracked through a predetermined number of cells.

Abstract: Techniques for verification of integrated circuit design are disclosed. A design relating to an integrated circuit is received (102). The design includes a first parameterized element and a second parameterized element (104). The first parameterized element is identified as a do-not-care (DNC) element based on usage of the first parameterized element in the design (106). A plurality of models relating to the design are generated by a processing device (110). A first value of the first parameterized element is not varied during the generating, based on the identification of the first parameterized element as a DNC element (108). A second value of the second parameterized element is varied during the generating (108).

Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to select, in the second electronic list, a path of the circuit unit that does not traverse through the net and provide a path information output that includes information associated with the path.

Abstract: A stretchable electronics generating apparatus and layout method thereof are provided. The layout method includes: establishing a layout database, wherein the layout database recodes a plurality of layout selection information respectively corresponding to a plurality of strain/stress information; detecting a layout target area to obtain a strain/stress distribution status of the layout target area; generating a wire routing information according to the strain/stress distribution status based on the layout database; and transporting the wire routing information to a manufacture device of the conductive wires for disposing a plurality of physical conductive wires on the layout target area by the manufacture device.

Abstract: A method for modeling clock gate timing for an integrated circuit may include creating a dataset having measured values of at least two design features and corresponding measured values of clock gate timing, applying an analytical framework to the dataset to determine how the design features affect the clock gate timing, measuring values of design features for a clock tree for the integrated circuit, and generating predicted values of clock gate timing for the clock tree for the integrated circuit based on how the design features of the dataset affect the clock gate timing of the dataset. The clock tree for the integrated circuit may be a second clock tree, and creating the dataset may include constructing a first clock tree, measuring values of design features of the first clock tree, and measuring corresponding values of clock gate timing of the first clock tree.

Abstract: A logic simulation electronic design automation (EDA) application, the logic can be configured to receive a circuit design of an integrated circuit (IC) chip, the circuit design comprising an imported module comprising a list of simple immediate assertions (SIAs) for the imported module, wherein the circuit design comprises a first power domain and a second power domain, wherein the first power domain controls a power state of the second power domain and the imported module is assigned to the second power domain. The logic simulation EDA application can be configured to convert, in response to user input, each SIA in the list of SIAs into a respective hybrid deferred assertion (HDA) to form a list of HDAs for the imported module and execute a simulation of the IC chip, and execution of the simulation can include execution of a plurality of time slots for a plurality of simulation cycles.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a susceptibility window. These techniques identify a set of multiple aggressors in an electronic design and determine, at a susceptibility window module stored in memory and executing in conjunction with a microprocessor of a computing node, a susceptibility window for an internal node of a victim and a timing window for the set of multiple aggressors in the electronic design. These techniques further determine a subset having at least one aggressor using at least the susceptibility window of the victim and the timing window for the set of multiple aggressors, and determine whether a glitch in the electronic design causes a violation at the internal node of the electronic design based at least in part upon the timing window and the susceptibility.

Abstract: Aspects of the invention include a method that includes performing timing analysis of an integrated circuit design to identify a critical path. The critical path fails to meet a corresponding timing requirement. The method also includes determining an amount of slack needed by the critical path. The amount of slack is an amount by which the critical path fails to meet the corresponding timing requirement. Downstream slack is created in each path of a next cycle, wherein each path of the next cycle is immediately downstream of the critical path. Slack stealing is performed to improve timing of the critical path based on the downstream slack created in each path of the next cycle.

Abstract: A controller and a method for determining a logical topology of communications resources for providing a service offering. The controller comprises a function identifier, a graph generator and a mapper. The identifier is coupled to a service level description (SLD) associating the service with at least one service type and a library of network functions (NFs) and identifies at least one NF in the library for each service type. The generator is coupled to the SLD and a library of primitive service level graphs (SLGs) representing at least one data flow between directly-coupled resource entities and associates at least one primitive SLG to each identified NF. The mapper is coupled to the service level description and a map of network infrastructure elements and maps at least one resource entity of a primitive SLG onto an available network infrastructure element.

Abstract: Methods and apparatus for creating an improved VLSI design. In-context timing analysis of a nominal VLSI design is performed and at least one assigned apportionment adjustment is determined for a sub-block of the nominal VLSI design. One or more slack adjustments are derived for at least one port of the sub-block based on the at least one apportionment adjustment and the one or more slack adjustments are applied to the in-context timing analysis to simulate a post optimization version of the sub-block. The in-context timing analysis is repeated using the one or more applied slack adjustments to generate the improved VLSI design.

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating clock information with the client configurable logic for various purposes.

Abstract: Various embodiments provide for analyzing (e.g., debugging) waveform data generated for a simulated circuit design, which can be used as part of electronic design automation (EDA). For example, where a user modifies a circuit design in a manner that impacts a next simulation run performed on the circuit design, various embodiments perform the next simulation run only on one or more portions of the circuit design affected by the user's modifications, while the results/simulated values for the rest of the circuit design are kept or reused.

Abstract: In the described examples, an electronic design automation formal verification EDA application is configured to receive an initial evaluation of a circuit design of an integrated circuit (IC) chip. The circuit design of the IC chip includes a list of properties for the IC chip, and the list of properties includes a list of assertions for the IC chip. The formal verification EDA program extracts a counter-example trace from the initial evaluation. The counter-example trace characterizes a set of signals over a plurality of cycles that reach a state in which a given assertion in the list of assertions does not hold true. The formal verification EDA program identifies a subset of signals in the counter-example trace that remain in a specific constant value over the plurality of cycles. The formal verification EDA program executes an over-constrained formal verification for the circuit design.

Abstract: Techniques for logic partition reporting for an integrated circuit (IC) design are described herein. An aspect includes generating a physical domain representation of an IC design based on a logic domain representation that includes a plurality of logic partitions, the physical domain representation including a plurality of logic clusters, each corresponding to a respective logic partition. Another aspect includes assigning a logic partition identifier corresponding to a logic partition of the plurality of logic partitions to each IC element in the physical domain representation. Another aspect includes assigning a pin name to each of the plurality of pins corresponding to the plurality of IC elements, wherein a pin name is derived based on the logic partition identifier of the IC element associated with the pin. Another aspect includes generating a timing report for a logic cluster based on the logic partition identifiers and the pin names.

Abstract: Glitch propagation is modelled during circuit design simulation by determining the input duration of each signal pulse received by a cell, utilizing the input duration to distinguish whether the input pulse is a glitch or a valid data signal pulse, assigning a cell-type-specific scaling factor value to each signal pulse identified as a scalable glitch, calculating a scheduled output duration by multiplying the scaling factor value and the input duration, and controlling the cell by scaling (i.e., limiting or reducing) the duration of a corresponding output pulse signal to the scheduled output duration. Each cell-type-specific scaling factor value corresponds to observed glitch decaying effect characteristics of corresponding cells in physical IC devices. A simulation tool automatically assigns glitch scaling modules to each cell of a circuit design, whereby the glitch scaling process is performed on each cell during simulation.

Abstract: A method of selecting relative timing constraints for enforcing in an asynchronous circuit is presented. The method includes selecting one or more sets of relative timing constraints, which include a first set of relative timing constraints, wherein the first set of relative timing constraints meets the following criteria: i) the first set is suitable for preventing the asynchronous circuit from entering two or more bad states in which a correctness property of the asynchronous circuit is violated, and ii) the first set comprises a plurality of relative timing constraints, wherein each relative timing constraint within the first set is associated with a bad state whose associated relative timing constraints comprise this relative timing constraint but no other relative timing constraint that is implied by another relative timing constraint in the first set.

Abstract: Described are techniques for reducing inaccurate values in databases by managing the order in which processes are enqueued and executed. A modification process to modify a first value in a database may be received. A precomputation process that modifies values dependent on the first value may be enqueued prior to enqueuing of the modification process to ensure that the modification process does not occur if the precomputation process fails. The modification process may be executed prior to executing the precomputation process to ensure that the precomputation process acts to modify the dependent values using the modified version of the first value.

Abstract: A method and associated system. The method includes steps of: (a) a voltage bin is selected from of a set of voltage bins, each voltage bin having a different range of frequencies based on the highest operating frequency and the lowest operating frequency specified for an integrated circuit chip not previously tested; (b) a functional path test is performed on a selected path of a set of testable data paths of the integrated circuit chip not previously tested; (c) if the integrated circuit chip fails the functional path test, then a current supply voltage value is changed to a voltage value associated with a not previously selected voltage bin; (d) a not previously tested path of the set of testable paths is selected. Steps (b), (c) and (d) are repeated until every path of the set of testable paths has been tested.

Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Abstract: The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include providing, using at least one processor, an electronic design and extracting hierarchical crossing path exception information from a hierarchical design view associated with the electronic design. Embodiments may further include transferring the hierarchical crossing path exception information to a block view associated with the electronic design and extracting a timing model based upon, at least in part, the hierarchical crossing path exception information. Embodiments may also include implementing the timing model at a top-level view associated with the electronic design.

Abstract: A system receives a circuit description and measures of intrinsic delay, intrinsic delay variation, transition time and transition time variation for each stage and determines stage delay variation of each stage. The system receives a circuit description and derate factors and determines an intrinsic delay standard deviation and a correlation coefficient. The system determines a stage delay variation of each stage based on the determined factors. The system receives parameters describing an asymmetric distribution of delay values and generates a normal distribution of delay values. The system receives measures of nominal transition time at an output and input of a wire, and transition time variation at the input of the wire and determines a transition time variation at the output of the wire. The system receives measures of an Elmore delay and a nominal delay of the wire and determines a delay variation at the output of the wire.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include providing, using a processor, an electronic design and determining one or more design violations based upon, at least in part, a structural observability filter. Embodiments may also include generating a violation trace based upon, at least in part, the one or more design violations and displaying the violation trace at a graphical user interface configured to allow a user to debug the one or more design violations. Embodiments may further include allowing the user to select at least one path to be waived at the graphical user interface and generating a new violation trace without the at least one path to be waived.

Abstract: During logic synthesis and placement optimization, designs are aggressively optimized for timing, power, and area but only the data paths are modified and the clock network is assumed to be “ideal” and fixed. The described embodiments optimize the clock network as well as the data path logic during the logic synthesis and placement optimization stages, thereby improving the overall performance of the design.

Abstract: The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.

Abstract: An indeterminate state representative of a metastable state is inserted into an output signal of a circuit representation responsive to the circuit representation receiving a metastable triggering event during a register transfer language (RTL) simulation. The simulation view of the RTL has been modified to ensure that the indeterminate state is propagated through the circuit representations regardless of the input on which the indeterminate state appears. The indeterminate state is maintained for a programmable amount of time and responsive to expiration of the amount of time, the output signal is set to a random binary value.

Abstract: A method for manufacturing an integrated circuit includes determining a static probability pattern of a circuit cell in a timing path of the integrated circuit; determining a timing delay of the circuit cell along the timing path according to the static probability pattern and a pattern based timing database, wherein the pattern based timing database indicates a plurality of reference delays of each timing arc of the circuit cell characterized in response to a plurality of input stress patterns respectively; and manufacturing the integrated circuit according to the timing delay of the circuit cell along the timing path.

Abstract: A circuit design tool places a circuit design, and after placing detects a hold violation of a path between a first flip-flop on a first IC die and a second flip-flop on a second IC die. The circuit design tool selects a window size based on an amount of the hold violation and determines an alternative path having a delay that resolves the hold violation. The alternative path is restricted to resources within an area of the window size on the second IC die. The circuit design tool replicates a plurality of instances of the alternative path in a plurality of areas of the second IC die and then routes the circuit design using the plurality of instances of the alternative path.

Abstract: A computer executable system and method analyzes a circuit design to extract a small set of signals for value collection using an emulator system. The collected signals are for specific purpose checkers such as assertions or interactive testbenches that are hard to emulate. A synthesizable monitor block is generated and added to the emulation environment to collect the signal value changes during emulation. The collected values are then used in localized logic simulation to perform the tasks that the original checkers intent to accomplish. This system leverages fast emulation speed and flexible logic simulation capabilities to perform the intended checker tasks much faster than using logic simulation alone.

Abstract: An apparatus for operation timing analysis of a semiconductor device considering multi-input switching (MIS) includes a timing input unit that generates an MIS model of each of a plurality of cells constituting a semiconductor device, and an MIS analyzer that receives timing data of each of the plurality of cells and dynamically calculates an MIS coefficient on the basis of the MIS model and the timing data.

Abstract: The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design at a debugging platform without performing a model extraction phase and mapping one or more extracted timing models (“ETM”) to one or more netlist objects associated with the electronic design. Embodiments may further include receiving, at the debugging platform, at least one timing arc specified by a source pin and a sink pin, wherein the at least one timing arc is associated with the electronic design. Embodiments may also include generating a worst timing path based upon, at least in part, the received at least one timing arc. Embodiments may further include generating characterization information for the at least one timing arc based upon, at least in part, one or more user-specified boundary conditions.

Abstract: A multi-point transmission system comprising a plurality of slave nodes (300) for transmitting data to a wireless receiver is described herein. An outer feedback loop and a plurality of inner feedback loops (100) connecting the plurality of slave nodes (300) to a master node (200) controls the timing skew of each slave node (300) using measurements provided by the slave nodes (300) to substantially synchronize the receipt of the transmitted data at the wireless receiver. In so doing, the solution presented herein provides improved multi-point control for any number of transmission points, which improves capacity, and solves the potential flow control problems associated with ultra-lean transmissions.

Abstract: A system and method to perform timing analysis in integrated circuit development involves defining an integrated circuit design as nodes representing components of the integrated circuit design that are interconnected by edges representing wires. Sequentially connected nodes define a path. Statistical variables are defined for a canonical delay model of each node and edge of the integrated circuit design and define a first set of conditions. The method includes performing a statistical static timing analysis to obtain an arrival time at each node as a sum of the canonical delay models for nodes and edges that precede the node in the path of the node, obtaining a projected arrival time at a second set of conditions for the node by scaling the arrival time for the node using scale factors that represent the second set of conditions and using a transformation matrix, and providing the integrated circuit design for fabrication.

Abstract: A set of multi-corner multimode (MCMM) databases that correspond to a set of working scenarios are accessed. A full timing update on the set of MCMM databases, for the set of working scenarios, is applied. A graph based analysis (GBA) timing calibration is performed on the databases, for the set of working scenarios to obtain a set of GBA-calibrated databases. Multiphase optimizations on the set of GBA-calibrated databases are iteratively performed to generate a set of optimized databases, including: performing a phase-specific optimization on the set of GBA-calibrated database to obtain an improved set of databases, and recalibrating GBA timing on the set of improved databases prior to a next phase-specific optimization.

Abstract: Local retiming for a circuit design includes determining, using computer hardware, a load of a synchronous circuit element within the circuit design tagged for forward retiming, traversing, using the computer hardware, each input of the load backward through the circuit design until a sequential circuit element or a primary input is reached, and adding, using the computer hardware, each synchronous circuit element encountered in the traversing to a forward retiming list. In response to determining that forward retiming criteria is met for the forward retiming list, the computer hardware modifies the circuit design by creating a new synchronous circuit element at an output of the load.

Abstract: A system and method to perform an ordered write of timing analysis data obtained in parallel during integrated circuit development process two or more data sets with two or more processors in parallel. The two or more data sets result from timing analysis and correspond with two or more paths, each path includes a set of interconnected components, and the processing includes collecting and formatting information to obtain the timing analysis data associated with each of the two or more paths. The method includes determining a next timing analysis data using an ordered list of the two or more data sets that correspond with the timing analysis data, consulting an availability vector to determine whether the next timing analysis data is available, and writing the next timing analysis data as soon as it is available prior to completion of the processing of others of the two or more data sets.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design.

Abstract: Various embodiments describe clustering of nodes of a directed graph based on the oriented edges of the directed graph and on a set of rules. In an example, each node represents a device identifier associated with a computing device. The device identifier facilitates an online activity provided by a computing service. A computing system accesses the directed graph and generates clusters that contain subsets of the nodes by at least iteratively updating the directed graph based on the set of rules. The set of rules specifies (i) removal of leaf nodes from the directed graph, (ii) reconnection of nodes that form a chain in the directed graph, and (iii) reconnection of nodes that form a split in the directed graph. The computing system also associates a client profile with a subset of the nodes contained in a cluster from the clusters.

Abstract: A sampling circuit automatically resamples the data from another timing domain until the sampled data is represented correctly in the new domain by assuring that no metastable states exist. If a metastable state exists, a sampling signal recirculates through the sampling circuit until the metastable state no longer exists. A comparison of input data to sampled data is used to determine the existence of a metastable state.

Abstract: Disclosed are techniques that can be used in a semiconductor chip to determine performance such as timing performance. Among other features, supply voltages and clock rates may be adjusted to accommodate the operating temperature and to compensate for the processing variations that occurred when that chip was produced, or may occur as the chip is used. The techniques include determining a series of variables that affect performance, determining the sensitivity of timing paths in the circuit to each variable, duplicating the most sensitive paths. A novel sensor circuit is produced that includes the sensitive paths, which can be used to determine when the chip is performing as required and when it is not, and adjusting one or more supply voltages and/or clock rates in a static or real time manner when the circuit is not performing as required.

Abstract: Verifying a circuit design may include, in response to modification of the circuit design involving at least one of inserting or removing a flip-flop, determining, using computer hardware, latency change values for pins of components of the circuit design, determining, using the computer hardware, total latency for the pins of the components of the circuit design based, at least in part, upon the latency change values, and comparing, using the computer hardware, total latency of the pins of the components of the circuit design. Verifying the circuit design may also include detecting, using the computer hardware, a latency error within the circuit design based upon the comparing and generating, using the computer hardware, a notification of the latency error in the circuit design, wherein the notification specifies a type of the latency error detected.

Abstract: Embodiments of the present invention provides methods, computer program products, and a system for processing hierarchical references for a formal equivalence check. In certain embodiments, hierarchical references of a first design are identified as functionally equivalent to hierarchical references of a second design. Value outputs of the first design can be compared to the value outputs of the second design to determine whether the value outputs of the respective designs match.

Abstract: In some examples, a system for modifying circuit can include a processor to detect a previous routed top level circuit design that was proven to close timing within a predetermined range and congestion below a threshold level. The processor can also detect a new pin to be added to a new circuit design and detect user input indicating a bounding box corresponding to a new macro boundary in the previous routed top level circuit design. Additionally, the processor can identify a location of a net in the previous circuit design corresponding to the new pin, wherein the new pin is placed at an intersection between the net and the bounding box. Furthermore, the processor can manufacture a circuit based on the previous circuit design and the placement of the new pin at the intersection between the net and the bounding box.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition.

Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.