Abstract: Provided are an apparatus and method for OpenVG API translation, a mobile terminal comprising the translation apparatus, and a record medium storing the translation program. The apparatus comprises a data parsing unit, an OpenVG API script creating unit, and a raster image data output unit. The data parsing unit parses SVG format data depending on a data attribute. The OpenVG API script creating unit extracts an OpenVG API format syntax and creates an OpenVG API script. The raster image data output unit creates and outputs raster image data associated with the created OpenVG API script.

Abstract: A system processes a reified generic. The system includes a memory device to store programming code in a first language, the programming code including a definition and an invocation of an interface method. The system also includes a processor to translate the programming code from the first language to a second language, generate a definition of a general dispatch method, generate definitions of special dispatch methods, each of the special dispatch methods corresponding to each primitive return type of the interface method, and generate an invocation of either the general dispatch method or one of the special dispatch methods based on a return type of the interface method.

Abstract: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.

Abstract: Concepts and technologies are described herein for extending the behavior of a software development tool. An extension can be accessed and consumed by a software development tool to configure the software development tool to perform an operation in an extended mode. In one example, an extension can extend a compiler based on the input source code. In one configuration, the compiler extension can provide a compiler with one or more runtime semantics of various source code elements for a particular programming language. The compiler can access an extensions list to determine if the compiler is to perform a compilation operation on a particular source code element or logical unit in an extended mode.

Abstract: A processor core includes a processor to execute a first translated instruction translated from a first instruction stored in first page of a memory. The processor also includes a translation indicator agent (XTBA) to store a first translation indicator that is read from a physical map (PhysMap) in the memory. In an embodiment, the first translation indicator is to indicate whether the first page has been modified after the first instruction is translated. Other embodiments are described as claimed.

Abstract: A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™ bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt. A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java™ bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.

Abstract: Methods, apparatuses and storage medium associated with ISA bridging with support for virtual functions, are disclosed. In embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution, to provide an ISA bridging layer to the target device to facilitate a library service of a library of the target device to call a virtual function of the library, while servicing an application operating on the target device, where the application has an overriding implementation. The ISA bridging layer may include a loader configured to load the application for execution, and as part of loading the application, detect the virtual function and modify a virtual function table of the application to enable the call. Other embodiments may be disclosed or claimed.

Abstract: A method, system, and article of manufacture are disclosed for transforming a definition of a process for delivering a service on a specified computing device. This service process definition is comprised of computer readable code. The method comprises the steps of expressing a given set of assumptions in a computer readable code; and transforming the definition by using a processing unit to apply the assumptions to the definition of the process to change the way in which the process operates. The definition of the process may be transformed by using factors relating to the specific context in or for which the definition is executed. Also, the definition may be transformed by identifying, in a flow diagram for the process, flows to which the assumptions apply, and applying program rewriting techniques to those identified flows.

Abstract: Methods and apparatus for preserving precise exceptions in code reordering by using control speculation are disclosed. A disclosed system uses a control speculation module to reorder instructions within an application program and preserve precise exceptions. Instructions, excepting and non-excepting, can be reordered by the control speculation module if the instructions meet certain conditions. When an excepting instruction is reordered, a check instruction is inserted into the program execution path and a recovery block is generated. The check instruction determines if the reordered excepting instruction actually needs to generate an exception. The recovery block contains instructions to revert the effects of code reordering. If the check instruction detects the need for an exception, the recovery block is executed to restore the architectural state of the processor and the exception is handled.

Abstract: In one embodiment, a method comprises receiving an application that describes functions according to a prescribed symbol manipulation language, the prescribed symbol manipulation language a non-Turing complete language that does not permit partial functions and describes the functions independent of any attribute of any computing system; identifying, in the application, a distribution annotation that identifies a candidate element in the application, the candidate element configured for execution in a distributed computing operation by a distributed computing system comprising two or more distributed computing devices; generating one or more variants of the application based on executing a nondestructive transformation of the application relative to prescribed equality axioms, at least one of the variants containing a corresponding semantically-equivalent variation of the candidate element; and selecting one of the variants as an optimization for execution of the application by the distributed computing syste

Abstract: A compiling method and a processor using the same are provided. The compiling method includes simulating a first program code which includes at least one first operation command to generate a first operation result, compiling the first program code to generate a second program code which includes at least one second operation command, simulating the second program code to generate a second operation result, and comparing the first operation result with the second operation result to verify whether the second program code is valid.

Abstract: A system interface of a processing system receives an indication to initiate configuration of a programmable system. A processing device coupled to the system interface and associated with an integrated development environment, responsive to the indication, translates a hardware description code into one or more configuration files specific to the programmable system, the hardware description code to describe circuitry in the programmable system. The processing device further generates program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configures the programmable system to implement the circuitry according to the configuration files and the program code. In addition, the processing device debugs the programmable system as configured by the configuration files and the program code.

Abstract: Methods and devices for thwarting code and control flow based attacks on software. The source code of a subject piece of software is automatically divided into basic blocks of logic. Selected basic blocks are amended so that their outputs are extended. Similarly, other basic blocks are amended such that their inputs are correspondingly extended. The amendments increase or create dependencies between basic blocks such that tampering with one basic block's code causes other basic blocks to malfunction when executed.

Abstract: A system and method accepts source code for one or more procedures and, for those procedures flagged as being remotely callable, generates communication code and a description that allows the code to be remotely callable via a server using a variety of formats, such as conventional web services formats.

Abstract: Configuring integration capabilities includes: receiving a configuration stencil that is a configuration artifact of a message flow, the configuration stencil comprising at least one configuration point, the configuration point currently having no assigned value, and at least one constraint for the configuration point, the constraint being a rule or type for a value to be assigned to the configuration point; receiving, using one or more processors, input comprising at least one configuration point value for the configuration point, the configuration point value having been selected based on first and second systems to be integrated using the message flow; determining whether the received configuration point value violates the constraint and if so requesting another configuration point value from the input; and generating a configuration stencil instance based on the configuration stencil and the input, the configuration stencil instance representing the message flow in an integration of the first and second s

Abstract: The disclosed system provides a transformation-based implementation of forward-mode and reverse-mode automatic differentiation as a built-in, first-class function in a functional programming language. Each of these constructs imposes only a small constant factor of the computational burden (time) of the function itself, and the forward construct has the same properties in terms of space. The functions can be applied to any function, including those involving derivatives and nested closures.

Abstract: Techniques for representing a program are provided. The techniques include creating one or more sub-variables for each of one or more variables in the program, and maintaining a single size of each of the one or more variables throughout a life-span of each of the one or more variables. Additionally, techniques for performing register allocation are also provided. The techniques include representing bit-width information of each of one or more variables in a powers-of-two representation, wherein the one or more variables comprise one or more variables in a program, coalescing the one or more variables, packing the one or more coalesced variables, and using the one or more packed variables to perform register allocation.

Abstract: Methods and an apparatus for dynamic best fit compilation of mixed mode instructions are provided. In one embodiment, a provided method includes receiving a non-native software instruction at a device, generating a first native software instruction from a first instruction set based on the non-native software instruction, the generation of the first native software instruction occurring at the device, executing the first native software instruction at the device, generating a second native software instruction from a second instruction set based on the non-native software instruction, the generation of the second native software instruction occurring at the device, and executing the second native software instruction at the device.

Abstract: The system and methods described herein may be used to detect and tolerate atomicity violations between concurrent code blocks and/or to generate code that is executable to detect and tolerate such violations. A compiler may transform program code in which the potential for atomicity violations exists into alternate code that tolerates these potential violations. For example, the compiler may inflate critical sections, transform non-critical sections into critical sections, or coalesce multiple critical sections into a single critical section. The techniques described herein may utilize an auxiliary lock state for locks on critical sections to enable detection of atomicity violations in program code by enabling the system to distinguish between program points at which lock acquisition and release operations appeared in the original program, and the points at which these operations actually occur when executing the transformed program code.

Abstract: Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.

Abstract: Interactive iterative program parallelization based on dynamic feedback program parallelization, in one aspect, may identify a ranked list of one or more candidate pieces of code each with one or more source refactorings that can be applied to parallelize the code, apply at least one of the one or more refactorings to create a revised code, and determine performance data associated with the revised code. The performance data may be used to make decisions on identifying next possible ranked list of refactorings.

Abstract: One embodiment of the present invention provides a system that improves program performance by enregistering memory locations. During operation, the system receives program object code which has been generated to use a specified number of registers that are available for a given target hardware implementation. Next, the system translates this object code to execute on a second hardware implementation which includes more registers than the first hardware implementation. The system uses these additional registers to improve the performance of the translated object code for the second hardware implementation. More specifically, the system identifies a memory access in the object code, and then rewrites an instruction associated with this memory access to access an available register instead of the original target memory location. To preserve program semantics, the system subsequently moderates accesses to the memory location to ensure that no threads access a stale value in the enregistered memory location.

Abstract: A system and method of translating functions of a program. In one embodiment, the system includes: (1) a local-scope variable identifier operable to identify local-scope variables employed in the at least some of the functions as being either thread-shared local-scope variables or thread-private local-scope variables and (2) a function translator associated with the local-scope variable identifier and operable to translate the at least some of the functions to cause thread-shared memory to be employed to store the thread-shared local-scope variables and thread-private memory to be employed to store the thread-private local-scope variables.

Abstract: A preparsers tool is provided for converting Software Communications Architecture (SCA) Extensible Markup Language (XML) files into Common Object Request Broker Architect (CORBA) structures usable by a Software Communications Architect (SCA) Core Framework (CF). The preparsers tool retrieves a set of target environment implementation definitions (TEID) that define at least one characteristic of a target environment to which a CORBA Common Data Representation (CDR) file is provided. For each component in the target environment, one or more dependencies are merged into an implementation device dependencies list that comprises visible device dependencies and external device dependencies. The parsed set of XML files is converted into a CORBA structure type, the conversion based at least in part on the TEID, such that the conversion of the parsed set of XML files results in a CORBA structure having a type and precedence order that is correct for the target environment.

Abstract: An information processing apparatus having an operating system installed thereon is provided with a help file manager. The help file manager obtains language type information indicating a language type currently set for the operating system, obtains one of a plurality of help files that corresponds to the obtained language type information from a resource file, and expands the obtained help file into an expanded help file to store the expanded help file at the information processing apparatus. The information processing apparatus displays a help window generated based on the expanded help file that is stored.

Abstract: The compiled code of a computer program is stored in multiple pieces within a database. Each piece is optionally stored within a separate data record. Execution of the computer program includes using database queries to retrieve pieces of the compiled code for execution. The database and associated database management logic are used to provide numerous advantages in execution and management of the computer program. For example, in some embodiments, database queries are used to help facilitate program flow logic. In another example, database queries are based on a command line or universal resource locator. These queries may be used to select functionality of a computer program in response to the command line or universal resource locator.

Abstract: A graphical program is analyzed, where the graphical program includes an I/O interface including one or more ordered parameters for providing input to or receiving output from the graphical program. A function is generated in a textual programming language based on the analyzing, where the function implements the functionality of the graphical program, and includes a textual function I/O interface with the one or more ordered parameters of the I/O interface of the graphical program. User input is received specifying a modified textual function I/O interface that differs from the textual function I/O interface. A wrapper for the function is generated with the modified textual function I/O interface, where the wrapper includes the function, and where during execution the wrapper receives or outputs values in accordance with the modified textual function I/O interface, and provides values to or receives values from the function via the textual function I/O interface.

Abstract: A code verification tool verifies that code generated from a model represents all of the functionality of the model and does not contain any unintended functionality. The code verification tool may receive for examination a model or an intermediate representation (IR) of the model and the generated code or an intermediate representation of the generated code. The code verification tool may create further intermediate representations of the model and/or the generated code in order to compare the functionality presented in both.

Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for identifying matching elements between a source model and a target model comprising receiving a source model and a target model, the source model and the target model each being stored in computer-readable memory; processing the source model and the target model to generate a plurality of similarity values, each similarity value being associated with an element of the source model and an element of the target model; generating a similarity value construct based on the plurality of similarity values and elements of the source model and the target model; and identifying matching elements between the source model and the target model based on the similarity value construct.

Abstract: A model is provided for transforming a program with a priori given class hierarchy that is induced by inheritance. An inheritance remover is configured to remove inheritance from a given program to produce an analysis-friendly program which does not include virtual-function pointer tables and runtime libraries associated with inheritance-related operations. The analysis-friendly program preserves the semantics of the given program with respect to a given class hierarchy. A clarifier is configured to identify implicit expressions and function calls and transform the given program into at least one intermediate program having explicit expressions and function calls.

Abstract: A system, method, and computer readable medium. A method includes loading a first language definition and a second language definition. The method includes loading a transformation definition corresponding to the first language definition and the second language definition and loading a validation rule definition. The method includes applying the validation rule definition to the transformation definition to produce a validation result indicating whether the transformation definition produces a valid transformation between the first language definition and the second language definition. The method includes storing the validation result.

Abstract: A computer implemented testing methodology employing a scenario-driven modeling of specific instances of bug patterns that commonly occur in concurrent programs which encodes these instances in an SMT-based symbolic analysis. Such modeling and encoding advantageously allow the symbolic analysis framework to focus on real bugs, thereby allowing effective utilization of resources. Experimentation determined a number of previously unknown bugs in public benchmarks and advantageously scenario-specific modeling and encoding improves the scalability of symbolic technique and, therefore, improves overall quality of concurrency testing.

Abstract: Described are techniques for generating a parser. A graphical representation of a finite state machine is provided for determining whether an input is syntactically valid in accordance with a syntax represented by the graphical representation. A second representation is generated which corresponds to the graphical representation. Using the second representation, a parser is generated for parsing an input. The parser determines whether the input is syntactically valid in accordance with the syntax.

Abstract: A preparser tool is provided for converting Software Communications Architecture (SCA) Extensible Markup Language (XML) files into Common Object Request Broker Architecture (CORBA) structures usable by an SCA Core Framework (CF) and comprises a CF_PreParsers interface definition language (IDL) and a first preparser. The CF_IDL is configured to be in operable communication with an XML parser and with at least a first type of preparser. The first type of preparser is in operable communication with the CF_PreParsers IDL, is associated with a first type of descriptor for the CF, and is configured to call the XML parser to request parsing of a first set of first XML files, convert the first parsed set of first XML files into a first CORBA structure type, encode the first CORBA structure type into a first CORBA Common Data Representation (CDR) file; and write the first CORBA CDR file as a first octet sequence.

Abstract: Systems, methods, and computer-readable media for optimizing emulated fixed-function and programmable graphics operations are provided. Data comprising fixed function and programmable states for an image or scenario to be rendered is received. The data for the image is translated into operations. One or more optimizations are applied to the operations. The optimized operations are implemented to render the scenario.

Abstract: A computing device programmed with an extensible framework that accepts one or more mark-up language parsers and/or generators, each implemented as plug-ins to the framework, with different plug-ins enabling different kinds of mark up languages to be handled by the device. In this way, the client is no longer tied to a single kind of parser or generator; it can operate with any different kind of parser compatible with the intermediary layer, yet it remains far simpler that prior art clients that are hard-coded to operate directly with several different kinds of parsers and generators.

Abstract: Methods and systems for executing a code stream of non-native binary code on a computing system are disclosed. One method includes parsing the code stream to detect a plurality of elements including one or more branch destinations, and traversing the code stream to detect a plurality of non-native operators. The method also includes executing a pattern matching algorithm against the plurality of non-native operators to find combinations of two or more non-native operators that do not span across a detected branch destination and that correspond to one or more target operators executable by the computing system. The method further includes generating a second code stream executable on the computing system including the one or more target operators.

Abstract: A virtual execution system that is configured to be used in a resource-constrained device. The resource-constrained device includes an operating system and an application program that includes instructions. The virtual execution system includes an execution engine that is configured to execute the application program, and to facilitate the compatibility of the application program with the operating system. Non-functional aspects characterize the instructions and the operating system. The execution engine has access to the non-functional aspects, and implements improvements during the execution of the application program based on the non-functional aspects.

Abstract: A mechanism for providing automatic interoperation between native objects created in a single language computing environment and objects created in external virtual machines and foreign class systems is discussed. Embodiments of the present invention provides a class definition syntax for objects created in the single language computing environment that provides the ability to directly subclass external classes and implement external interfaces. One embodiment of the present invention also permits a foreign object system to instantiate native objects and to create foreign subclasses of native classes. More specifically, one embodiment of the present invention provides bidirectional mapping between metadata associated with objects created with each of a plurality of different types of foreign object systems and metadata created in a form supported by the single language computing environment.

Abstract: Automated refactorings as implemented in modern IDEs for Java usually make no special provisions for concurrent code. Thus, refactored programs may exhibit unexpected new concurrent behaviors. We analyze the types of such behavioral changes caused by current refactoring engines and develop techniques to make them behavior-preserving, ranging from simple techniques to deal with concurrency-related language constructs to a framework that computes and tracks synchronization dependencies. By basing our development directly on the Java Memory Model we can state and prove precise correctness results about refactoring concurrent programs. We show that a broad range of refactorings are not influenced by concurrency at all, whereas other important refactorings can be made behavior-preserving for correctly synchronized programs by using our framework. Experience with a prototype implementation shows that our techniques are easy to implement and require only minimal changes to existing refactoring engines.

Abstract: A method and apparatus for protecting computer systems from a virus are disclosed. For example, the present method protects against a class of computer viruses that replicate themselves by making use of the knowledge that a specific piece of software code or data component that always resides at a specific relative memory location in RAM for all instances of the software. In one embodiment, the present method divides a software application into a plurality of components and creates distinct copies of the software application by varying the locations of the components when loaded onto a computer system.

Abstract: A method of processing natural language assertions (NLAs) can include identifying an NLA and then translating that NLA into a verification language assertion (VLA) using a natural language parser (NLP) and synthesis techniques. This VLA can be translated into an interpreted NLA (NLA*) using a VLA parser and pattern matching techniques. At this point, the process can allow user review of the NLA* and the NLA. When the user determines that the NLA* and the NLA are the same or have insignificant difference, then verification can be performed using the VLA. The results of the verification can then be back annotated on the NLA. In one fully-automatic embodiment, in addition to comparing the NLA and the NLA*, the VLA and a VLA* (generated from the NLA*) can be compared, thereby providing yet another test of accuracy for the user during verification.

Abstract: A mechanism is provided for detecting pattern occurrences utilizing a transformation software application on a computer. An input model is received in which the transformation software application is configured to detect model elements playing pattern roles, and report them in an output model (conforming to new pattern result language). A pattern specification is configured as a declarative transformation relation that is used by the transformation software application to detect pattern occurrences in the input model. Pattern occurrences are reported in the output model, where the pattern occurrences are instances of the pattern detected in the input model.

Abstract: Various embodiments provide a mechanism by which a driver writer can describe the operation set of a particular driver using an intermediary representation, such as an XML. A generation tool can then process the intermediary representation and generate client code and device driver code to support these operations. In one or more embodiments, driver operation and associated elements that support the driver operation can be described according to a customized schema that is specific to the operation of the particular device driver.

Abstract: A system and method for generating test code software utilized by a test system for testing a circuit card assembly is provided. A translator provides an automatic translation of a test code from a first computer language to a second computer language. One or more pinmap documents are provided to map the pins of the circuit card assembly.

Abstract: An improved technique of providing computer code to a set of client computers is disclosed. In the improved technique, a set of files is generated, each file in the set of files including computer code configured to be read by an interpreter on each client computer, the computer code in each file including a set of functions, each function in the set of functions having a name, the name of a function in the set of functions in a first file in the set of files differing from the name of a corresponding function in the set of functions in a second file in the set of files, the computer code in the first file and the computer code in the second file being constructed and arranged to produce functionally equivalent sets of computer instructions when run through the interpreter on each client computer.

Abstract: A method and an apparatus that instructs a compiler server to build or otherwise obtain a compiled code corresponding to a compilation request received from an application are described. The compiler server may be configured to compile source codes for a plurality of independent applications, each running in a separate process, using a plurality of independent compilers, each running in a separate compiler process. A search may be performed in a cache for a compiled code that satisfies a compilation request received from an application. A reply message including the compiled code can be provided for the application, wherein the compiled code is compiled in direct response to the request, or is obtained from the cache if the search identifies in the cache the compiled code that satisfies the compilation request.

Abstract: A computer-implemented method, system, and computer program product for detecting and monitoring server side state during the scanning of a web application. The method includes: monitoring executed code of the web application while scanning the web application; retrieving code coverage information from the monitoring of the executed code and retrieving scanning information from the scanning of the web application; correlating the code coverage information with the scanning information; and determining a change in the server side state based on the correlation. The system includes one or more devices that executes the steps of the method. The computer program products includes computer program instructions stored on a computer readable storage medium, where the instructions, when executed, will cause a computer to perform the steps of the methods.

Abstract: A system and method for generating test code software utilized by a test system for testing a circuit card assembly is provided. A translator provides an automatic translation of a test code from a first computer language to a second computer language. One or more pinmap documents are provided to map the pins of the circuit card assembly.

Abstract: A program-converting module for a multi-axis cooperated machine and a program-converting method. Machining programs and mechanism data of a plurality of first machines are input to a first input module. Mechanism data of a plurality of second machines are input to a second input unit. A setting unit sets at least one of the first machines to be a source machine, and sets one of the second machines to be a target machine. A conversion unit uses a kinematical method to convert the machining program of the source machine into a machining program applicable to the target machine based on the mechanism data of the source and target machines, without requiring CAD/CAM software.