Abstract: It is an object of the present invention to provide an information processing device and a memory management method that enable execution of memory management processing for simultaneously starting up two types of applications. During execution of an application in the form of a Java application, the application starts up another an application in the form of Flash data, and then a native software in the form of a Flash Player causes a memory management unit to secures a prescribed memory area from a memory area for the native software. A native software then starts up the other application using the secured memory area.

Abstract: A real-time operating system (RTOS) for use with minimal-memory controllers has a kernel for managing task execution, including context switching, a plurality of defined tasks, individual ones of the tasks having subroutines callable in nested levels for accomplishing tasks. In the RTOS context switching is constrained to occur only at task level, and cannot occur at any lower sub-routine level. This system can operate with a single call . . . return stack, saving memory requirement. The single stack can be implemented as either a general-purpose stack or as a hardware call . . . return stack. In other embodiments novel methods are taught for generating return addresses, and for using timing functions in a RTOS.

Abstract: An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device 100 includes: an instruction execution circuit 101 capable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuit 102 instructing the instruction execution circuit 101 to switch a thread mode.

Abstract: In a system that executes a program by simultaneously running a plurality of threads, the entries in a CSE 17 are divided into groups of the number of threads. Each group allocates continuous storage areas, and holds the initial position of the entry in each group as a pointer in a point register selection circuit 35. The pointer is associated with each thread. A thread selection circuit 36 selects one thread for determining an execution completion of an instruction, allows an entry selection circuit 37 to store a copy of the entry of the thread from the CSE 17 in the completion target entry 38, allows a completion determination unit 39 to perform a completion determination and update programmable resources. A thread is selected without a bias toward one thread.

Abstract: A multiplexed hierarchical array of interrupt controllers is configured to enable low latency task switching of a processor. The hierarchical array comprises a plurality of interrupt controllers coupled to a root interrupt controller. For each task that the processor is configured to execute, a corresponding interrupt controller is provided. To switch the processor to a task, the corresponding interrupt controller signals the root interrupt controller which, in turn, sends an interrupt and a Task Identifier to the processor. The root interrupt controller also cooperates with an access multiplexer/demultiplexer to select the corresponding interrupt controller for communication with the processor. By providing interrupt controller selection as well as task identification, the hierarchical array offloads arbitration and context switching overhead from the processor. That is, in response to the interrupt, the processor switches to the identified task and may access a memory address space dedicated to the task.

Abstract: A controlling process may enable or disable the launching of a predicated process that has already been queued for launching, e.g. via a pushbuffer. The controlling process generates a report so that launching of the predicated process is enabled or disabled based on the report. The predicate may be global in application to enable or disable all subsequent launch commands. Alternatively, the predicate may be specific to one or more predicated processes. In an embodiment with a central processing unit (CPU) coupled to a graphics processing unit (GPU), the CPU may generate the controlling process that enables or disables the launch of the predicated process. Alternatively or additionally, the GPU may generate the controlling process that enables or disables the launch of the predicated process.

Abstract: An apparatus and method capable of performing multiple tasks in a portable terminal are provided, in which menu functions of the portable terminal can be implemented while continuing to play the music. The multi-tasking apparatus includes a controller for performing controlling to implement at least one menu function while playing a music file and a display unit for displaying an indication that the music file is being played during the implementation of the menu function.

Abstract: Methods and apparatuses provide for referencing thread local variables (TLVs) with techniques such as stack address mapping. A method may involve a head pointer that points to a set of thread local variables (TLVs) of a thread. A method according to one embodiment may include an operation for storing the head pointer in a global data structure in a user space of a processing system. The head pointer may subsequently be retrieved from the global data structure and used to access one or more TLVs associated with the thread. In one embodiment, the head pointer is retrieved without executing any kernel system calls. In an example embodiment, the head pointer is stored in a global array, and a stack address for the thread is used to derive an index into the array. Other embodiments are described and claimed.

Abstract: Disclosed is a computer implemented method, computer program product, and apparatus for generating diagnostic data for a thread. A service processor may begin by executing the computer usable program code to allocate a first thread to a monitoring function. The service processor determines if a second thread is running, wherein the second thread is associated with an operation. The service processor obtains an object pointer from a list of running threads, wherein the object pointer references a time data structure associated with the second thread, the time data structure comprising a maximum running time interval and a check time. The service processor calculates the check time as a maximum running time interval added to an initially sampled timestamp. The service processor determines if a current time exceeds the check time. In addition, the service processor generates an error log, responsive to a determination that the current time exceeds the check time.

Abstract: A computing resource allocation system allocates hardware and software resources among employees, based upon a combination of the employee level, job function, and demonstrated workstation performance within the context of the job requirements of the employee and usage patterns of the computing resource. The system collects various performance data for computing resources. A set of policy rules is applied to the collected performance data and processed by the present system. Consequently, the present system automatically identifies and prioritizes employees in need of technology upgrades and replacements based on business needs and available resources. Performance data of a computing resource is captured and transmitted to a central collection agency. From the performance data, the present system determines when partial upgrades, such as memory additions or faster adapters are appropriate based on system performance or errors.

Abstract: A system and method for scheduling threads in a Simultaneous Multithreading (SMT) processor environment utilizing multiple SMT processors is provided. Poor performing threads that are being run on each of the SMT processors are identified. After being identified, the poor performing threads are moved to a different SMT processor. Data is captured regarding the performance of threads. In one embodiment, this data includes each threads' CPI value. When a thread is moved, data regarding the thread and its performance at the time it was moved is recorded along with a timestamp. The data regarding previous moves is used to determine whether a thread's performance is improved following the move.

Abstract: In one embodiment, jobs requiring short processing time are given preference over jobs requiring long processing time by processing to completion all jobs for the first N seconds of the job. Jobs requiring longer than N seconds to complete are given a lower priority than a newly arriving job can and continue being processed, but are subject to reduction in resources by new jobs as each new job arrives.

Abstract: A multitasking processor and a task switching method thereof are provided. The task switching method includes following steps. A first task is executed by the multitasking processor, wherein the first task contains a plurality of switching-point instructions. An interrupt event occurs. Accordingly, the multitasking processor temporarily stops executing the first task and starts to execute a second task. The multitasking processor executes a handling process of the interrupt event and sets a switching flag. After finishing the handling process of the interrupt event, the multitasking processor does not perform task switching but continues to execute the first task, and the multitasking processor only performs task switching to execute the second task when it reaches a switching-point instruction in the first task.

Abstract: A heap organization for a multitasking virtual machine is described. The heap organization may comprise an execution engine to concurrently execute a plurality of tasks and a plurality of heaps coupled to the execution engine. In some embodiments, the plurality of heaps may comprise a system heap and a task heap separated from the system heap. The system heap may store system data accessible by the plurality of tasks. The task heap may store task data only accessible by one task of the plurality of tasks.

Abstract: Methods, systems, and media are disclosed for autonomic system tuning of simultaneous multithreading (“SMT”). In one embodiment, the method for autonomic tuning of at least one SMT setting for an optimized processing, such as via throughput, latency, and power consumption, of a workload on a computer system includes calling, by a kernel, an SMT scheduler having at least one hook into a genetic library. Further, the method includes obtaining, by the SMT scheduler through the at least one hook, genetic data from the genetic library for the optimized processing of the workload. Further still, the method includes tuning, by the SMT scheduler and based on the obtaining, the at least one SMT setting for at least one cpu of the computer system.

Abstract: A method includes, in a network, representing a first request from a first user as a first ClientUser, assigning the first ClientUser to a ServerSession, the ServerSession having one or more ClientSessions, each of the ClientSessions allowing a server to have a single session for all first user requests from the server. The method includes, in a client/server network, providing a session that can be common to all connections to a web server by a user.

Abstract: A data processing system in a multi-tasking environment is provided. The data processing system comprises at least one processing unit (1) for an interleaved processing of the multiple tasks. Each of the multiple tasks comprises available data associated to it and a corresponding waiting time. In addition, a task scheduler (2) is provided for scheduling the multiple tasks to be processed by the at least one processing unit (1). The task scheduling is performed based on the amount of data available for the one of the multiple tasks and based on the waiting time of the data to get processed by that task.

Abstract: A multitasking virtual machine is described. The multitasking virtual machine may comprise an execution engine to concurrently execute a plurality of tasks. The multitasking virtual machine may further comprise a heap organization coupled to the execution engine. The heap organization may comprise a system heap to store system data accessible by the plurality of tasks; and a plurality of task heaps. Each of the plurality of task heaps may be assigned to each of the plurality of tasks to store task data accessible by the assigned task. The multitasking virtual machine may further comprise a heap manager to manage the heap organization. The heap manager may comprise a heap size controller to control heap size of the system heap.

Abstract: Illustrative embodiments provide a computer implemented method, a data processing system and a computer program product for lock contention reduction. In one illustrative embodiment, the computer implemented method provides a lock to an active thread, increments a lock counter, receives a request to de-schedule the active thread, and determines whether the lock is held by the active thread. The computer implemented method, responsive to a determination that the lock is held by the active thread, adds a first pre-determined amount to a time slice of the active thread.

Abstract: The invention relates to a real time-capable control system essentially consisting of a software-implemented SPS application that exchanges the output data and input data by means of a field bus connecting module. The SPS application runs on a computer under the control of a non-real time-capable operating system, whereby the full functionality of the non-real-time-capable operating system is maintained. The real time capability makes the field bus connecting module ready for use, and the data are exchanged between the field bus connecting module and the SPS application via the host interface located inside the computer.

Abstract: An operating system in a shared processor logical partitioned data processing system is given a target percentage. The hypervisor assigns the target processor percentage to the operating system. The operating system also has a predetermined time slice to allot to threads in a multitasking environment. The operating system adjusts the time slice based on a per-virtual-processor percentage.

Abstract: A method, apparatus, and computer instructions for executing a handler in a multi-threaded process handling a number of threads in a manner that avoids deadlocks. A value equal to the number of threads executing in the data processing system is set. The value is decremented each time a lock count for a thread within the number of threads is zero. A thread within the number of threads is suspended if the thread requests a lock and has a lock count of zero. A procedure, such as a handler, is executed in response to all of the threads within the number of threads having no locks.

Abstract: A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets.

Abstract: The invention concerns a method for synchronizing the execution of at least one critical code section (C1) by at least one of a plurality of concurrent tasks (S1, Sn) of an application (4), the application (4) running on an operating system (5) providing cooperative multitasking, the critical code section (C1) being restricted to execution by only a limited number of the plurality of tasks (S1, Sn), the method comprising at least the following steps performed by at least one of the tasks (S1, Sn): a. testing (F11) at least one variable (Mx) associated to the at least one critical code section (C1) and setting (F12) the variable (Mx) and entering the associated critical code section (C1), if the variable (Mx) is not set by another task (S1, Sn), or, waiting (F13) for a release (F22) by another task (S1, Sn) and releasing the CPU, if the variable (Mx) is already set by another task (S1, Sn); and b.

Abstract: A mechanism for recording a timing in which a high urgency process is started is provided, and upon entry to a critical section in the middle of a low urgency process, by referencing the record, it is inspected whether a high urgency process will be started during execution of the critical section. If it will not be started, the critical section is entered, and if it will be started, control is exerted so that entry to the critical section is postponed until the high urgency process is completed. Exclusive access control in a critical section can be performed suitably under conditions where a plurality of task execution environments exist.

Abstract: When a specified task process may mix with another more highly prioritized task process, it is aimed at accurately calculating a process time for the specified task process. A CPU 11 can simultaneously perform a plurality of task processes such as a task process to display the reproduction time during an audio reproduction process on a display 20 and a task process concerning a telephone call. A DSP 12 performs the audio reproduction process and changes a timing to notify the CPU 11 of information about the audio reproduction time in accordance with loads on the task process in the CPU 11.

Abstract: A method for scheduling tasks in a computer operating system comprises a background task creating at least one registered service. The background task provides an execution presence and a data present to a registered service and ranks the registered services according to the requirements of each registered service. The background task also allocates an execution presence and a data presence according to each of the registered services such that each of the registered services is given an opportunity to be scheduled in the dedicated pre-assigned time slice.

Abstract: The system for conducting intensive multitask and multistream calculation in real time comprises a central processor core (SPP) for supporting the system software and comprising a control unit (ESCU) for assigning threads of an application, the non-critical threads being run by the central processor core (SPP), whereas the intensive or specialized threads are assigned to an auxiliary processing part (APP) comprising a set of N auxiliary calculation units (APU0, . . . , APUN-1) that are optimized for fast processing of certain operations, a memory space (SMS) shared by the auxiliary calculation units (APU0, . . . , APUN-1) via an internal network and a unit (ACU) for controlling and assigning the auxiliary resources. The various elements of the system are arranged in such a manner that communication between the various auxiliary calculation units (APU0, . . . , APUN-1) or between those auxiliary calculation units (APU0, . . .

Abstract: The present invention extends to methods, systems, and computer program products for protected mode scheduling of operations. Protected mode (e.g., user mode) scheduling can facilitate the development of programming frameworks that better reflect the requirements of the workloads through the use of workload-specific execution abstractions. In addition, the ability to define scheduling policies tuned to the characteristics of the hardware resources available and the workload requirements has the potential of better system scaling characteristics. Further, protected mode scheduling decentralizes the scheduling responsibility by moving significant portions of scheduling functionality from supervisor mode (e.g., kernel mode) to an application.

Abstract: A method for communicating video data between a first host and a second host. The method may comprise encoding a video signal producing an encoded video signal at the first host. The method may also comprise transmitting, by the first host, the encoded video signal to the second host. The encoding and transmitting may both be performed by a first single multimedia thread of execution associated with an operating system at the first host. Other embodiments are also disclosed.

Abstract: An inter-processor communication system includes processors and a transfer device that, upon receiving a multicast packet from any of the processors, transfers the packet to processors designated in the packet as destinations among the processors. Each processor includes: a memory unit; a holding unit which holds position information indicating a reference position in the memory unit; a transmitting unit which transmits to the transfer device a multicast packet representing data and an adjustment value indicating an area for writing data that was set for use by its own processor by using the reference position; and a receiving unit which, upon receiving a multicast packet that has been transmitted by way of the transfer device, determines a write position in the memory unit based on the adjustment value in the packet and the position information and stores the data in the packet in that write position.

Abstract: The invention relates to a mechanism for executing one Hard Real-Time (HRT) task in a multithreaded processor comprising means for determining the slack time of the HRT task; means for starting the execution of the HRT task; means for verifying if the HRT task requires using a resource that is being used by at least one Non Hard Real-Time (NHRT) task; means for determining the delay caused by the NHRT task; means for subtracting the determined delay from the slack time of the HRT task; means for verifying if the new value of the slack time is lower than a critical threshold; and means for stopping the NHRT tasks.

Abstract: A system and associated method for mutually exclusively executing a critical section by a process in a computer system. The critical section accessing a shared resource is controlled by a lock. The method measures a detection time when a lock contention is detected, a wait time representing a duration of wait for the lock at each failed attempt to acquire the lock, and a delay representing a total lapse of time from the detection time till the lock is acquired. The delay is logged and used to calculate an average delay, which is compared with a suspension overhead time of the computer system on which the method is executed to determine whether to spin or to suspend the process while waiting for the lock to be released.

Abstract: A virtual execution system that is configured to be used in a resource-constrained device. The resource-constrained device includes an operating system and an application program that includes instructions. The virtual execution system includes an execution engine that is configured to execute the application program, and to facilitate the compatibility of the application program with the operating system. Non-functional aspects characterize the instructions and the operating system. The execution engine has access to the non-functional aspects, and implements improvements during the execution of the application program based on the non-functional aspects.

Abstract: The management of computational resources of coprocessors to facilitate efficient execution of multiple applications in a multitasking environment is accomplished by enabling multiple threads of execution to compose command buffers in parallel, submitting those command buffers for scheduling and dispatch by the operating system, and fielding interrupts that notify of completion of command buffers, the system enables multiple applications to efficiently share the computational resources available in the system.

Abstract: In a computing system having virtualization software including a guest operating system (OS), a method for executing guest OS instructions that includes: replacing each of one or more guest OS instructions with: (a) a translated instruction, which translated instruction is a one-to-one translation, or (b) a trap instruction.

Abstract: A system, method and apparatus for time block planning is disclosed. For example, one disclosed embodiment comprises receiving a first task with a set start time and a set duration, receiving a second task with a flexible start time, and scheduling the first task at the set start time and for the set duration. Next, the embodiment comprises scheduling the second task if the second task does not temporally overlap the first task, otherwise scheduling the second task at a different time or placing the second task in a user input queue if the second task temporally overlaps the first task. Additionally, this embodiment comprises displaying a schedule with a graphical user interface and prompting a response to the second task in the user input queue. In this way, a second task can be scheduled at a different time according to a response to the user input queue.

Abstract: A method for executing an application, that includes instantiating, by a first thread, a first executable object and a second executable object, creating a first processing unit and a second processing unit, instantiating an executable container object, spawning a second thread, associating the first executable object and the second executable object with the executable container object, processing the executable container object to generate a result, and storing the result. Processing the executable container object includes associating the first executable object with the first processing unit, and associating the second executable object with the second processing unit, wherein the first thread processes executable objects associated with the first processing unit, wherein the second thread processes executable objects associated with the second processing unit, and wherein the first thread and the second thread execute concurrently.

Abstract: The invention relates to a process for carrying out at least one task for calculating at least one signal to be simulated in real time by a task manager implemented on a data processing system with a real-time operating system in software, which manager periodically starts a task after a time period that is given or can be given which task calculates at least one output signal from at least one given input signal which output signal is a function of it, characterized in that a set of at least two different tasks with different calculation times for calculating the same at least one signal to be simulated is stored in an executable manner in the data processing system, and at least one minimal task has a calculation time shorter than the time period, in which the task manager starts at least one of the tasks from the set according to a stored strategy with which a calculation result of at least one of the tasks from the set is obtained while maintaining the real time within the given time period.

Abstract: A method for scheduling a plurality of computation jobs to a plurality of data processing units (DPUs) in a grid computing system 100. The method includes receiving a first computation job by a scheduling DPU from the plurality of computation jobs. Further, the method includes scheduling the first computation job at a first set of DPUs in the grid computing system based on first scheduling criteria. Furthermore, the method includes scheduling the first computation job at a first DPU from the first set of DPUs based on second scheduling criteria. The method also includes storing information about the first computation job and the first set of DPUs in a history table at the scheduling DPU. The method further includes storing information about the first DPU in a demand matrix of the first set of DPUs.

Abstract: A mechanism is provided for integrating a user resource into a managed computing resource system. If a level of data privacy indicating a first level of dedicated computing resources, a user resource is integrated into a first logical design. Responsive to the level of data privacy indicating a second level of dedicated computing resources, the user resource is integrated into a second logical design. If there is no indication of the level of data privacy and the user resource has at least one associated unique IP address, a capacity of a point of deployment (POD) device is determined. If there is no indication of the level of data privacy and no unique IP address, the user resource is integrated into the first logical design. If the user resource utilizes a predefined percentage of the capacity, the user resource is integrated into a third logical design.

Abstract: In an information processing apparatus according to the present invention, a control unit notifies each application program of a key input event in a multi-window system. If the state of a first application program is inactive, the control unit determines whether or not the event notified to the first application program is a key input event caused by a key other than an active switching key. If it is determined that the event is a key input event caused by a key other than the active switching key, the control unit causes a clock circuit to time a predetermined time period, and performs control so as to omit part of processing by the first application program, or to provide a predetermined wait time in between the processing by the first application program, until the predetermined time period is timed out.

Abstract: Techniques for segregating one or more logs of at least one multitasking user to derive at least one behavioral pattern of the at least one multitasking user are provided. The techniques include obtaining at least one of at least one action log, configuration information, domain knowledge, at least one task history and open task repository information, correlating the at least one of at least one action log, configuration information, domain knowledge, at least one task history and open task repository information to determine a task associated with each of one or more actions and segregate the one or more logs based on the one or more actions, and using the one or more logs that have been segregated to derive at least one behavioral pattern of the at least one multitasking user. Techniques are also provided for deriving intelligence from at least one activity log of at least one multitasking user to provide information to the at least one user.

Abstract: An information processing system includes a master processor and a slave processor. The master processor operates in a multitasking environment capable of executing request source tasks for making processing requests to the slave processor in parallel by task scheduling based on execution priorities of the tasks. The slave processor operates in a multitasking environment capable of executing a communication processing task and child tasks created by the communication processing task for executing processing requested by the processing requests in parallel by task scheduling. The processing requests contain priority information associated with the execution priorities of the request source tasks in the master processor. The slave processor activates the communication processing task in common for the processing requests from the different request source tasks.

Abstract: A method and apparatus for improving forwarding information base (FIB) lookup performance. An FIB is partitioned into a multiple portions that are distributed across segments of a multi-channel SRAM store to form a distributed FIB that is accessible to a network processor. Primary entries corresponding to a linked list of FIB entries are stored in a designated FIB portion. Secondary FIB entries are stored in other FIB portions (a portion of the secondary FIB entries may also be stored in the designated primary entry portion), enabling multiple FIB entries to be concurrently accessed via respective channels. A portion of the secondary FIB entries may also be stored in a secondary (e.g., DRAM) store. A depth level threshold is set to limit the number of accesses to a linked list of FIB entries by a network processor micro-engine thread, wherein an access depth that would exceed the threshold generates an exception that is handled by a separate execution thread to maintain line-rate throughput.

Abstract: Methods and apparatus, including computer systems and program products, for enabling collaborative asset management. In one implementation, a computer program product includes instructions to perform the operations of providing a first copy of an asset for use by a first user. The asset is available for use and editing by multiple users, and the asset and the first copy each has a corresponding state. The instructions include monitoring changes in the states of the asset, the first copy, and/one or more additional copies of the asset. The additional copies of the asset correspond to one or more concurrent users. If a conflict is detected between the state of the first copy and the state of the asset, or between the state of the first copy and the states of the additional copies, the instructions include providing guidance to the first user about how to resolve the conflict.

Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.

Abstract: Coordination between multiple processors presents a set of difficult problems, since most processors are not designed for multi-processing, but for multi-tasking. Additionally, CPUs are increasingly limited by the memory bandwidth bottleneck. The iMEM architecture addresses the multi-processing problem, by simplifying processor access, and the memory bandwidth problem, by distributing intelligence across the memory system. ASCII encoding of task structure and instructions addresses compiler complexities.

Abstract: A task count controller, a task count control method, and a computer program capable of dynamically controlling the number of tasks that can be processed in parallel simultaneously without increasing computational load are provided. When a plurality of tasks are to be executed simultaneously in parallel processing, the number of tasks that can be executed simultaneously is controlled. The tasks to be executed simultaneously are added in units of a predetermined number of tasks and the throughput in one unit of work is measured for each task every time the tasks are added. The total sum of the measured throughputs is calculated, and it is determined whether the calculated total sum of throughputs is more than the total sum of throughputs immediately before the predetermined number of tasks are added.

Abstract: Embodiments of a computer system and methods for changing operating systems (OSs) can perform a task switching into a different OS without checking a system reset or power off of the system. A method for changing the OS in a multi-OS system can include initializing, at the BIOS, a hardware and dividing an area on the main memory for a booting initiated by an instant-on key/signal; turning over a system control to the embedded OS after loading an embedded OS on a specific area of the divided main memory and booting the same, and operating an instant-on player (IOP). When the IOP is terminated by a user, forcibly loading the normal OS on the main memory. The normal OS can be loaded in a hidden state before termination of the IOP. Thus, a time to reach normal computer system operations from an instant-on-function can be reduced.