Abstract: An order-relation analyzing apparatus collects assigned destination processor information, a synchronization process order and synchronization information, determines a corresponding element associated with a program among a plurality of elements indicating an ordinal value of the program based on the assigned destination processor information, when an execution of the program is started, and calculates the ordinal value indicated by the corresponding element for each segment based on the synchronization information, when the synchronization process occurs while executing the program. When a first corresponding element associated with a second program, of which the execution starts after the execution of a first program associated with the first corresponding element finishes, is determined, the ordinal value of the second program is calculated by calculating the ordinal value indicated by the first corresponding element.

Abstract: The invention provides a processor comprising an execution unit arranged to execute multiple program threads, each thread comprising a sequence of instructions, and a plurality of synchronisers for synchronising threads. Each synchroniser is operable, in response to execution by the execution unit of one or more synchroniser association instructions, to associate with a group of at least two threads. Each synchroniser is also operable, when thus associated, to synchronise the threads of the group by pausing execution of a thread in the group pending a synchronisation point in another thread of that group.

Abstract: Methods and systems are presented for updating software applications in a processor cluster, in which the cluster is divided into first and second processor groups and the first group is isolated from clients and from the second group with respect to network and cluster communications by application of IP filters. The first group of processors is updated or retrofitted with the new software and brought to a ready-to-run state while the second group is active to serve clients. The first group is then transitioned to an in-service state after isolating the then-active service providing application on second group. Thereafter, the second group of processors is offlined, updated or retrofitted, and transitioned to an in-service state to complete the installation of the new application version across the cluster with reduced or zero downtime and without requiring backward software compatibility.

Abstract: In a time management control method of a computer system for managing each individual time of a plurality of virtual systems, a service process or retains an overall system time and a difference time between the overall system time and a virtual system time for each virtual system, and a firmware in the virtual system acquires the overall system time and the difference time, calculates a difference time between the overall system time and the change time of the virtual system, adds the both difference times, and informs the service processor. Accordingly, the virtual system time can be changed without time management hardware in each virtual system. Further, since service processor performs update processing only, it is also possible to prevent a time set error caused by delayed calculation processing etc.

Abstract: Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a maskable or non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a maskable non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread. In addition, the disclosed methods and computer-executable components also: (a) allow scheduling of CPU resources such that real-time threads are guaranteed respective portions of time slots, (b) enable real-time scheduling on a non-real-time operating system, and (c) provide scheduling of CPU resources on a uni-processor machine such that at least first and second real-time threads dependent on one another are synchronized.

Abstract: A mechanism is provided for scheduling tasks across multiple processor units of differing capacity. In a multiple processor unit system with processor units of disparate speeds, it is advantageous to have the most processing-intensive tasks run on the processor units with the highest capacity. All tasks are initially scheduled on the lowest capacity processor units. Because processor units with higher capacity are more likely to have idle time, these higher capacity processor units may pull one or more tasks onto themselves from the same or lower capacity processor units. A processor unit will attempt to pull tasks that utilize a larger percentage of the timeslice. When a higher capacity processor unit is overloaded or near capacity, the higher capacity processor unit may push tasks to processor units with the same or lower capacity. A processor unit will attempt to push tasks that utilize a smaller percentage of the timeslice.

Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.

Abstract: A program execution time determining portion determines an execution start time and a processing volume per unit time of a program in such a manner that a processing volume necessary to execute the program is made equal to the extent that registered request for the execution time and allowable range are met. It is thus possible to determine the execution time of the program in such a manner that a necessary processing volume is made as equal as possible within the allowable range of the request for the execution time of the program, which enables clock control that suppresses a variation of the operating frequency of the CPU. Power consumption of the CPU can be thus reduced.

Abstract: A solution for managing a service engagement is provided. A service delivery model for the service engagement is defined within an engagement framework. The engagement framework, and consequently the service delivery model, can include a hierarchy that comprises a service definition, a set of service elements for the service definition, and a set of element tasks for each service element. The set of element tasks can be selected from a set of base tasks, each of which defines a particular task along with its input(s), output(s), and related asset(s). As a result, service engagements can be managed in a consistent manner using a data structure that promotes reuse and is readily extensible.

Abstract: In one embodiment, the present invention includes a method for receiving a signal in a filter register of a performance monitor from an execution unit to enable a field of the filter register associated with a first thread when a filter enable instruction is executed during execution of code of the first thread, receiving a thread identifier and event information in the performance monitor from the execution unit, and determining if the thread that corresponds to the received thread identifier is enabled in the filter register and if so, storing the event information in a first counter of the performance monitor. Other embodiments are described and claimed.

Abstract: A system for viewing and managing work flow. The system includes at least one processor and memory configured to track time requirements for each of a plurality of jobs, compile and display the time requirements relative to current time in a plurality of managerial-level views, and in each view, indicate status of the jobs relative to the time requirements.

Abstract: Systems and methods for switching from a first Internet context to a second Internet context without process shutdown are described. Internet context data, such as cookies, history and user-defined data, is stored in containers unique to each user on a system. Internet content is stored in a common location so redundant downloaded information is not stored. Content information is found or stored by hashing a URL and indexing the memory location according to the resulting hash value. If content data is specific to a particular user, a hash is performed on a combination of the URL and an ordinal associated with the user's unique identity to obtain a hash value unique to the user. The user-specific content is then stored and the memory location is indexed according to the unique hash value.

Abstract: A method, apparatus and system are described for seamlessly sharing I/O devices amongst multiple virtual machines (“VMs”) on a host computer. Specifically, according to one embodiment of the invention, the virtual machine manager (“VMM”) on the host cycles access to the I/O devices amongst the VMs according to a round robin or other such allocation scheme. In order to provide direct access to the devices, the VMM may save the device state pertaining to the currently active VM, store the state in a memory region allocated to the currently active VM, retrieve a device state for a new VM from its memory region and restore the device using the retrieved device state, thus providing the illusion that each VM has direct, full-speed, exclusive access to the I/O device.

Abstract: Managing access to a shared resource includes receiving a request indicating that an operation requires access to the shared resource, associating the operation with a lock in a lock queue that is associated with the shared resource, and determining whether the shared resource is accessible to the operation.

Abstract: Visibility profiles associated with a substantially real time messaging environment are disclosed. Additionally, techniques for managing visibility profiles are disclosed, which include associating a first visibility profile with a first situation, and associating a second visibility profile with a second situation, A visibility profile indicates a set of friends, of a particular user, that are allowed, or disallowed, to view the particular user as available when the particular user is in the associated situation. A situation refers to one or more of a particular time period that a user is logged in, a particular location of the user, a particular device that the user is currently using, or a particular log-in that the user is currently using. Visibility profiles are used to manage the appearance of a user to other users/friends for communication using applications such as instant messaging, electronic mail, web-based mail programs, or other types of data communication exchange applications.

Abstract: A system and method for increasing performance in a simulator environment operable to simulate a multiprocessor platform with program code running thereon. A set of processors are initialized upon instantiating the simulator environment on a host machine for executing the program code instructions. Code execution on a simulated processor is suspended by executing a simulator API routine which is called when the program code is to enter an idle state. The host resources that would otherwise have been spent on the processor running the idle loops are therefore conserved for use by the remaining processors.

Abstract: A method and apparatus for monitoring the performance characteristics of a multithreaded processor executing instructions from two or more threads simultaneously. Event detectors detect the occurrence of specific processor events during the execution of instructions from threads of a multithreaded processor. Specialized event select control registers are programmed to control the selection, masking and qualifying of events to be monitored. Events are qualified according to their thread ID and thread current privilege level (CPL). Each event that is qualified is counted by one of several programmable event counters that keep track of all processor events being monitored. The contents of the event counters can then be accessed and sampled via a program instruction.

Abstract: Currently lacking are effective and accurate tools to help petroleum traders and logistics personnel to make better decisions, collaborate in real-time and negotiate deals in a private and secure environment. The present invention addresses this and other needs in the industry. In particular, the present invention provides automated workflow management for a series of workflow tasks by mapping the workflow tasks to a collaborative workflow process comprising: roles, users, business processes and computer executable activities. A workflow object is received that supplies information used to set particular attributes of the roles, the users, the business activities and the computer executable activities of the collaborative workflow process. Information and data objects are shared electronically among the users performing certain of the roles. At least one of the activities is automatically executed, such that the workflow is automatically managed.

Abstract: According to one embodiment, a program processing method includes converting parallel execution control description into graph data structure generating information, extracting a program module based on preceding information included in the graph data structure generating information when input data is given, generating a node indicating an execution unit of the program module for the extracted program module, adding the generated node to a graph data structure configured based on preceding and subsequent information defined in the graph data structure generating information, executing a program module corresponding to a node included in a graph data structure existing at that time, by setting values for the parameter, based on performance information of the node when all nodes indicating a program module defined in the preceding information have been processed, and obtaining and saving performance information of the node when a program module corresponding to the node has been executed.

Abstract: A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) an event recorder that records occurrences of predetermined events and (2) an event acknowledger, associated with the event recorder, that acknowledges ones of the events based on an identity of a currently-active context.

Abstract: A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.

Abstract: Provided are a method, system, and program for executing multiple threads in a processor. Credits are set for a plurality of threads executed by the processor. The processor alternates among executing the threads having available credit. The processor decrements the credit for one of the threads in response to executing the thread and initiates an operation to reassign credits to the threads in response to depleting all the thread credits.

Abstract: A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet is presented. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.

Abstract: A task switch from a first data processing task to a second data processing task can be accomplished by the first task calling a function which saves the first task's context, restores the second task's context and then returns. Because the second task's context has been restored, the called function actually returns to the second task, thereby completing the task switch.

Abstract: In one embodiment, a processor comprises a cache and a cache miss unit coupled to the cache. The cache miss unit is configured to initiate a cache fill of a cache line for the cache responsive to a first cache miss in the cache, wherein the first cache miss corresponds to a first thread of a plurality of threads in execution by the processor. Furthermore, the cache miss unit is configured to record an additional cache miss corresponding to a second thread of the plurality of threads, wherein the additional cache miss occurs in the cache prior to the cache fill completing for the cache line. The cache miss unit is configured to inhibit initiating an additional cache fill responsive to the additional cache miss.

Abstract: There is provided with a multitask processing device for processing a plurality of tasks by multitask, the tasks being each split into at least two sections, including: a stable set storage configured to store a stable set including one or more section combinations; a program execution state calculator configured to calculate, for each of the tasks, a program execution state including a section where execution is to start when the task is next executed and current sections of other tasks different from the task among the tasks; a distance calculating unit configured to calculate a distance between each of the program execution states and the stable set; and a task execution unit configured to select and execute a next task to be executed next based on calculated distances.

Abstract: A method and computer system for dynamically selecting an optimal synchronization mechanism for a data structure in a multiprocessor environment. The method determines a quantity of read-side and write-side acquisitions, and evaluates the data to determine an optimal mode for efficiently operating the computer system while maintaining reduced overhead. The method incorporates data received from the individual units within a central processing system, the quantity of write-side acquisitions in the system, and data which has been subject to secondary measures, such as formatives of digital filters. The data subject to secondary measures includes, but is not limited to, a quantity of read-side acquisitions, a quantity of write-side acquisitions, and a quantity of read-hold durations. Based upon the individual unit data and the system-wide data, including the secondary measures, the operating system may select the most efficient synchronization mechanism from among the mechanisms available.

Abstract: A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states.

Abstract: A sensor adjusting circuit for adjusting a digital sensor, whose circuit scale is small and which can maintain high accuracy in a wide adjustment range is provided. A sensor adjusting circuit for adjusting an analog input signal inputted from a sensor and outputting it as another analog output signal in accordance with a physical quantity to be sensed, comprises: a first analog-to-digital converter having an analog integrator (2) for integrating the analog input signal, a comparator (3) for comparing an output of the analog integrator with a predetermined value, and a D/A converter (7) for outputting an output of the comparator as the input signal; and a second digital-to-analog converter (5) for converting the output of the comparator and outputting it as the analog output signal.

Abstract: A method and computer program are provided for managing man hours of multiple individuals working one or more tasks during a predefined time period that include selectively opening a plurality of tasks of differing task characteristic and task type, selectively associating one or more individuals to one of the open plurality of tasks, selectively unassociating at least one of the associated one or more individuals, maintaining at least one timer for each of the open plurality of tasks, selectively closing one or more of the open plurality of tasks, and selectively outputting an invoice for the closed plurality of tasks based on the bid price of each of the open plurality of tasks. One or more of the individuals are associated and unassociated prior to completion of the open one or more tasks. The at least one timer maintains a total time for all of the associated one or more individuals for each of the open plurality of tasks.

Abstract: One embodiment of the present invention provides a method and a system for tracking memory usage of tasks in a shared heap. The system performs a full garbage-collection operation on the shared heap, during which a base memory usage is determined for each task. The system then periodically samples task state during execution to generate an estimate of newly allocated memory for each task. The base memory usage and the estimate of newly allocated memory for each task are combined to produce an estimate of current memory usage for each task. This estimate of current memory usage is used to determine whether a task is likely to be violating a memory quota. If so, the system triggers a remedial action, which can include: a full garbage-collection operation; a generational garbage-collection operation; or generation of a signal which indicates that a memory quota violation has occurred.

Abstract: In a simplified user switching function for switching to another user without terminating an application of a current user, data of an application started up a user before switching is included and temporarily stored in a temporary storage file. Data generated by using an application started up a user A who is currently inactive as a result of user switching (user being in a logged-on state but the desktop changed to that of another user) is stored temporarily at the time of the user switching. Thus, even when a user B (currently active user) after the user switching performs a shutdown operation or the like, the data of the currently inactive user A can be protected securely. Also, when the writing time is set unchanged, transistor size of the TFTs provided in the pixel circuit can be reduced.

Abstract: A uniprocessor that can run multiple threads (programs) simultaneously is achieved by use of a plurality of low-frequency minicore processors, each minicore for receiving a respective thread from a high-frequency cache and processing the thread. A superscalar processor may be used in conjunction with the uniprocessor to process threads requiring high throughput.

Abstract: An example of a solution provided here comprises: providing a logical design, including at least one hub containing central management tools, and a plurality of lower tiers containing local management tools; placing components according to the design; and providing, from the hub, one or more management functions. The lower tiers include one or more elements chosen from RIM's, spokes, and POD's.

Abstract: A graphics processor buffers vertex thread and pixel threads. The different types of threads issue instructions corresponding to different sets of operations. A plurality of different types of execution units are provided, each type of execution unit servicing a different class of operations, such as an executing unit supporting texture operations, an execution unit supporting blending operations, and an execution unit supporting mathematical operations. Current instructions of the threads are buffered and prioritized in a common instruction buffer. A set of high priority instructions is issued per cycle to the plurality of different types of execution units.

Abstract: This process for maintaining synchronization applies to processors of redundant parallel processing units of a computer running, in parallel and under the control of the same multi-tasking time-sharing operating system (30) and independent clocks of the same speed, with the same applications with the same parameterizations. It consists on the one hand of including in the operating system (30) a synchronization service (303) called by a synchronization interrupt request and applying a correction of synchronization based on comparing the contents of the processed-instruction counters belonging to the various processors (1, 2) and the utilisation of the lockstep operating mode and on the other hand of inserting a synchronization interrupt request when commencing the processing of timing interrupts generated by the scheduler (301) of the operating system in order to terminate a time slice allocated to processing an application.

Abstract: The present invention relates to a method for measuring a quantity of usage of a CPU, in particular to a method for measuring a quantity of usage of a CPU which is capable of getting a credible quantity of usage of a CPU without amending an algorithm in order to adapt it to the an operating system, e.g., MS-Windows System, or requiring a complicated code. The method uses various algorithms provided by the operating system on the behalf of a registry storing a quantity of usage of a CPU inside a system. Accordingly the present invention can measure a quantity of usage of a CPU easily without lowering a performance of the operating system.

Abstract: Exemplary embodiments may use remote processing resources to perform processing operations on behalf of a client. The embodiments may dynamically switch among available processing resources while processing is performed. Exemplary embodiments may be used, for example, to publish code, perform processing operations within a determined interval, perform scheduled processing operations, perform synchronized simultaneous execution of two or more programs, support coding competitions, support social networking and/or computing activities, and/or other types of processing activities.

Abstract: The present invention provides providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems. In one embodiment, a scheduler accesses an activity scheduling graph. The activity scheduling graph is comprised of nodes each representing a recurring execution interval, and has one root, one or more leaves, and at least one path from the root to each leaf. Each node is on at least one path from the root to a leaf, and the number of times the execution interval represented by each node occurs during the traversal of the graph is equal to the number of paths from the root to a leaf that the node is on. Each node has associated with it an execution interval length, and is adapted to being dedicated to executing the threads of a single activity. There may be one scheduling graph for each processor, or a scheduling graph may traverse multiple processors.

Abstract: A porting layer takes software developed using a single threaded modeling tool to a multiple threaded environment. The single threaded modeling tool is used to model the software. The porting layer ports in variables into a multiple threaded operating environment by reference and not as variables so that each thread can access variables by reference.

Abstract: A parallel process execution method that allocates CPU time to parallel processes at any desired ratios. The method sets a time allocation ratio to determine how much of a given cycle period should be allocated for execution of a parallel program. Process switching is then performed in accordance with the time allocation ratio set to the parallel program. More specifically, parallel processes produced from a parallel program are each assigned to a plurality of processors, and those parallel processes are started simultaneously on the processors. When the time elapsed since the start of the parallel processes has reached a point that corresponds to the time allocation ratio that has been set to the parallel program, the execution of the assigned parallel processes is stopped simultaneously on the plurality of processors.

Abstract: The present invention is a method of doing business over a network that: receives a request for transmitting digital information after a start time and before an end time, determines the time required to transmit the digital information based on the number of packets in the information and the network speed, schedules a transmit time for the digital information, and accepts the digital information for transmission only if the time required to transmit is less than or equal to the difference between the transmit time and the end time. Pricing of the transmission can be determined by the priority of transmission, whether the information is transmitted the first time or rescheduled, and whether the user receives an acknowledgment.

Abstract: Systems, methods, devices enable the efficient synchronization of timing information from first time-based process to a second time-based process using periodic or event-driven synchronization messages.

Abstract: An approach that uses a handler to detect asynchronous lock line reservation lost events, and switching tasks based upon whether a condition is true or a mutex lock is acquired is presented. A synergistic processing unit (SPU) invokes a first thread and, during execution, the first thread requests external data that is shared with other threads or processors in the system. This shared data may be protected with a mutex lock or other shared memory synchronization constructs. When requested data is not available, the SPU switches to a second thread and monitors lock line reservation lost events in order to check when the data is available. When the data is available, the SPU switches back to the first thread and processes the first thread's request.

Abstract: An approach that optimizes system performance using performance monitors is presented. The system gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread.

Abstract: Identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.

Abstract: The invention relates to an electronic device (1) and a method for carrying out several processes with said electronic device (1), by means of which rapid solution times may be achieved in a resource-saving manner, whereby, in operation, said electronic device (1) carries out first and second processes (P1, P2), of which the first process (P1) may be carried out in the form of an approximation (P1-N) and in the form of an executable calculation (P1-B). The electronic device comprises a processor (9), for carrying out processes (P1, P2) and an electronic unit (11) comprises a device which recognizes whether the processor (9) is active and serves to carry out the first process (P1) during a simultaneous processing of two processes by the processor (9), by itself determining the approximation (P1-N), used in place of an executable calculation (P1-B), carried out by the processor (9).

Abstract: A method and mechanism for using threads in a computing system. A multithreaded computing system is configured to execute a first thread and a second thread. The first and second threads are configured to operate in a producer-consumer relationship. The second thread is configured to execute utility type functions in advance of the first thread reaching the functions in the program code. The second thread executes in parallel with the first thread and produces results from the execution which are made available for consumption by the first thread. Analysis of the program code is performed to identify such utility functions and modify the program code to support execution of the functions by the second thread.

Abstract: A system for sharing computing resources including a multi-tasking environment within which a multiple of speech-enabled applications concurrently execute. The system can include a speech resource manager configured to receive speech based requests from the applications, to associate these requests with the requesting application, to use a set of speech resources to produce results for the requests, and to deliver the results to a requesting application. The speech resource manager permits each concurrently executing speech-enabled application to utilize the speech resources. In one embodiment, the system can be a mobile communication device that includes a wireless transceiver configured for real-time communications. When implementing the system in a mobile communication device, the multitasking environment can be a virtual machine environment. such a JAVA MICRO EDITION PLATFORM (J2ME) environment.

Abstract: A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries.