Abstract: A program is executed utilizing a main hardware thread. During execution, an instruction specifies to execute a portion utilizing a worker hardware thread. If a processor state indicator is set to multi-threaded, the specified portion is executed utilizing the worker hardware thread. However, if the processor state indicator is set to single-threaded, the specified portion is executed utilizing the main hardware thread as a subroutine. The main hardware thread may pass parameter data to the worker hardware thread by copying the parameter data register or memory location for the main hardware thread to an equivalent parameter data register or memory location for the worker hardware thread. Similarly, the worker hardware thread may pass return values to the main hardware thread by copying a return value register or memory location for the worker hardware thread to an equivalent return value register or memory location for the main hardware thread.

Abstract: In one embodiment, a processor comprises an execution core configured to execute instructions including instructions comprising a guest and a circuit coupled to the execution core. The circuit is configured to monitor the execution core, and is programmable to limit an execution of the guest in the execution core to an execution interval. In another embodiment, a method comprises establishing an execution interval for a guest to be executed in a processor; and initiating execution of the guest in the processor. The processor includes a circuit configured to monitor execution of the guest to detect an end of the execution interval. A computer accessible medium storing instructions which, when executed, implement the method is also contemplated.

Abstract: The present invention extends to methods, systems, and computer program products for resolving lock conflicts. For a state persistence system, embodiments of the invention can employ a logical lock clock for each persisted state storage location. Lock times can be incorporated into bookkeeping performed by a command processor to distinguish cases where the instance is locked by the application host at a previous logical time from cases where the instance is concurrently locked by the application host through a different name. A logical command clock is also maintained for commands issued by the application host to a state persistence system, with introspection to determine which issued commands may potentially take a lock. The command processor can resolve conflicts by pausing command execution until the effects of potentially conflicting locking commands become visible and examining the lock time to distinguish among copies of a persisted state storage location.

Abstract: An information processing apparatus capable of displaying a predetermined object, such as a file, is configured to allow a plurality of users to access the object. First, a plurality of users are set to a logged-in status. While the plurality of users are set to the logged-in status, one user in the logged-in status and having no access right to an object is permitted to operate the object using an access right of another user in the logged-in status.

Abstract: An application programming interface (API) that leverages operating system instrumentation to provide a chain of threads and processes may alleviate some debugging complications. Specifically, the chain may start with the first thread in the process that experienced the original failure and end with the last thread upon which the first thread directly or indirectly depends. The API may aid debugging efforts by classifying all threads related or dependent upon an original failed thread into specific categories of failures, requesting further information from the originating OS concerning specific failed threads, and using that information to debug the failed application or process more thoroughly.

Abstract: A technique to process interrupts on a virtualized platform. A plurality of virtual machines (VMs) runs on the virtualized platform having at least a processor. The VMs include a power VM. A VM scheduler schedules the VMs for execution on the virtualized platform according a scheduling policy. A virtualized interrupt mask controller controls masking an interrupt from an interrupting source according to the scheduling policy.

Abstract: A method and a system efficiently and effectively share array entries among multiple threads of execution in a multiprocessor computer system. The invention comprises a method and an apparatus for array creation, a method and an apparatus for array entry data retrieval, a method and an apparatus for array entry data release, a method and an apparatus for array entry data modification, a method and an apparatus for array entry data modification release, a method and an apparatus for multiple array entry atomic release-and-renew, a method and an apparatus for array destruction, a method and an apparatus for specification of array entry discard strategy, a method and an apparatus for specification of array entry modification update strategy, and finally a method and an apparatus for specification of user-provided array entry data construction method.

Abstract: A method of assigning task management blocks for first type tasks to time slot information on a one-by-one basis, assigning a plurality of task management blocks for second type tasks to time slot information, selecting a task management block according to a priority classification when switching to the time slot of the time slot information, and switching to the time slot except the time slot information. Additionally a task switching apparatus selects the task management block assigned to the time slot and executes the task.

Abstract: Disclosed are methods and apparatus for measuring performance of a multi-thread processor. The method and apparatus determine loading of a multi-thread processor through execution of an idle task in individual threads of the multi-thread processor during predetermined time periods. The idle task is configured to loop and run when no other task is running on the threads. Loop executions of the idle task on each thread are counted over each of the predetermined time periods. From these counts, loading of each of the threads of the multi-thread processor may then be determined. The loading may be used to develop a processor profile that may then be displayed in real-time.

Abstract: Embodiments of the invention enable the efficient use of shared resources by different processes, such as background and foreground processes sharing a mass storage device. Thus, disk intensive operations, such as file indexing, do not unduly interfere with higher priority processes. In one embodiment, a first process is permitted to access a computer resource for a first predetermined time period. After the first predetermined time period has elapsed, the first process is inhibited from accessing the computer resource for a second predetermined time period. After the second predetermined time period has elapsed, a determination is made as to whether the computer resource is idle, wherein if the computer resource is not idle, the embodiment waits for a third predetermined time period and again determining if the computer resource is idle, and wherein if the computer resource is idle, the embodiment allows the first process to access the computer resource again.

Abstract: A context switch request is made from a host unit to a processing engine separately from the method stream to that processing engine and does not require the host unit to know what context the processing engine is currently working on. Upon receiving the request, the processing engine compares the requested context with the context that it is currently working on, and if the two are different, performs the context switch to the requested context. On the other hand, if the two are the same, the engine does not perform the context switch and continues working on the current context.

Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller. The memory is organized into a set of logical partitions. Task partitions describe a task and include task state information, task data registers and ASCII task instructions. The task state information includes a set of index registers that are accessible by the task instructions. The index registers typically have dedicated locations in the task partition and are referred to by lower case ASCII alphabetic characters. Index registers are used to refer to a task partition in some cases or to a location in the current task partition in other cases for purposes of branching. Index registers can be incremented or decremented and loaded with an immediate data value. In one embodiment, the data flow unit is used to interpret the branch code and fetch contents of a named index register used in the branch.

Abstract: A distributed processing system for executing an application includes a processing element capable of performing parallel processing, a control unit, and a client that makes a request for execution of the application to the control unit. The processing element has, at least at the time of executing the application, one or more processing blocks that process respectively one or more tasks to be executed by the processing element, a processing block control section for calculating the number of parallel processes based on an index for controlling the number of parallel processes received from the control unit, a division section that divides data to be processed input to the processing blocks by the processing block control section in accordance with the number of parallel processes, and an integration section that integrates processed data output from the processing blocks by the processing block control section in accordance with the number of parallel processes.

Abstract: Techniques for allocating computing resources to tasks include receiving first data and second data. The first data indicates a limit for unblocked execution by a processor of a set of at least one task that includes instructions for the processor. The second data indicates a maximum use of the processor by the set. It is determined whether a particular set of at least one task has exceeded the limit for unblocked execution based on the first data. If it is determined that the particular set has exceeded the limit, then execution of the particular set by the processor is blocked for a yield time interval based on the second data. These techniques can guarantee that no time-critical tasks of an embedded system on a specific-purpose device are starved for processor time by tasks of foreign applications also executed by the processor.

Abstract: A scheduling mechanism that fairly allocates a resource to a number of schedulable elements, of which some are latency-sensitive, is disclosed. Each element's use of the resource is tracked by determining the element's virtual time. An active element is selected from the elements that are ready to use the resource by determining the element that has the smallest effective virtual time. The effective virtual time is the element's actual virtual time modified by a borrowed virtual time value. When an element has a short-term need for the resource, it can borrow the privilege to run by borrowing virtual time. As the element uses the resource, it consumes virtual time according to its weight. When the elements are scheduled for the resource, the ready element having the smallest virtual time is selected. The invention enforces long-term fairness to each element while allowing latency-sensitive elements to be preferably selected.

Abstract: The invention set forth herein describes a mechanism for predicated execution of instructions within a parallel processor executing multiple threads or data lanes. Each thread or data lane executing within the parallel processor is associated with a predicate register that stores a set of 1-bit predicates. Each of these predicates can be set using different types of predicate-setting instructions, where each predicate setting instruction specifies one or more source operands, at least one operation to be performed on the source operands, and one or more destination predicates for storing the result of the operation. An instruction can be guarded by a predicate that may influence whether the instruction is executed for a particular thread or data lane or how the instruction is executed for a particular thread or data lane.

Abstract: Methods and systems for scenario-based process modeling are described. In one example embodiment, a system for scenario-based process modeling can include a scenario module, a deviations module, a parallel tasks module, and a workflow generation engine. The scenario module is to receive a series of tasks to define a standard process flow. The deviations module is to receive a deviation from the standard process flow. The parallel tasks module is to enable identification of one or more parallel tasks. The workflow generation engine is to generate a workflow model based on the standard process flow, deviation, and one or more parallel tasks.

Abstract: A source code clarification system is described. In various embodiments, the source code clarification system receives clarified source code and transforms the clarified source code into standard source code or object code that implements asynchronous components. The standard software source code can contain expressions for enabling asynchronous communications. The clarified code can be software source code that is expressed in an imperative language and is capable of static analysis. The clarified source code can contain a coordination primitive that encapsulates interactions between asynchronous components. By using the coordination primitives and events, the clarified source code can express interactions between asynchronous components so that the clarified source code is easier for developers to understand and for static analysis tools to analyze.

Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.

Abstract: A method for compensating for dynamic IR (voltage) drop for instruction execution. In a data processing system having a memory, and a central processing unit (CPU), where the CPU includes an adaptive power supply, a method is provided for determining the power required for instruction execution, adjusting power supplied by the adaptive power supply to the CPU to execute the instruction, and dispatching the instruction from the memory to the CPU for execution.

Abstract: A method for real-time monitoring of the performance of a network. From a set of predefined network capabilities, one or more of the network capabilities is attributed to an application of the network. Activity of the application running in the network is sampled to individually monitor each capability attributed to the application. This method allows the collection and evaluation of usage information for each application by network capability. A user can also manipulate a NCO environment by adding phantom nodes and/or resources to observe effects on capability loads.

Abstract: A wireless mobile communication device has an application program and a garbage collection program stored in memory. The garbage collection program is configured to identify a root set of referenced objects of the application program with use of a reference indicator array and to perform a mark and sweep process based on the root set of referenced objects. The reference indicator array has a plurality of reference indicators where each referenced indicator corresponding to a referenced object is set as referenced. The application program is configured to be executed during execution of a mark and sweep process of the garbage collection program, such that information received or provided via the user interface during the execution of the mark and sweep process is received or provided without suspension or delay.

Abstract: Systems, methods and computer program products for supporting transformation to a shared on-demand infrastructure. Exemplary embodiments include a method including identifying a CPU resource type (or, in general, other sharable resource) to analyze, calculating a number of servers in scope, Ns, collecting current resource usage data for systems in the scope, wherein the current resource data is provided by systems and performance management tools, identifying a Period P, counting a number of peaks (Np) in the Period, excluding adjacent spikes to each of the number of peaks, calculating an average of CPU usage, Um, which is generally provided by the usage collection tools, defining an amplitude Am, defining a value for % Ks, in the range of 0.2-0.3 (value suggested) and applying transformation formulas to obtain a minimum size of a resource pool, a size of a target environment and a resource saving.

Abstract: A method for dynamically arranging DSP tasks. The method comprises receiving an audio bit stream, checking a remaining execution time as the DSP transforms the audio information into spectral information, simplifying the step of transforming the audio information when the DSP detects that the remaining execution time is shorter then a predetermined interval, and skipping one section of the audio information and decoding the remaining section when the execution time is less than a predetermined interval.

Abstract: An approach is provided for coordination resource access. A resource access coordinating application determines the conflict condition among a plurality of queries from a respective plurality of applications for access to an identical resource in an information space. The resource access coordinating application then orders the queries based on one or more characteristics (e.g., read, write, update, delete, read-only, read-update, write-update, write-add, write-add, etc.) of the queries irrespective of the applications. Thereafter, the resource access coordinating application selects one of the queries based on the order.

Abstract: A wakeup mechanism for computing system is disclosed. A wakeup unit connected to a host interface is configured to detect a sequence of data values and to generate the activation signal if the detected sequence matches an expected sequence of data values. First, a read by the host processor at a particular address in memory is detected by the wakeup unit. Next, a sequence of data values is written to the address by the host processor and the wakeup unit compares the sequence to an expected sequence. If there is a match, the wakeup unit causes the multitasking controller to execute a test of the data in memory. If the test is positive, then an indicator is written to the address and when the host reads the indicator, the wakeup unit causes the multitask controller to become active.

Abstract: Methods and systems for coordinating the handling of information are disclosed herein and may include scheduling multiple processing tasks for processing multimedia data by a processor. A portion of the scheduled multiple processing tasks may be preprocessed and the preprocessed portion may be buffered within a modifiable buffer that handles overflow and underflow. A portion of the buffered preprocessed portion of the scheduled multiple processing tasks may be executed. The scheduling may utilize a non-preemptive scheduling algorithm, such as an earliest deadline first (EDF) scheduling algorithm and/or a rate monotonic (RM) scheduling algorithm. The scheduled multiple processing tasks may include at least one maximum real deadline. The preprocessed portion of the scheduled multiple processing tasks may be outputted during processing of the blocking task, if a current task of the scheduled multiple processing tasks comprises a blocking task.

Abstract: A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of threads executing on the plurality of TCs. The system also includes a multiprocessor operating system (OS), configured to schedule execution of the threads on the plurality of TCs, wherein a thread of the threads executing on one of the plurality of TCs is configured to update the shared TLB, and prior to updating the TLB to disable interrupts, to prevent the OS from unscheduling the TLB-updating thread from executing on the plurality of TCs, and disable the instruction scheduler from dispatching instructions from any of the plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing.

Abstract: For a variable accessed at least once in a software-based transactional memory system (STM) defined (STM-defined) critical region of a program, modifying an access to the variable that occurs outside any STM-defined critical region system by starting a hardware based transactional memory based transaction, within the hardware based transactional memory based transaction, checking if the variable is currently owned by a STM transaction, checking if the variable is currently owned by a STM transaction; if the variable is not currently owned by a STM transaction, performing the access and then committing the hardware based transactional memory transaction; and if the variable is currently owned by a STM transaction, performing a responsive action.

Abstract: The invention comprises system and method for offloading a processor tasked with calendar processing of channel status information. The method comprises multiplexing channel status information received from a plurality of physical interfaces; grouping the channels based on bandwidth; comparing current and previous status information of a group of channels in a first memory; sending current channel status to the processor only if the status of any of the channels in the group has changed; and periodically synchronizing channel status information in the first memory to status information in the processor's memory. The system comprises: multiplexer to combine channel status information received from the interfaces and means for grouping, based on bandwidth, the channels; hardware assist engine to send current channel status to the processor only if channel status has changed; and device to synchronize channel status information in the hardware assist engine to status information in the processor's memory.

Abstract: Systems and methods of sharing processing resources in a multi-threading environment are disclosed. An exemplary method may include allocating a lock value for a resource lock, the lock value corresponding to a state of the resource lock. A first thread may yield at least a portion of the processing resources for another thread. The resource lock may be acquired for the first thread if the lock value indicates the resource lock is available.

Abstract: The present invention provides for programmable interleaved graphics processing. The invention provides an execution pipeline and a number of registers. Each register holds instructions from a separate program. Instructions from the registers are interleaved in the execution pipeline such that the average latency is one instruction per cycle. This is accomplished even when there is conditional branching and execution latency. When one instruction has a dependency based on execution of a previous instruction, that second instruction is not provided to the execution pipeline until completion of the first instruction. However, in the meantime interleaved instructions from other programs are still being executed while the first instruction of the first program is executing. Thus the pipeline is always full and the processor is always working at peak capacity. The automatic interleaving of instructions permits simplified graphics software routines to be written.

Abstract: A system for executing distributed software under hard real-time conditions comprises a plurality of nodes and a communication channel. Nodes are allowed to transmit data across the communication channel within time windows relative to repetitive communication time intervals of the communication channel, wherein a number of bytes transmitted within the communication time windows may vary from communication time window to communication time window. The data may be transmitted as a message comprising a representation of an identifying tag and a representation of the data. Also a number of bytes representing respective tags may vary from communication time interval to communication time interval.

Abstract: A transaction manager maintains an enlistment data structure used for managing resource object enlistment. A transaction manager may receive an enlistment request initiated from a resource object. Upon receiving the request, the transaction manager will determine if the resource object is already enlisted. If the resource object is already enlisted, the transaction manager will block the enlistment request. If the resource object is not enlisted, the transaction manager will enlist the resource. Upon enlistment, the resource object will perform a requested task or service. After the requested task or service is complete, the resource initiates a delistment request to the transaction manager. After receiving the delistment request from the resource, object, the transaction manager is delisted from the enlistment data structure.

Abstract: Systems and methods for dynamically variable idle time thread scheduling are described. In one aspect, threads are scheduled according to a predetermined periodic rate. If there are no threads to execute, one or more hardware elements and program modules are deactivated to an idle state for a dynamic variable amount of time. The dynamic variable amount of time is independent of the predetermined periodic rate at which threads are scheduled. The dynamic variable amount of time is also independent of key press events, and any event associated with release of a resource. Instead, the dynamic variable amount of time is based on a sleep state of a set of threads in a sleep queue.

Abstract: A method for scheduling jobs in a networked computing grid is described. The method includes scheduling jobs to meet goals related to execution of the jobs within the computing grid. The jobs may be scheduled by evaluating job execution goals against available resource slots provided by the computing grid. Also disclosed are related methods for scheduling jobs in which the jobs are submitted to service classes having defined job execution goals, and wherein the jobs are scheduled according to the job execution goals of the service classes.

Abstract: A threaded-programming analysis and diagnostic tool including two data structures to store a termination status of each of the threads in a multi-threaded program, logic to propagate information between the two data structures, and detection logic to determine whether a first thread could access the stack of a second thread before the second thread terminates.

Abstract: A computer implemented method, apparatus, system, and computer usable program product for controlling preemption rates. A scheduler identifies a preemption interval in response to a plurality of processes being executed by a processor. Only a single preemption of a process occurs during the preemption interval. The scheduler preempts a currently running process only once during the preemption interval. The preemption interval is adjusted to increase performance in executing processes.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests.

Abstract: Throttling of an iterative process in a computer system is disclosed. Embodiments of the present invention focus on non-productive iterations of an iterative process in a computer system. The number of productive iterations of the iterative process during a current timeframe is determined while the iterative process is executing. A count of the number of process starts for the iterative process during the current timeframe is stored. The count can be normalized to obtain a number of units of work handled during the current timeframe. A throttling schedule can be calculated, and the throttling schedule can be stored in the computer system. The throttling schedule can then be used to determine a delay time between iterations of the iterative process for a new timeframe. A formula can be used to calculate the throttling schedule. The throttling schedule can be overridden in accordance with a service level agreement (SLA), as well as for other reasons.

Abstract: Dual processor accelerated graphics rendering is a method which allows for optimizing graphics performance using two processors and 3D hardware accelerators. This method allows for real time embedded systems to have multiple partitions to render to multiple windows with non-blocking graphics calls. One processor queues up graphics calls within a discrete time because they do not interface with the graphics accelerator hardware. The second processor supports the hardware accelerator with drivers operating in a single partition. This design abstracts the graphics calls from the native interface of the graphics hardware accelerator.

Abstract: Methods and apparatuses for compiler-created helper thread for multi-threading are described herein. In one embodiment, exemplary process includes identifying a region of a main thread that likely has one or more delinquent loads, the one or more delinquent loads representing loads which likely suffer cache misses during an execution of the main thread, analyzing the region for one or more helper threads with respect to the main thread, and generating code for the one or more helper threads, the one or more helper threads being speculatively executed in parallel with the main thread to perform one or more tasks for the region of the main thread. Other methods and apparatuses are also described.

Abstract: An embodiment of the present invention is a technique to provide a real-time threading service to an application in a multi-core environment. An executive is launched, within a most privilege level of an operating system (OS), on a real-time core in the multi-core environment. The real-time core is sequestered from the OS. A real-time thread is created in a least privilege level on the real-time core for an application using a library. The library is loaded by the application. The real-time thread shares a virtual address space with the application.

Abstract: A system and method is disclosed for automated task/program management which is not dependent upon a calendar based schedule and flexibly accounts for various operating conditions. In one embodiment, the disclosed system and method permits specification of one or more tasks to be performed, such as a recurring task, and a time interval. The performance/execution of the task(s) may be related to or dependent upon satisfaction of one or more conditions, for example, that the computer that will execute the task(s) is turned on or otherwise available. The system and method monitors for the elapse of the specified time interval and also that the condition(s) is/are satisfied (which may occur by default if the monitoring program is similarly dependent upon the condition(s)). Upon elapse of the time interval and satisfaction of the condition(s), the specified task(s)/program(s) is/are caused to be executed.

Abstract: A method, for monitoring resources of a system for performing a first task and a second task, includes calculating a first completion count of the first task; calculating a second completion count of the second task; and determining whether the resources of the system are exhausted according to the first completion count and the second completion count.

Abstract: A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the shared cache memory.

Abstract: A context estimation rule is applied to spare time on a user's schedule, and contexts are estimated. On the basis of a task template, an input task is divided into plural subtasks. A task recommendation rule for recommending tasks to do from the relation between contexts and metadata of tasks is applied to the spare time of the user, and tasks to do in the spare time are recommended on the basis of the contexts of the spare time and the metadata of the subtasks. The recommended tasks are managed as schedules.

Abstract: A system, method, and computer readable medium for providing application isolation to one or more applications and their associated resources. The system may include one or more isolated environments including application files and executables, and one or more interception layers intercepting access to system resources and interfaces. Further, the system may include an interception database maintaining mapping between the system resources inside the one or more isolated environments and outside, and a host operating system. The one or more applications may be isolated from other applications and the host operating system while running within the one or more isolated environments.