Abstract: A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality register file segments are coupled to the partitionable engines for providing data storage.

Abstract: A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.

Abstract: Application virtualization at the thread level, rather than at the process level. the operation of a thread across virtualization contexts. For instance, one virtualization context might be a native environment, whereas another virtualization context might be a virtualization environment in which code running inside a virtualization package has access to virtualized computing resources. A thread operating in a first virtualization context then enters an entry point to code associated with a second virtualization context. For instance, a native thread might enter a plug-in operating as part of a virtualized package in a virtualization environment. While the thread is operating on the code, the thread might request access to the second computing resources associated with the second virtualization environment. In response, the thread is associated with the second virtualization context such that the thread has access to the second computing resources associated with the second virtualization context.

Abstract: Disclosed are various embodiment(s) for a digital device and a service processing method by the digital device. Here, a digital device according to an embodiment of the present invention comprises: a display processing unit for transmitting a first lifecycle message, a second lifecycle message, and coordinate information on the size and the position of the second application in a display, to Webkits of a first application and a second application, when a plurality of applications exist in the foreground; a display engine comprising a main sink for the first application and a sub sink for the second application; and a video processing unit for connecting the first application to the main sink of the display engine according to an identifier and a connection request received from a Webkit of the first application and connecting the second application to the sub sink of the display engine according to an identifier and a connection request received from a Webkit of the second application.

Abstract: Embodiments relate to parallel data streaming between a first computer system and a second computer system. Aspects include transmitting a request to establish an authenticated connection between a processing job on the first computer system and a process on the second computer system and transmitting a query to the process on the second computer system over the authenticated connection. Aspects further include creating one or more tasks on the first computer system configured to receive data from the second computer system in parallel and reading data received by the one or more tasks by the processing job on the first computer system.

Abstract: Parallel tasks are created, and the tasks include a first task and a second task. Each task resolves a future. At least one of three possible continuations for each of the tasks is supplied. The three continuations include a success continuation, a cancellation continuation, and a failure continuation. A value is returned as the future of the first task upon a success continuation for the first task. The value from the first task is used in the second task to compute a second future. The cancellation continuation is supplied if the task is cancelled and the failure continuation is supplied if the task does not return a value and the task is not cancelled.

Abstract: A method for executing instructions using a plurality of virtual cores for a processor. The method includes receiving an incoming instruction sequence using a global front end scheduler, and partitioning the incoming instruction sequence into a plurality of code blocks of instructions. The method further includes generating a plurality of inheritance vectors describing interdependencies between instructions of the code blocks, and allocating the code blocks to a plurality of virtual cores of the processor, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines. The code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.

Abstract: A first executing unit executes a first program by emulating information processing in a first operational environment in which the first program is executable. A generating unit generates, in parallel with the execution of the first program, a second program which is executable in a second operational environment of an information processing system and which is capable of acquiring the same processing result as the first program. A second executing unit terminates the execution of the first program by the first executing unit and also executing the second program, after the generation of the second program is completed.

Abstract: A grace period detection technique for a preemptible read-copy update (RCU) implementation that uses a combining tree for quiescent state tracking. When a leaf level bitmask indicating online/offline CPUs is fully cleared due to all of its assigned CPUs going offline as a result of hotplugging operations, the bitmask state is not immediately propagated to the root level of the combining tree as in prior art RCU implementations. Instead, propagation is deferred until all tasks are removed from an associated leaf level task list tracking tasks that were preempted inside an RCU read-side critical section. Deferring bitmask propagation obviates the need to migrate the task list to the combining tree root level in order to prevent premature grace period termination. The task list can remain at the leaf level. In this way, CPU hotplugging is accommodated while avoiding excessive degradation of real-time latency stemming from the now-eliminated task list migration.

Abstract: A grace period detection technique for a preemptible read-copy update (RCU) implementation that uses a combining tree for quiescent state tracking. When a leaf level bitmask indicating online/offline CPUs is fully cleared due to all of its assigned CPUs going offline as a result of hotplugging operations, the bitmask state is not immediately propagated to the root level of the combining tree as in prior art RCU implementations. Instead, propagation is deferred until all tasks are removed from an associated leaf level task list tracking tasks that were preempted inside an RCU read-side critical section. Deferring bitmask propagation obviates the need to migrate the task list to the combining tree root level in order to prevent premature grace period termination. The task list can remain at the leaf level. In this way, CPU hotplugging is accommodated while avoiding excessive degradation of real-time latency stemming from the now-eliminated task list migration.

Abstract: The present invention relates to a temporal base method of mutual exclusion control of a shared resource. The invention will usually be implemented by a plurality of host computers sharing a shared resource where each host computer will read a reservation memory that is associated with the shared resource. Typically a first host computer will perform and initial read of the reservation memory and when the reservation memory indicates that the shared resource is available, the first host computer will write to the reservation memory. After a time delay, the host computer will read the reservation memory again to determine whether it has won access to the resource. The first host computer may determine that it has won access to the shared resource by checking that data in the reservation memory includes an identifier corresponding to the first host computer.

Abstract: A mainframe computing system includes a central processor complex, a plurality of billing entities, each billing entity having a respective capacity limit, and a workload manager that schedules work requested by the plurality of billing entities on the central processor complex and tracks, by billing entity, a rolling average of millions of service units. The mainframe also includes a dynamic capping policy that identifies a maximum MSU limit, a maximum cost limit, a subset of the plurality of billing entities, and, for each billing entity in the subset, information from which to determine a MSU entitlement value and cost entitlement value. The mainframe also includes a dynamic capping master that adjusts the respective capacity limits of the subset of the plurality of billing entities at scheduled intervals based on the dynamic capping policy to favor billing entities having high-importance workload within the maximum MSU limit and maximum cost limit.

Abstract: A scalable concurrent queue includes a central queue associated with multiple temporary queues for holding batches of nodes from multiple producers. When a producer thread or service performs an insertion operation on the scalable concurrent queue, the producer inserts one or more nodes into a batch in one of the multiple temporary queues associated with the central queue. Subsequently, the producer (or another producer) inserts the batch held in the temporary queue into the central queue. Contention between the multiple producers is reduced by providing multiple temporary queues into which the producers may insert nodes, and also by inserting nodes in the central queue in batches rather than one node at a time. The scalable concurrent queue scales to serve large number of producers with reduced contention thereby improving performance in a distributed data grid.

Abstract: A system and method of parallelizing programs assigns write tokens and read tokens to data objects accessed by computational operations. During run time, the write sets and read sets for computational operations are resolved and the computational operations executed only after they have obtained the necessary tokens for data objects corresponding to the resolved write and read sets. A data object may have unlimited read tokens but only a single write token and the write token may be released only if no read tokens are outstanding. Data objects provide a wait list which serves as an ordered queue for computational operations waiting for tokens.

Abstract: A reconfigurable processor based on mini-cores (MCs) includes a plurality of MCs, each MC of the MCs including a group of function units (FUs), the group of FUs having a capability of executing a loop iteration independently. The MCs include a first MC configured to execute a first loop iteration, and a second MC configured to execute a second loop iteration.

Abstract: Some embodiments provide a method to extract metadata of MIME attachments or other distinguishable MIME parts of MIME emails into virtual emails. The virtual emails do not contain the full MIME attachment data but instead include some or all header fields of the parent email which contains the MIME attachment and a link to the MIME part of the MIME attachment in this email. The virtual emails may be stored in a separate namespace, or a folder which may be hidden from some IMAP clients, on an IMAP server. The virtual emails may be indexed by the IMAP server like any other email. Virtual emails may be created when new emails arrive on the IMAP server and synchronized automatically, e.g., when the parent email changes. As such, standard IMAP commands like FETCH, SEARCH, SORT, THREAD, etc. may be used for virtual emails.

Abstract: Embodiments of the technology can provide steering of one or more I/O resources to compute subsystems on a system-on chip (SoC). The SoC may include a first I/O subsystem comprising a plurality of first I/O resources and a second I/O subsystem comprising a plurality of second I/O resources. A steering engine may steer at least one of the first I/O resources to either a network compute subsystem or to a server compute subsystem and may steer at least one of the second I/O resources to either the network compute subsystem or to the server compute subsystem.

Abstract: A system and method for distributed computing, including executing a job of distributed computing on compute nodes. The speed of parallel tasks of the job executing on the compute nodes are adjusted to increase performance of the job or to lower power consumption of the job, or both, wherein the adjusting is based on imbalances of respective speeds of the parallel tasks.

Abstract: A system for providing a stateful virtual compute system is provided. The system may be configured to maintain a plurality of virtual machine instances. The system may be further configured to receive a request to execute a program code and select a virtual machine instance to execute the program code on the selected virtual machine instance. The system may further associate the selected virtual machine instance with shared resources and allow program codes executed in the selected virtual machine instance to access the shared resources.

Abstract: Methods and systems for performing garbage collection involving sensitive information on a mobile device are described herein. Secure information is received at a mobile device over a wireless network. The sensitive information is extracted from the secure information. A software program operating on the mobile device uses an object to access the sensitive information. Secure garbage collection is performed upon the object after the object becomes unreachable.

Abstract: Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode units are configured to reduce power provided to the processor core when the processor core has one or more threads in pending status and no threads in active status. An operand of an instruction being processed by a thread may be data in memory located outside processor core. If the processor core does not require as much power to operate while a thread waits for a request from outside the processor core, the power consumed by the processor core can be reduced during these waiting periods. Power can be conserved in the processor core even when threads are being processed if the only threads being processed are in pending status, and can reduce the overall power consumption in the processor core and its corresponding CPU.

Abstract: Causing a processor to execute a plurality of tasks includes determining a count for each task to be executed, determining a total count representing a sum of all counts for all tasks to be included in a run list, and constructing the run list by distributing corresponding entries for each task within the run list a number of times in accordance with each task's weighting factor. The weighting factor corresponds to a ratio of the each task's count with respect to a total count. Causing a processor to execute a plurality of tasks may also include executing the tasks in the run list in a round-robin manner where a particular entry in the run list is skipped in response to a corresponding task having previously relinquished a slot prior to expiration of time allotted for the task to run in the slot.

Abstract: A method and apparatus to alter acoustic noise induced by processor performance changes is disclosed. In one embodiment, a processor having one or more processor cores may execute instructions of one or more applications. The performance level (e.g., supply voltage and/or clock frequency) may be adjusted in accordance with workload demands. One or more of the applications executing on a core of the processor may exhibit periodic behavior, thereby causing periodic changes (e.g., increases) in the performance level. Performance monitoring may be conducted and may detect the periodic changes in the workload of the application. Responsive to the detection of the periodic changes, a power management unit may subsequently cause future performance level changes associated with the application to occur aperiodically.

Abstract: A method according to one embodiment includes the operations of receiving a list of one or more data race analysis targets, wherein the data race analysis targets comprise at least one of a source file name, source file line, function name, variable name or target address range; generating a data race analysis filter, wherein the data race analysis filter comprises a data structure including memory address ranges based on the list of data race analysis targets; and performing a data race analysis on a memory access, wherein the memory access is associated with memory addresses included in the data race analysis filter.

Abstract: Disclosed herein are representative embodiments of methods, systems, and apparatus that can used to control real-time events (e.g., the real-time clock) during the design, simulation, or verification of an embedded system. In one exemplary embodiment disclosed herein, for example, a real-time clock signal is generated and tasks defined by an embedded software application are triggered with the real-time clock signal. In this embodiment, the embedded software application is executed by an embedded processor with a real-time operating system (“RTOS”), and the real-time clock signal is controllable independent of a processor clock signal driving the embedded processor in a manner that allows the real-time clock to have a different time base than the processor clock.

Abstract: Techniques for increased destaging efficiency by smoothing destaging tasks to reduce long input/output (I/O) read operations are described. A system may comprise a processor device operable in the computing storage environment. The processor device calculates a current number of the destaging tasks and calculates a desired number of the destaging tasks. The processor device smoothes the destaging of the of the destaging tasks between the desired number of the destaging tasks and the current number of the destaging tasks by accelerating the calculating of the current number of the destaging tasks and the desired number of the destaging tasks, according to either a time interval or a variable recomputed destaging task interval, for reaching the desired number of the destaging tasks by decrementing the current number of destaging tasks or incrementing the current number of destaging tasks.

Abstract: Techniques for increased destaging efficiency by smoothing destaging tasks to reduce long input/output (I/O) read operations are described. A method may comprise a processor device operable in the computing storage environment. The processor device destages tasks are calculated according to one of a standard time interval and a variable recomputed destaging task interval. The destaging of storage tracks between a desired number of destaging tasks and a current number of destaging tasks is smoothed according to the calculating.

Abstract: The present disclosure extends to maintaining an item inventory status at an inventory cache management system. The inventory cache may be refreshed regularly by a threshold-based triggering mechanism. In embodiments, as item inventory breaches certain thresholds, the inventory cache may be refreshed with increased frequency to mitigate overselling or underselling scenarios and reduce overall network traffic for items having relatively high inventory levels.

Abstract: Systems and methods of enhancing computing performance may provide for detecting a request to acquire a lock associated with a shared resource in a multi-threaded execution environment. A determination may be made as to whether to grant the request based on a context-based lock condition. In one example, the context-based lock condition includes a lock redundancy component and an execution context component.

Abstract: A method, system, and apparatus to divide a computing job into micro-jobs and allocate the execution of the micro-jobs to times when needed resources comply with one or more idleness criteria is provided. The micro-jobs are executed on an ongoing basis, but only when the resources needed by the micro-jobs are not needed by other jobs. A software program utilizing this methodology may be run at all times while the computer is powered up without impacting the performance of other software programs running on the same computer system.

Abstract: A method and apparatus for outputting data is provided. The method includes outputting a first web page containing streaming data, before the streaming data is completely reproduced, when a request to output a second web page is received, outputting the second web page while continuously receiving the streaming data, and when data of an amount that is appropriate to continuously reproduce the streaming data without data delay is received, announcing that the streaming data is capable of being reproduced.

Abstract: A method and a device for loading a virtual machine application are provided herein. An exemplary method comprises: loading a management object of the virtual machine by the layer-booting object; reading the virtual machine configuration by the management object of the virtual machine; and invoking a creation function of the management object of the virtual machine by the virtual machine configuration and creating an operational instance of the virtual machine. The Android loading method and device for a virtual machine can be used to improve switching speed between instances.

Abstract: A system and method for controlling processor instruction execution. In one example, a method for synchronizing a number of instructions performed by processors includes instructing a first processor to iteratively execute instructions via a first set of iterations until a predetermined time period has elapsed. A number of instructions executed in each iteration of the first set of iterations is less than a number of instructions executed in a prior iteration of the first set of iterations. The method also includes instructing a second processor to iteratively execute instructions via a second set of iterations until the predetermined time period has elapsed. A number of instructions executed in each iteration of the second set of iterations is less than a number of instructions executed in a prior iteration of the second set of iterations. The method includes determining whether additional instructions are to be executed.

Abstract: A task execution controller includes a context generating unit that generates context information concerning a user and a surrounding situation of the user; a task managing unit that stores multiple tasks the user attempts to execute, selects a task according to the context information and a predetermined task selection rule, and controls execution of the task; and a service managing unit that confirms services executed by a device used for execution of the task, gives notification of a service corresponding to the execution of the task selected by the task managing unit, to the device and causes the device to perform the service. The task managing unit selects a task by using, as the task selection rule, information of priority levels of tasks and an execution-related dependency relation between tasks preset among the tasks.

Abstract: A system, method, and computer program product are provided for altering a line of code. In use, a line of code is identified, where the line of code is written utilizing both a programming language and one or more syntax extensions to the programming language. Additionally, the line of code is altered so that the altered line of code is written using only the programming language. Further, the altered line of code is returned.

Abstract: A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command.

Abstract: A middleware processor provisioning process provisions a plurality of processors in a multi-processor environment. The processors themselves may be subdivided in to one or more partitions or processing instances for which a single processing queue is created and a single kernel thread is started. User processing requests are portioned and dispatched across the plurality of processing queues and are serviced by the corresponding kernel process, thereby efficiently using available processing resources while servicing the user processing requests in a desired manner.

Abstract: A method and system for performing garbage collection involving sensitive information on a mobile device. Secure information is received at a mobile device over a wireless network. The sensitive information is extracted from the secure information. A software program operating on the mobile device uses an object to access the sensitive information. Secure garbage collection is performed upon the object after the object becomes unreachable.

Abstract: Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.

Abstract: A middleware processor provisioning process provisions a plurality of processors in a multi-processor environment. The processors themselves may be subdivided in to one or more partitions or processing instances for which a single processing queue is created and a single kernel thread is started. User processing requests are portioned and dispatched across the plurality of processing queues and are serviced by the corresponding kernel process, thereby efficiently using available processing resources while servicing the user processing requests in a desired manner.

Abstract: A graphics processing unit, method, computer readable media, and system are described herein. The graphics processing unit includes at least one execution unit, the execution unit configured to execute a shader. The shader includes instructions that causes the execution unit to process a plurality of pixels in parallel until each of the plurality of pixels is discarded and execution of a last write instruction, and execute a conditional end of thread instruction after each of the plurality of pixels is discarded and after execution of the last write instruction, wherein execution of the conditional end of thread instruction is to terminate the thread.

Abstract: There is provided with an information processing apparatus for controlling execution of a plurality of threads which run on a plurality of calculation cores connected to a memory including a plurality of banks. A first selection unit is configured to select a thread as a continuing thread which receives data from other thread, out of threads which process a data group of interest, wherein the number of accesses for a bank associated with the selected thread is less than a predetermined count. A second selection unit is configured to select a thread as a transmitting thread which transmits data to the continuing thread, out of the threads which process the data group of interest.

Abstract: Embodiments of the present invention provide a scheduling implementation method, apparatus, and system. The method includes: according to a processing delay and user priority information of a user processing request, determining a priority to which the user processing request currently belongs; if the user processing request is not recorded in a priority queue corresponding to the priority to which the user processing request currently belongs, writing the user processing request into the priority queue corresponding to the priority to which the user processing request currently belongs; and in a situation that a processing apparatus is in an idle state, reading a user processing request in a non-empty priority queue with a highest priority, and if the user processing request with the highest priority does not time out, sending the user processing request with the highest priority to the processing apparatus.

Abstract: A method for executing and polling an operational slice of a supply capability engine. The method of polling is designed to query a DB2 table searching for a predetermined, eligible operational slice to process. When an operational slice is detected that is ready to be processed, an entry on a queue is placed, typically to a second DB2 table. The operational slices on the queue are then processed sequentially. The poller monitors the duration of the operational slice, and generates an alert if any of the operational slices placed on the queue exceed an allowable duration.

Abstract: One or more virtual processors can be added or removed from a virtual machine based on CPU pressure measured within the virtual machine. In addition to the foregoing, CPU pressure can also be used to determine whether to remove a virtual processor from a virtual machine, which may cause the computer system to consume less power. In the alternative, virtual processors can be parked and/or unparked in order to reduce the amount of power consumed by the virtual machine. In addition, virtual processors can be forcibly parked during a migration operation.

Abstract: Techniques for handling events are provided. In one embodiment, a computer system can create a plurality of I/O handles for receiving events. The computer system can further partition the plurality of I/O handles into one or more subsets, where events received via I/O handles in the same subset are correlated and events received via I/O handles in different subsets are uncorrelated. The computer system can then delegate each I/O handle in the plurality of I/O handles to a poll thread in a plurality of poll threads, where I/O handles in the same subset are delegated to the same poll thread.

Abstract: In some implementations, a processor is configured to receive a current pending packet number representing a number of packets of data that currently remain to be transferred between two devices, determine whether to adjust a priority of a thread based on the current pending packet number, a previous pending packet number, and a priority pending packet number, and adjust or maintain the priority of the thread based on determining whether to adjust the priority of the thread. The thread is to be executed by the processor to perform a transfer of the packets of data between the two devices, the previous pending packet number represents a number of packets of data that previously remained to be transferred between the two devices, and the priority pending packet number corresponds to the current priority of the thread.

Abstract: An Email processing method and system comprising in response to obtaining an Email, parsing contents of the Email to obtain an Email subject identifier of the Email, at least one new interaction record, and interaction information corresponding to the at least one new interaction record; determining whether there is a merged Email, which has a merge Email subject identifier matching a subject identifier of the Email, and conforms to a predefined interaction content structure comprising at least one interaction record divided by interaction relationship of contents; and in response to that the determination result is yes, merging the at least one new interaction record of the Email into the merged Email to generate a new merged Email based on the interaction information corresponding to the at least one new interaction record.

Abstract: Services for a personal electronic device are provided through which a form of background processing or multitasking is supported. The disclosed services permit user applications to take advantage of background processing without significant negative consequences to a user's experience of the foreground process or the personal electronic device's power resources. To effect the disclosed multitasking, one or more of a number of operational restrictions may be enforced. By way of example, thread priority levels may be overlapped between the foreground and background states. In addition, system resource availability may be restricted based on whether a process is receiving user input. In some instances, an application may be suspended rather than being placed into the background state. Implementation of the disclosed services may be substantially transparent to the executing user applications and, in some cases, may be performed without the user application's explicit cooperation.