Abstract: An information technology services management product is provided with a change management component that identifies conflicts based on a wide range of information. When a change on a configuration item is scheduled, the change management component identifies, for example, affected business applications, affected service level agreements, resource availability, change schedule, workflow, resource dependencies, and the like. The change management component warns the user if a conflict is found. The user does not have to consult multiple sources of information and make a manual determination concerning conflicts. The change management component may also suggest a best time to schedule a change request based on the information available. The change management component provides a constrained interface such that the user cannot schedule a change request that violates any of the above requirements. The change management component also applies these requirements when changing an already scheduled change request.

Abstract: One embodiment of the present invention provides a method for supporting the development of a parallel/distributed application, wherein the development process comprises a design phase, an implementation phase and a test phase. A script language can be provided in the design phase for representing elements of a connectivity graph and the connectivity between them. In the implementation phase, modules can be provided for implementing functionality of the application, executors can be provided for defining a type of execution for the modules, and process-instances can be provided for distributing the application over several computing devices. In the test phase, abstraction levels can be provided for monitoring and testing the application.

Abstract: A sandbox tool can cooperate with components of a secure operating system to create an isolated execution environment for accessing untrusted content without exposing other processes and resources of the computing system to the untrusted content. The sandbox tool can allocate resources (storage space, memory, etc) of the computing system, which are necessary to access the untrusted content, to the isolated execution environment, and apply security polices of the operating system to the isolated execution environment such that untrusted content running in the isolated execution environment can only access the resources allocated to the isolated execution environment.

Abstract: One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value that may be static or computed during execution of a shader program. Any texture operation instruction may specify an index value for each of the texture header and the texture sampler.

Abstract: A multi-core system enabling cores to simultaneously execute a task includes memory storing task information including for each task, deadline information indicating a deadline for completion of the task and execution period information indicating an execution period of the task, for cache utilization rates of each core, and power information including for each core, source voltage information indicating a source voltage enabling the core to operate and power deriving information deriving power consumption based on the source voltage; and a core configured to: estimate a process period of the task, based on the execution period information and usable-cache size information, and set a task assignment pattern so that within a range where the estimated process period satisfies a real-time restriction by the deadline information, a cache size used by the task and power consumption that is based on the source voltage information and the power deriving information are minimized.

Abstract: An apparatus and method provide for profile optimizations at a binary level. Thread specific data may be used to lay out a procedure in a binary. In one example, a hot thread may be identified and a layout may be generated based on the identified hot thread. Also, threads of an application may be ranked according to frequency of execution of the corresponding threads. The layout may be created based on the different threads of differing frequency of execution and conflicts between a hottest thread and each of the other threads of the application. In another example, different threads of the application may conflict. For example, two threads may contain operations that overlap temporally to create a race condition. A layout of the application threads may be created based on conflicting threads.

Abstract: Some computing devices have limited resources such as, for example, battery power. When a user ceases to interact with an application, execution of the application can be moved to background and the application can be paused. During the time period in which the application is paused, the application consumes no CPU cycles because executing managed threads of the paused application are stopped, and native threads are prevented from running using asynchronous procedure calls.

Abstract: One embodiment of the present invention sets forth a technique for partitioning a predecessor thread program into sub-programs and dynamically spawning a thread grid of the sub-programs based on the outcome of a conditional statement in the predecessor thread program. The programming instructions for the predecessor thread program are analyzed to assess the benefit of partitioning the thread program at a conditional statement into sub-programs. If the predecessor thread program is partitioned, then each branch of the conditional statement may be used to form a separate sub-program. Predicate tables are populated at the predecessor thread program run-time to establish which possible instances of the thread sub-programs should be spawned in subsequent execution phases.

Abstract: A technique for managing read-copy update readers that have been preempted while executing in a read-copy update read-side critical section. A single blocked-tasks list is used to track preempted reader tasks that are blocking an asynchronous grace period, preempted reader tasks that are blocking an expedited grace period, and preempted reader tasks that require priority boosting. In example embodiments, a first pointer may be used to segregate the blocked-tasks list into preempted reader tasks that are and are not blocking a current asynchronous grace period. A second pointer may be used to segregate the blocked-tasks list into preempted reader tasks that are and are not blocking an expedited grace period. A third pointer may be used to segregate the blocked-tasks list into preempted reader tasks that do and do not require priority boosting.

Abstract: A program is executed utilizing a main hardware thread. During execution, an instruction specifies to execute a portion utilizing a worker hardware thread. If a processor state indicator is set to multi-threaded, the specified portion is executed utilizing the worker hardware thread. However, if the processor state indicator is set to single-threaded, the specified portion is executed utilizing the main hardware thread as a subroutine. The main hardware thread may pass parameter data to the worker hardware thread by copying the parameter data register or memory location for the main hardware thread to an equivalent parameter data register or memory location for the worker hardware thread. Similarly, the worker hardware thread may pass return values to the main hardware thread by copying a return value register or memory location for the worker hardware thread to an equivalent return value register or memory location for the main hardware thread.

Abstract: A method, for monitoring resources of a system for performing a first task and a second task, includes calculating a first completion count of the first task; calculating a second completion count of the second task; and determining whether the resources of the system are exhausted according to the first completion count and the second completion count.

Abstract: A method for distributing a task to plural processors is provided. A distribution rule of distributing plural tasks to sub processors or the main processor, respectively, is previously written in a program code of an application configured to include plural tasks. At the time of executing the application, the main processor reads out the distribution rule, and distributes plural tasks to the sub processors or the main processor, respectively, in accordance with the distribution rule.

Abstract: A multi-thread processor in accordance with an exemplary aspect of the present invention includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal TSEL designating a hardware thread to be executed in a next execution cycle, a first selector that outputs an instruction generated by a hardware thread selected according to the thread selection signal, and an execution pipeline that executes an instruction output from the first selector, wherein the thread scheduler specifies execution of at least one hardware thread selected in a fixed manner in a predetermined first execution period, and specifies execution of an arbitrary hardware thread in a second execution period.

Abstract: Two or more processors that each provides a specified thread to access a shared resource that can only be accessed by one thread at a given time. A locking mechanism enables one of the threads to access the shared resource while other threads are retained in a waiting queue. Responsive to an additional thread that is not one of the specified threads being provided access the shared resource during an identified time period, and responsive to a first criterion an a second criterion being met, the additional thread accesses the shared resource before the other threads in the waiting queue.

Abstract: Provided are a method, system, and program for executing multiple threads in a processor. Credits are set for a plurality of threads executed by the processor. The processor alternates among executing the threads having available credit. The processor decrements the credit for one of the threads in response to executing the thread and initiates an operation to reassign credits to the threads in response to depleting all the thread credits.

Abstract: Method, system, and computer program product embodiments for synchronizing workitems on one or more processors are disclosed. The embodiments include executing a barrier skip instruction by a first workitem from the group, and responsive to the executed barrier skip instruction, reconfiguring a barrier to synchronize other workitems from the group in a plurality of points in a sequence without requiring the first workitem to reach the barrier in any of the plurality of points.

Abstract: A method, computer program product, and computer system for shared execution of mixed data flows, performed by one or more computing devices, comprises identifying one or more resource sharing opportunities across a plurality of parallel tasks. The plurality of parallel tasks includes zero or more relational operations and at least one non-relational operation. The plurality of parallel tasks relative to the relational operations and the at least one non-relational operation are executed. In response to executing the plurality of parallel tasks, one or more resources of the identified resource sharing opportunities is shared across the relational operations and the at least one non-relational operation.

Abstract: A method for deterministic locking in a parallel computing environment is provided. The method includes creating a data structure in memory of a computer for a shared resource. The data structure encapsulates a reference to an owner of a lock for the shared resource and a queue of threads able to seek exclusive access to the shared resource. The queue in turn includes different entries, each entry including an identifier for a corresponding one of the threads and a deterministic time computed for the corresponding one of the threads from a count of memory accesses occurring in the corresponding one of the threads. Consequently, a thread can be selected from the queue to receive ownership of the lock and exclusive access to the shared resource based upon a deterministic time for the selected thread as compared to other deterministic times for others of the threads in the queue, for example, a lowest deterministic time.

Abstract: A network device establishes a logical channel with each server device of multiple server devices, where each logical channel is not shared with another server device of the multiple server devices. The network device also determines a network loopback Internet protocol (IP) address for each server device of the multiple server devices, and associates each network loopback IP address with a corresponding logical channel. The network device further receives a packet destined for a particular server device, and provides the packet to the particular server device via the logical channel associated with the particular server device.

Abstract: A method for deterministic locking in a parallel computing environment is provided. The method includes creating a data structure in memory of a computer for a shared resource. The data structure encapsulates a reference to an owner of a lock for the shared resource and a queue of threads able to seek exclusive access to the shared resource. The queue in turn includes different entries, each entry including an identifier for a corresponding one of the threads and a deterministic time computed for the corresponding one of the threads from a count of memory accesses occurring in the corresponding one of the threads. Consequently, a thread can be selected from the queue to receive ownership of the lock and exclusive access to the shared resource based upon a deterministic time for the selected thread as compared to other deterministic times for others of the threads in the queue, for example, a lowest deterministic time.

Abstract: Task scheduling in a processing system having a main memory and a processor having a plurality of software-configurable registers is disclosed. The processor may be a synergistic processing unit (SPU) of a cell processor. The processing system operates under the control of a kernel and a program code. A subset of the plurality of software-configurable registers is reserved for use by the kernel. Upon occurrence of an interrupt event requiring control of the processor by the kernel, the kernel may be run on the processor without saving the contents the plurality of registers.

Abstract: A method for determining the task load in real-time. The method takes a difference in real-time between a first count value from a free running counter prior to a task executing, and a second count value after the task stops running. The task load may then be determined by using an accumulator to accumulate the difference between the first count value and the second count value over a reference interval and dividing the sum by a configurable reference interval. The individual task load computed in real-time may be used in scheduling an audio task.

Abstract: A method and mechanism for using threads in a computing system. A multithreaded computing system is configured to execute a first thread and a second thread. Responsive to the first thread detecting a launch point for a function, the first thread is configured to provide an indication to the second thread that the second thread may begin execution of a given function. The launch point of the function precedes an actual call point of the function in an execution sequence. The second thread is configured to initiate execution of the function in response to the indication. The function includes one or more inputs and the second thread uses anticipated values for each of the one or more inputs. When the first thread reaches a call point for the function, the first thread is configured to use a results of the second thread's execution, in response to determining the anticipated values used by the second thread were correct.

Abstract: Information about a job is left correctly on a user-by-user basis while minimizing a work load on a user. In a method for controlling a job processing system, a user logs in to a job processing apparatus having an operation unit and a job processing unit and causes the job processing unit to execute a job using the operation unit. The method includes, permitting, in a state in which a first user has been logged in to the job processing apparatus, a second user to log into the job processing apparatus, storing information about a job as information about the second user in a storage unit, in the case where the second user logs in to the job processing apparatus in the state in which a first user has been logged in to the job processing apparatus, and the second user issues an instruction to the job processing unit to execute the job using the operation unit.

Abstract: In a method of scheduling tasks for controlling hardware devices, a specified task having the execution right in a current time slice is terminated by depriving the execution right therefrom, when a time during which the execution right continues reaches the activation time given to the specified task. An identification process is performed when each reference cycle has been completed or each task has been terminated. In the identification process, i) when there remain, time-guaranteed tasks which have not been terminated in the current time slice, a time-guaranteed task whose priority is maximum among the remaining tasks is identified, and ii) when there remain no un-terminated time-guaranteed tasks in the current slice, of remaining non-time-guaranteed tasks which are not terminated yet in the current time slice, a non-time-guaranteed task whose priority is maximum is identified. The execution right is assigned to the identified task through the identification process.

Abstract: A device stores a plurality of applications and a list of associations for those applications. The applications are preferably stored within a secondary memory of the device, and once launched each application is loaded into RAM. Each application is preferably associated to one or more of the other applications. Preferably, no applications are launched when the device is powered on. A user selects an application, which is then launched by the device, thereby loading the application from the secondary memory to RAM. Whenever an application is determined to be associated with a currently active state application, and that associated application has yet to be loaded from secondary memory to RAM, the associated application is pre-launched such that the associated application is loaded into RAM, but is set to an inactive state.

Abstract: The present invention is directed to methods and systems for rendering perceivable stimuli representative of information processing by a multi-tenant architecture that pre-fetches a portion of a subset of data on a multi-tenant architecture and emulates a result set of data in accordance with a report definition. To that end the method comprises identifying a subset of data on the multi-tenant architecture that is subject to a report definition. A portion of the subset is pre-fetched and analyzed to emulate a result. The emulated result is transmitted to a computer system of a user of the multi-tenant architecture. Perceivable stimuli is generated on the user computer system, in response to receiving the emulated result.

Abstract: A memory swap management method that can preferentially place in a primary storage device a process that has a high possibility of being executed next, thereby shortening the time to start executing the next process. A planned execution sequence of jobs is stored when there are a plurality of jobs waiting to be executed. A process as a swap-out candidate and a process as a swap-in candidate are determined based on the execution sequence and types of processes stored in the primary storage device. According to the determination, the process as the swap-out candidate is swapped out from the primary storage device to a secondary storage device, and the process as the swap-in candidate is swapped in from the secondary storage device into an area of the primary storage device freed as a result of the swap-out.

Abstract: A hard real time (HRT) thread scheduler and a non-real time (NRT) thread scheduler for allocating processor resources among HRT threads and NRT threads are disclosed. The HRT thread scheduler communicates with a HRT thread table including a plurality of entries specifying a temporal order for allocating execution cycles to one or more HRT threads. If a HRT thread identified by the HRT thread table is unable to be scheduled during the current execution cycle, the NRT thread scheduler accesses an NRT thread table which includes a plurality of entries specifying a temporal order for allocating execution cycles to one or more NRT threads. In an execution cycle where a HRT thread is not scheduled, the NRT thread scheduler identifies an NRT thread from the NRT thread table and an instruction from the identified NRT thread is executed during the execution cycle.

Abstract: Various technologies and techniques are disclosed for switching threads within routines. A controller routine receives a request from an originating routine to execute a coroutine, and executes the coroutine on an initial thread. The controller routine receives a response back from the coroutine when the coroutine exits based upon a return statement. Upon return, the coroutine indicates a subsequent thread that the coroutine should be executed on when the coroutine is executed a subsequent time. The controller routine executes the coroutine the subsequent time on the subsequent thread. The coroutine picks up execution at a line of code following the return statement. Multiple return statements can be included in the coroutine, and the threads can be switched multiple times using this same approach. Graphical user interface logic and worker thread logic can be co-mingled into a single routine.

Abstract: Multi-threaded processing with reduced context switching is disclosed. Context switches may be avoided through the use of pre-emption notification, a pre-emption wait time attribute and a no-context-save yield.

Abstract: An embodiment of the invention provides an apparatus and a method for direct switching of software threads. The apparatus and method include performing acts including: issuing a wakeup call from a first thread to a second thread in a sleep state; removing the second thread from the sleep state; switching out the first thread from the resource; switching in the second thread to the resource; and running the second thread on the resource.

Abstract: Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-processor. In a particular embodiment, a method is disclosed that includes collecting data from a plurality of software threads being processed by a processor, where the data for each of the events includes a value of an associated clock cycle counter upon occurrence of the event. Data is correlated for the events occurring for each of the plurality of threads by starting each of a plurality of clock cycle counters associated with the software threads at a common time. Alternatively, data is correlated for the events by logging a synchronizing event within each of the plurality of software threads.

Abstract: A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

Abstract: The present invention relates generally to computer operating systems, and more specifically, to operating system calls in a symmetric multiprocessing (SMP) environment. Existing SMP strategies either use a single lock or multiple locks to limit access to critical areas of the operating system to one thread at a time. These strategies suffer from a number of performance problems including slow execution, large software and execution overheads and deadlocking problems. The invention applies a single lock strategy to a micro kernel operating system design which delegates functionality to external processes. The micro kernel has a single critical area, the micro kernel itself, which executes very quickly, while the external processes are protected by proper thread management. As a result, a single lock may be used, overcoming the performance problems of the existing strategies.

Abstract: A technique for processing instructions in an electronic system is provided. In one embodiment, a processor of the electronic system may submit a unit of work to a queue accessible by a coprocessor, such as a graphics processing unit. The coprocessor may process work from the queue, and write a completion record into a memory accessible by the processor. The electronic system may be configured to switch between a polling mode and an interrupt mode based on progress made by the coprocessor in processing the work. In one embodiment, the processor may switch from an interrupt mode to a polling mode upon completion of a threshold amount of work by the coprocessor. Various additional methods, systems, and computer program products are also provided.

Abstract: An embodiment can include one or more computer readable media storing executable instructions for performing execution scheduling for code generated from an executable graphical model. The media can store instructions for accessing a first code portion having a first priority, and a second code portion having a second priority, where the second priority has a relationship with the first priority. The media can store instructions for accessing target environment characteristics that indicate a performance of the target environment, and for performing execution scheduling for the first code portion and the second code portion, the execution scheduling taking into account the target environment characteristics, the execution scheduling using an execution schedule.

Abstract: A computer implemented method, apparatus, and computer program product for sampling call stack information. A set of methods and a set of criteria are received. Responsive to detecting an event associated with a method in the set of methods, a determination is made as to whether the method has met a set of criteria comprising at least one of a time based metric and a hardware performance monitor counter metric. A call stack is retrieved for the method if the method has met the set of criteria. The retrieved call stack is saved in a tree.

Abstract: Systems and methods for efficient execution of operations in a multi-threaded processor. Each thread may include a blocking instruction. A blocking instruction blocks other threads from utilizing hardware resources for an appreciable amount of time. One example of a blocking type instruction is a Montgomery multiplication cryptographic instruction. Each thread can operate in a thread-based mode that allows the insertion of stall cycles during the execution of blocking instructions, during which other threads may utilize the previously blocked hardware resources. At times when multiple threads are scheduled to execute blocking instructions, the thread-based mode may be changed to increase throughput for these multiple threads. For example, the mode may be changed to disallow the insertion of stall cycles. Therefore, the time for sequential operation of the blocking instructions corresponding to the multiple threads may be reduced.

Abstract: The present invention describes a method for securing the execution of a computer program in a multitask device. This method is based on the execution, in parallel with the program to be made secure, of a security thread, able to modify the parameters of the scheduler.

Abstract: Two threads may communicate via shared memory using two different modes. In a polling mode, a receiving thread may poll an indicator set by the sending thread to determine if a message is present. In a blocking mode, the receiving thread may wait until a synchronization object is set by the sending thread which may cause the receiving thread to return to the polling mode. The polling mode may have low latency buy may use processor activity of the receiving thread to repetitively check the indictor. The blocking mode may have a higher latency but may allow the receiving thread to enter a sleep mode or perform other activities.

Abstract: A wireless communication device that has one or more applications resident on a computer platform, a wireless communication interface, a display, and a user interface that, at least, appears on the display and through which a user of the wireless communication device interacts with the computer platform. The display is configured to be selectively controlled by the specific user interfaces of one or more applications resident on the computer platform, and the one or more applications and/or an arbiter that is resident on the computer platform will determine which user interface of the one or more applications resident on the computer platform controls the display based upon a predetermined criteria when the user interfaces compete for control of the display.

Abstract: A comparator unit for two Nm-bit data words, comprises a comparison output indicative of an order relation between the two data words, the function of the comparison unit being represented by a logic table comprising rows associated with the possible consecutive values of the first data word and columns associated with the possible consecutive values of the second data word, where each row includes a one at the intersection with the column associated with the same value as the row, followed by a series of zeros. The series of zeros is followed by a series of ones completing the row circularly, the number of zeros being the same for each row and smaller than half of the maximum value of the data words.

Abstract: A method for executing a first and a second task in M time units is disclosed. The method includes comparing the priority of the first task and the task. If the first task has a higher priority than the second task, the first task is executed. The first task is then suspended after the first duration, and the second task is executed for a second duration.

Abstract: A computer program product for performing runtime analysis on and control of a multithreaded computer program. One embodiment of the present invention can include identifying threads of a computer program to be analyzed. Under control of a supervisor thread, a plurality of the identified threads can be folded together to be executed as a folded thread. The execution of the folded thread can be monitored to determine a status of the identified threads. An indicator corresponding to the determined status of the identified threads can be presented in a user interface that is presented on a display.

Abstract: A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.

Abstract: In a parallel computer executing a parallel application, where the parallel computer includes a number of compute nodes, with each compute node including one or more computer processors, the parallel application including a number of processes, and one or more of the processes executing a barrier operation, creating a checkpoint of a parallel application includes: maintaining, by each computer processor, global barrier operation state information, the global barrier operation state information includes an aggregation of each process's barrier operation state information; invoking, for each process of the parallel application, a checkpoint handler; saving, by each process's checkpoint handler as part of a checkpoint for the parallel application, the process's barrier operation state information; and exiting, by each process, the checkpoint handler.

Abstract: In an exemplary aspect, the present invention provides a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a first or second schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector, wherein when the multi-thread processor is in a first state, the thread scheduler selects the first schedule, and when the multi-thread processor is in a second state, the thread scheduler selects the second schedule.

Abstract: In an information processing apparatus according to the present invention, a control unit notifies each application program of a key input event in a multi-window system. If the state of a first application program is inactive, the control unit determines whether or not the event notified to the first application program is a key input event caused by a key other than an active switching key. If it is determined that the event is a key input event caused by a key other than the active switching key, the control unit causes a clock circuit to time a predetermined time period, and performs control so as to omit part of processing by the first application program, or to provide a predetermined wait time in between the processing by the first application program, until the predetermined time period is timed out.

Abstract: The present invention provides a method for obtaining predicable and repeatable output results in a continuous processing system. The method involves processing messages and primitives in accordance with the following rules: (1) Messages are processed in accordance with timestamps, where messages are divided up into “time slices”; (2) message order within a data stream is preserved among messages with the same time stamp; (3) subject to rule #4, for each time slice, a primitive is executed when either the messages within such time slice show up in the input stream for such primitive or the state of the window immediately preceding such primitive changes due to messages within such time slice; and (4) for each time slice, primitives that are dependent on one or more upstream primitives are not executed until such upstream primitives have finished executing messages in such time slice that are queued for processing.