Multitasking, Time Sharing Patents (Class 718/107)
  • Patent number: 8539499
    Abstract: A system, method and computer program product, including a primary operating system (OS) having access to at least some hardware resources of the computer system. A Hypervisor controls a plurality of virtualization spaces and at least some of the remaining hardware resources. Each virtualization space maintains data of a corresponding instance of a Virtual Machine with a guest operating system running inside the Virtual Machine. Each Virtual Machine is associated with at least one virtual processor. A hyperswitch controlled by the Hypervisor starts and stops execution of the Virtual Machines. A scheduler dedicates a quantum of running time to each virtual processor. When the quantum is given to the Virtual Machine, the Hypervisor forces the hyperswitch to activate the Virtual Machine on its virtual processor.
    Type: Grant
    Filed: February 18, 2008
    Date of Patent: September 17, 2013
    Assignee: Parallels IP Holdings GmbH
    Inventors: Sergei V. Tovpeko, Alexey B. Koryakin, Andrey A. Omelyanchuk, Alexander G. Tormasov, Nikolay N. Dobrovolskiy
  • Patent number: 8533734
    Abstract: A method includes receiving a start request from a client at a launcher application programming interface (API), determining whether an existing time sharing option (TSO) address space associated with a user of the client is available, retrieving security environment data associated with the user from a security product responsive to determining that no existing TSO address space associated with a user of the client is available, saving the retrieved security environment data as a security object, generating a message queue, generating a terminal status block (TSB) and saving the terminal status block, creating a TSO address space in a processor, sending an instruction to an operating system to start the TSO address space, and sending a message queue identifier associated with the message queue and an address space token associated with the TSO address space to the client.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: September 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Susan Z. Demkowicz, James M. Hertzig, Michael P. Kasper, Harris M. Morgenstern, Gary S. Puchkoff
  • Patent number: 8533428
    Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard Uhlig, Larry Smith, Dion Rodgers
  • Patent number: 8533721
    Abstract: A method and system to schedule out of order operations without the requirement to execute compare, ready and pick logic in a single cycle. A lazy out-of-order scheduler splits each scheduling loop into two consecutive cycles. The scheduling loop includes a compare stage, a ready stage and a pick stage. The compare stage and the ready stage are executed in a first of the two consecutive cycles and the pick stage is executed in a second of the two consecutive cycles. By splitting each scheduling loop into two consecutive cycles, selecting the oldest operation by default and checking the readiness of the oldest operation, it relieves the system of timing requirements and avoids the need for power hungry logic. Every execution of an operation does not appear as one extra cycle longer and the lazy out-of-order scheduler retains most of the performance of a full out-of-order scheduler.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Stephen J. Robinson, Deepak Limaye
  • Patent number: 8533719
    Abstract: The disclosed embodiments provide a system that facilitates scheduling threads in a multi-threaded processor with multiple processor cores. During operation, the system executes a first thread in a processor core that is associated with a shared cache. During this execution, the system measures one or more metrics to characterize the first thread. Then, the system uses the characterization of the first thread and a characterization for a second, second thread to predict a performance impact that would occur if the second thread were to simultaneously execute in a second processor core that is also associated with the cache. If the predicted performance impact indicates that executing the second thread on the second processor core will improve performance for the multi-threaded processor, the system executes the second thread on the second processor core.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: September 10, 2013
    Assignee: Oracle International Corporation
    Inventors: Alexandra Fedorova, David Vengerov, Kishore Kumar Pusukuri
  • Patent number: 8527999
    Abstract: The invention in particular has as an object supervising a scheduler for the management of processing time sharing in a multitask data-processing system comprising a computation unit having a standard execution mode and a preferred execution mode for executing a plurality of applications. The execution time for the said plurality of applications is divided into a plurality of periods and a minimal time for access per period to the said computation unit is determined for at least one application of the said plurality of applications. For at least one period, the said preferred execution mode is associated with the said at least one application and the said at least one application is executed according to at least the said minimal time for access to the said computation unit. For the said at least one period, the said standard execution mode is associated with the applications of the said plurality of applications and at least any one of the applications of the said plurality of applications is executed.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: September 3, 2013
    Assignee: Airbus Operations S.A.S.
    Inventors: Franck Dessertenne, Pierre Guirriec
  • Patent number: 8528001
    Abstract: A system and method for automatically controlling run-time parallelization of a software application. A buffer is allocated during execution of program code of an application. When a point in program code near a parallelized region is reached, demand information is stored in the buffer in response to reaching a predetermined first checkpoint. Subsequently, the demand information is read from the buffer in response to reaching a predetermined second checkpoint. Allocation information corresponding to the read demand information is computed and stored the in the buffer for the application to later access. The allocation information is read from the buffer in response to reaching a predetermined third checkpoint, and the parallelized region of code is executed in a manner corresponding to the allocation information.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: September 3, 2013
    Assignee: Oracle America, Inc.
    Inventors: Yonghong Song, Spiros Kalogeropulos, Partha P. Tirumalai
  • Patent number: 8521570
    Abstract: A process modeling tool provides a process designer with the ability to design a plurality of business process models that include tasks for achieving a desired result(s). The process modeling tool allows the process designer to merge the process models into a merged process model by replacing event flow coordinators within the process models with control flow coordinators that dictate a flow of the merged process model. Accordingly, the process designer is allowed to use the merged process model for monitoring of a current status of the tasks, and for re-distributing the tasks in a desired manner for execution by selected entities, while the original process models are maintained and may be executed in their original execution environment.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: August 27, 2013
    Assignee: SAP Aktiengesellschaft
    Inventor: Wasim Sadiq
  • Patent number: 8516494
    Abstract: Methods, apparatus, and products are disclosed for executing an application on a parallel computer that include: executing, by a current compute node, a current task of the application, including producing results; determining, by the current compute node in dependence upon current network characteristics and application characteristics, whether to transfer the results to a next compute node for further processing by a next task on the next compute node or to execute the next task for further processing of the results on the current compute node; transferring, by the current compute node, the results to the next compute node for further processing by the next task on the next compute node if the determination specifies transferring the results to the next node; and executing, by the current compute node, the next task for further processing of the results if the determination specifies executing the next task on the current compute node.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Eric L. Barsness, Michael B. Brutman, David L. Darrington, Amanda E. Peters, John M. Santousso
  • Publication number: 20130205304
    Abstract: A multi-tasking execution apparatus and a method for easily controlling applications running in a portable terminal are provided. The apparatus includes a display and a controller. The display displays an application-containing image in which at least one specific image representing at least one application running in a background is contained and arranged. The controller operatively displays at least one specific image representing at least one application running in the background, so as to be contained in the application-containing image, and controls the at least one application running in the background by controlling the specific image based on a specific gesture.
    Type: Application
    Filed: January 31, 2013
    Publication date: August 8, 2013
    Applicant: SAMSUNG ELECTRONICS CO. LTD.
    Inventor: Samsung Electronics Co. Ltd.
  • Patent number: 8504749
    Abstract: The invention relates to a spinlock-based multi-core synchronization technique in a real-time environment, wherein multiple processor cores perform spinning attempts to request a lock and the lock is allocated to at most one of the multiple cores for a mutually exclusive operation thereof. A method embodiment of the technique comprises the steps of allocating the lock to the first core requesting it; establishing for each core an indication of a waiting time for receiving the lock; selecting at least one of the spinning cores based on the waiting time indications; and, upon return of the lock, conditionally allocating the lock to the selected core, if the selected core performs a spinning attempt within a predefined time window starting with the return of the lock.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: August 6, 2013
    Assignee: Elektrobit Automotive GmbH
    Inventor: Claus Stellwag
  • Patent number: 8499305
    Abstract: Systems and methods for thread group kickoff and thread synchronization are described. One method is directed to synchronizing a plurality of threads in a general purpose shader in a graphics processor. The method comprises determining an entry point for execution of the threads in the general purpose shader, performing a fork operation at the entry point, whereby the plurality of threads are dispatched, wherein the plurality of threads comprise a main thread and one or more sub-threads. The method further comprises performing a join operation whereby the plurality of threads are synchronized upon the main thread reaching a synchronization point. Upon completion of the join operation, a second fork operation is performed to resume parallel execution of the plurality of threads.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: July 30, 2013
    Assignee: VIA Technologies, Inc.
    Inventor: Yang (Jeff) Jiao
  • Patent number: 8499140
    Abstract: A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 30, 2013
    Assignee: International Business Machines Corporation
    Inventors: Susan K. Lichtensteiger, Pascal A. Nsame, Sebastian T. Ventrone
  • Patent number: 8495652
    Abstract: When a process sleep event, a process wake-up event, a process save event, and a process resume event occur in an IT system having a multiprocessor configuration, a tracer respectively generates sleep event data, wake-up event data, save event data, and resume event data and records them as trace data in a trace buffer. The analysis unit generates an analysis result by referring to the trace data to accumulate a number of times of execution of the process wake-up process and a first time as a time from the process save event to the process wake-up event or to the process resume event with respect to a plurality of processes to be executed. When a contention for a shared resource occurs, the process wake-up process is repeatedly executed among relevant processes. For this reason, based on the analysis result, a possibility can be presented that the shared resource contention occurs in the IT system.
    Type: Grant
    Filed: December 25, 2008
    Date of Patent: July 23, 2013
    Assignee: NEC Corporation
    Inventor: Takashi Horikawa
  • Patent number: 8495650
    Abstract: A method for determining a number of threads to maximize system utilization. The method begins with determining a first value which corresponds to the current system utilization. Next the method determines a second value which corresponds to the current number of threads in the system. Next the method determines a third value which corresponds to the number of processor cores in the system. Next the method receives a fourth value from an end user which corresponds to the optimal system utilization the end user wishes to achieve. Next the method determines a fifth value which corresponds to the number of threads necessary to achieve the optimal system utilization value received from the end user. Finally, the method sends the fifth value to all running applications.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Stefan Raspl, Dirk Seider
  • Patent number: 8495637
    Abstract: Apparatus for data processing includes a processor, memory and storage. A plurality of sets of instructions, each corresponding to one of a plurality of programs, is stored in the storage. The processor is configured to load the sets of instructions from the storage into the memory, identify a first program as nonessential, close the first program and remove its corresponding set of instructions from the memory, and reload the set of instructions corresponding to the first program into the memory from the storage.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: July 23, 2013
    Assignee: Gzero Limited
    Inventor: Stavros George Alambritis
  • Patent number: 8495636
    Abstract: A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Michael A. Paolini, Michael Jay Shapiro
  • Patent number: 8495651
    Abstract: An information processing system periodically performs a real-time operation including a plurality of chained tasks. The system includes a plurality of processors, a unit for dividing the chained tasks into a first task group and a second task group based on a relationship in order of execution among the tasks, the second task group being executed after the first task group, and a unit for performing a scheduling operation of periodically assigning each of the first task group and the second task group to at least one of the processors to periodically execute the first task group at regular time intervals and periodically execute the second task group at the regular time intervals with a one-period delay relative to the first task group.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: July 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Hirokuni Yano, Kenichiro Yoshii
  • Patent number: 8490097
    Abstract: An information processing apparatus comprises a plurality of control units, a shared memory, a processing number table and a start-up time table. When a transaction is received, each of the control units determines whether the current time in the shared memory coincides with the most recent start-up time in the processing number. If the current time does not coincide with the most recent start-up time, each of the control units updates the most recent start-up time with current time and if or not, adds 1 to the number of transactions being processed in the processing number table so as to update the number of transactions being processed. After the number of transactions is updated, each of the control units sums up the number of transactions being processed in the processing number table. Each of the control units determines whether the number of transactions is not more than the threshold value in the shared memory.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: July 16, 2013
    Assignee: NEC Corporation
    Inventors: Kiyoshi Sano, Tetsuo Inoue
  • Patent number: 8490118
    Abstract: In a first thread of a process a determination is made that a current value at a target address is not a desired value. In response to this determination, a first application programming interface (API) is invoked to indicate that the first thread is to sleep and be woken up when a second thread modifies the value at the target address. When a second thread modifies the value at the target address, the second thread invokes a second API to indicate that the value at the target address has been modified. In response to the second API being invoked, the first thread is woken up.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: July 16, 2013
    Assignee: Microsoft Corporation
    Inventors: Gregory J. Colombo, Hari Pulapaka, Neill M. Clift
  • Publication number: 20130179896
    Abstract: An indication to process an Extensible Markup Language (XML) document that includes a hierarchy of nodes is received. A set of one or more page nodes to be processed is obtained, where the set of page nodes are part of the hierarchy of nodes. A plurality of threads is created. One of the set of page nodes and those nodes, if any, in the hierarchy that descend from that node are assigned to one of the plurality of threads to be processed by that thread. Processing, by said one of the plurality of threads, of the assigned page node and those nodes that descend from that page node is initiated.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 11, 2013
    Inventor: Alex Kalaidjian
  • Publication number: 20130174179
    Abstract: A multitasking method and apparatus of a user device is provided for intuitively and swiftly switching between background and foreground tasks running on the user device. The multitasking method includes receiving an interaction to request for task-switching in a state where an execution screen of a certain application is displayed, displaying a stack of tasks that are currently running, switching a task selected from the stack to a foreground task, and presenting an execution window of the foreground task.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 4, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Samsung Electronics Co., Ltd.
  • Patent number: 8479217
    Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 2, 2013
    Assignee: Intel Corporation
    Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
  • Patent number: 8468540
    Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: June 18, 2013
    Assignee: Bridge Crossing, LLC
    Inventors: Mario D. Nemirovsky, Adolfo M. Nemirovsky, Narendra Sankar
  • Patent number: 8468550
    Abstract: Mobile devices, systems and methods are described with a plurality of virtual machines, wherein each virtual machine executes a separate virtual interface, or guest operating system. Each guest operating system corresponds to a different virtual device having its own contact list, applications, and so on. A virtual “device” can be controlled by an employer or service provider, and is a secure space that provides authenticated applications that are walled off from another virtual device. A host operating system provides a hardware abstraction layer. A proxy server on the host operating system receives an incoming signal from a remote device on the external network, and routes the incoming signal to one of the first and second virtual machines based on a call context. A method and computer program product for providing a plurality of virtual interfaces on a mobile device are also disclosed.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: June 18, 2013
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Larry B. Pearson
  • Publication number: 20130152104
    Abstract: The present invention extends to methods, systems, and computer program products for handling synchronous operations by means of asynchronous operations. Upon completion of an asynchronous operation, a state flag is accessed. The state flag indicates whether or not a sync-over-async wrapper/adapter requested execution of the asynchronous operation. The sync-over-async wrapper/adapter is currently blocked awaiting notice of completion of the asynchronous operation. Based on the state flag, results of the asynchronous operation are stored at a location accessible by the sync-over-async wrapper. A completion signal is sent to the sync-over-async wrapper.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: Gregory Paperin, Eric L. Eilebrecht
  • Patent number: 8458706
    Abstract: A computer apparatus is provided for use with a database management system. The computer apparatus is instructed to carry out a first task and a second task in series on a section of data, by: (a) instructing the first task process to begin the first task on a first part of the section of data in the database, and (b) after the first task process on the first part of the section of the data is complete, instructing the first task process to carry out the second task on the first part of the section of data on which the first task has already been carried out, or carry out the first task on the second part of the data, or pipeline the second task to a third task process, or carry out the first task on a second part of the section of data.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: June 4, 2013
    Assignee: Neutrino Concepts Ltd.
    Inventor: Patrick Foody
  • Patent number: 8458721
    Abstract: The system and methods described herein may be used to implement a scalable, hierarchal, queue-based lock using flat combining. A thread executing on a processor core in a cluster of cores that share a memory may post a request to acquire a shared lock in a node of a publication list for the cluster using a non-atomic operation. A combiner thread may build an ordered (logical) local request queue that includes its own node and nodes of other threads (in the cluster) that include lock requests. The combiner thread may splice the local request queue into a (logical) global request queue for the shared lock as a sub-queue. A thread whose request has been posted in a node that has been combined into a local sub-queue and spliced into the global request queue may spin on a lock ownership indicator in its node until it is granted the shared lock.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: June 4, 2013
    Assignee: Oracle International Corporation
    Inventors: Virendra J. Marathe, Nir N. Shavit, David Dice
  • Patent number: 8458720
    Abstract: A system and method for choosing non-continual jobs to run in a stream-based distributed computer system includes determining a total amount of resources to be consumed by non-continual jobs. A priority threshold is determined above which jobs will be accepted, below which jobs will be rejected. Overall penalties are minimized relative to the priority threshold based on estimated completion times of the jobs. System constraints are applied to ensure that jobs meet set criteria such that a plurality of non-continual jobs are scheduled which consider the system constraints and minimize overall penalties using available resources.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Nikhil Bansal, Kirsten Weale Hildrum, Deepak Rajan, Joel Leonard Wolf
  • Patent number: 8458707
    Abstract: An approach that uses a handler to detect asynchronous lock line reservation lost events, and switching tasks based upon whether a condition is true or a mutex lock is acquired is presented. A synergistic processing unit (SPU) invokes a first thread and, during execution, the first thread requests external data that is shared with other threads or processors in the system. This shared data may be protected with a mutex lock or other shared memory synchronization constructs. When requested data is not available, the SPU switches to a second thread and monitors lock line reservation lost events in order to check when the data is available. When the data is available, the SPU switches back to the first thread and processes the first thread's request.
    Type: Grant
    Filed: March 15, 2008
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Maximino Aguilar, Jr., Michael Norman Day, Mark Richard Nutter
  • Patent number: 8458710
    Abstract: A technique includes determining an order for projects to be performed on a computer system. Each project is associated with multiple job sets, such that any of the job sets may be executed on the computer system to perform the project. The technique includes selecting the projects in a sequence according to the determined order to progressively build a schedule of jobs for execution on the computer system. For each selected project, incorporating one of the associated job sets into the schedule based on a cost of each of the associated job sets.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: June 4, 2013
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Kimberly Keeton, Manish Gupta
  • Patent number: 8453157
    Abstract: Provided are a method, system and article of manufacture, wherein a first application executes at least two threads corresponding to a simultaneous multi-threaded processor whose resources have been acquired by the first application. The at least two threads are synchronized before releasing the simultaneous multi-threaded processor to a second application.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Benhase, Yu-Cheng Hsu, John Norbert McCauley, Louis Alonso Rasor, William Griswold Sherman, Cheng-Chung Song
  • Patent number: 8452999
    Abstract: A method of processing data using a data processor having an operating system for performing tasks of an application program, and a power and performance controller controlling parameters and modes of execution of the tasks by the data processor. The power and performance controller includes a performance predictor producing an estimation of required performance of the data processor for the tasks taking account of inactive periods of the tasks and adjusting the performance and power consumption of the data processor in response to the estimation. The performance predictor distinguishes for each of the tasks between: —available inactive periods of the task during which the operating system is available to continue to process the same task, and—unavailable inactive periods of the task during which the operating system is not available to continue to process the same task. A substantial improvement is obtained in quality of service, with fewer missed deadlines in performance of the tasks.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: May 28, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Andy Barth, Daniele Dall'Acqua, Nigel Drew
  • Patent number: 8443363
    Abstract: A computer includes a plurality of activity modules in multiple virtual machines. An activity module performs an activity, such as malware detection, in a virtual machine. A monitoring module receives virtualized infrastructure information of the computer comprising a hardware configuration of the computer and a virtual machine configuration of the computer. A scheduling module determines, based on the virtualized infrastructure information, scheduling instructions for an activity module. A supervisor communication module causes the activity module to execute based on the scheduling instructions. The scheduling instructions minimize hardware resource conflicts between the activity module and the other activity modules of the computer.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: May 14, 2013
    Assignee: Symantec Corporation
    Inventors: James E. Brennan, III, James Waggoner
  • Patent number: 8438554
    Abstract: A system, method, and computer program product are provided for removing a synchronization statement. In use, synchronization statements are identified. Additionally, the synchronization statements are analyzed. Furthermore, the synchronization statements are removed based on the analysis.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: May 7, 2013
    Assignee: NVIDIA Corporation
    Inventors: Vinod Kumar Grover, John Stratton
  • Patent number: 8438512
    Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: May 7, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Cross, Eric Nequist
  • Patent number: 8438571
    Abstract: In an embodiment, asynchronous conflict events are received during a previous rollback period. Each of the asynchronous conflict events represent conflicts encountered by speculative execution of a first plurality of work units and may be received out-of-order. During a current rollback period, a first work unit is determined whose speculative execution raised one of the asynchronous conflict events, and the first work unit is older than all other of the first plurality of work units. A second plurality of work units are determined, whose ages are equal to or older than the first work unit, wherein each of the second plurality of work units are assigned to respective executing threads. Rollbacks of the second plurality of work units are performed. After the rollbacks of the second plurality of work units are performed, speculative executions of the second plurality of work units are initiated in age order, from oldest to youngest.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: May 7, 2013
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Gooding, John Kevin O'Brien, Kai-Ting Amy Wang, Xiaotong Zhuang
  • Publication number: 20130111497
    Abstract: In a method for minimizing occurrences of hanging escalations in a computer system, a computer determines that a number of escalations are scheduled for simultaneous execution in a time interval in a production environment. The computer divides the time interval by the number of escalations to form a shortened time interval. Moreover, the computer reschedules execution of the number of escalations in the production environment such that a plurality of subsets of the number of escalations execute in a staggered order according to the shortened time interval. A hanging escalation is an escalation that fails to complete, fails to process all data or records that the escalation was to process, or completes beyond an allotted processing time.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 2, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Danny Y. Chen, Fabian F. Morgan, Siddhartha Upadhyaya, Sarah V. White Eagle
  • Patent number: 8434092
    Abstract: Techniques for allocating computing resources to tasks include receiving first data and second data. The first data indicates a limit for unblocked execution by a processor of a set of at least one task that includes instructions for the processor. The second data indicates a maximum use of the processor by the set. It is determined whether a particular set of at least one task has exceeded the limit for unblocked execution based on the first data. If it is determined that the particular set has exceeded the limit, then execution of the particular set by the processor is blocked for a yield time interval based on the second data. These techniques can guarantee that no time-critical tasks of an embedded system on a specific-purpose device are starved for processor time by tasks of foreign applications also executed by the processor.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: April 30, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: James Miner, Billy Moon, Mickey Sartin
  • Patent number: 8434091
    Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing tasks is also provided. The processing system includes processing devices and an absolute timer. The absolute timer defines a time budget. The time budget provides a time period for the completion of tasks by selected processing devices independent of clock frequencies employed by the processing devices for processing the tasks.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: April 30, 2013
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Masakazu Suzuoki, Takeshi Yamazaki
  • Patent number: 8433830
    Abstract: Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.
    Type: Grant
    Filed: June 10, 2012
    Date of Patent: April 30, 2013
    Assignee: Calos Fund Limited Liability Company
    Inventors: Peter Mattson, David Goodwin
  • Publication number: 20130104144
    Abstract: A method for application switching in an operating system may be provided. The method may comprise providing at least two active applications on the operating system, and providing a first list of actions related to the first active application, via a first interface, to an application switching manager, and providing a second list of actions related to the second active application, via a second interface, to the application switching manager. Additionally, the method may further comprise selecting an active application out of the at least two active applications together with selecting an action selected from the first list of actions for a first application or a second action for the second list for a second application using a graphical user interface.
    Type: Application
    Filed: September 24, 2012
    Publication date: April 25, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: International Business Machines Corporation
  • Patent number: 8427702
    Abstract: According to an aspect of the disclosure, a printing system is provided comprising a plurality of resources including idle and non-idle resources having a at least one image marking engine. The plurality of resources includes a page parallel RIP system wherein the RIP system supports configurable sized print chunks. The RIP system adaptively adjusts the size of the chunks according to the busyness of receiving RIP nodes.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: April 23, 2013
    Assignee: Xerox Corporation
    Inventors: R. Victor Klassen, Peter A. Crean
  • Patent number: 8423681
    Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: April 16, 2013
    Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd., Hitachi Engineering & Services Co., Ltd.
    Inventors: Yusaku Otsuka, Naoya Mashiko, Shin Kokura, Yu Iwasaki, Ryuichi Murakawa, Akira Bando, Wataru Sasaki, Hideyuki Yoshikawa, Masamitsu Kobayashi
  • Patent number: 8423688
    Abstract: A configuration performing processing of dividing a file into a plurality of pieces and transmitting the same even when a size of the file is large in transfer of files (input/output) between computers on a network is provided. A multi-thread file input/output system includes a first module performing processing of reading data from an input file, dividing the data into a plurality of pieces, and transmitting the plurality of pieces to a network by multi-thread processing in a transmitter computer; and a second module performing processing of receiving the plurality of pieces from the network and integrating and writing the same to an output file 5 in a receiver computer.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 16, 2013
    Assignee: Hitachi Systems, Ltd.
    Inventor: Mineyuki Tamura
  • Patent number: 8424021
    Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: April 16, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Jack Kang, Yu-Chi Chuang
  • Patent number: 8418188
    Abstract: A slot calculation unit calculates a current slot number and stores it in a slot storage unit. When each of control tasks of a recognition processing portion, a vehicle speed calculation portion, a brake control portion, and a steering control portion is activated, a slot number at the time of output of an execution result used as input data is obtained from a task table storage unit, and it is determined whether a time constraint is violated based on a permissible slot number for the input data, stored in a constraint table storage unit. When an execution result of each control task is output, the stored current slot number is read, and it is determined whether a time constraint is violated based on a permissible slot number for the output of the execution result, stored in the constraint table storage unit.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: April 9, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Naoya Chujo, Masatoshi Kido
  • Patent number: 8418189
    Abstract: An approach for switching from one application to another, according to time information of a schedule item with respect to a current date and time and including converting data of the first application to data suitable for use in the other application, is provided. Such other application is chosen based on a comparison between the time information of the schedule item and the current date and time, and the data of the first application is automatically converted to data suitable for use in the other application and transferred to the other application.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: April 9, 2013
    Assignees: Ricoh Company, Ltd., Ricoh Americas Corporation
    Inventor: Hiroaki Ishizuka
  • Patent number: 8413163
    Abstract: Provided is a program control device which switches, per timeslot, between threads to be executed. The program control device includes: a first interrupt creation unit which creates a first interrupt signal which designates a timeslot as a destination; and a first receiving unit which [i] does not receive the first interrupt signal if the timeslot as the destination is not a current timeslot, and [ii] receives the first interrupt signal if the timeslot as the destination is the current timeslot.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: April 2, 2013
    Assignee: Panasonic Corporation
    Inventor: Kunihiko Hayashi
  • Publication number: 20130081033
    Abstract: Computationally implemented methods and systems include configuring a device to acquire one or more subtasks configured to be carried out by at least two discrete interface devices, said one or more subtasks corresponding to portions of one or more tasks of acquiring data requested by a task requestor, facilitating execution of the received one or more subtasks, and controlling access to at least one feature of the device unrelated to the execution of the one or more subtasks, based on successful execution of the one or more subtasks. In addition to the foregoing, other aspects are described in the claims, drawings, and text.
    Type: Application
    Filed: March 30, 2012
    Publication date: March 28, 2013
    Inventors: Royce A. Levien, Richard T. Lord, Robert W. Lord, Mark A. Malamud, John D. Rinaldo, JR.