Abstract: A small footprint device can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same namespace or memory space or to see that a requested action is authorized for an object to be operated upon. Each program or set of programs runs in a separate context. Access from one program to another program across the context barrier can be achieved under controlled circumstances by using a global data structure.

Abstract: Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated register file to be accessed by the corresponding processor thread. In an illustrative embodiment, the register file is divided into even and odd portions, with a least significant bit or other portion of the thread identifier being used to select either the even or the odd portion for use by a given processor thread. The thread-based register file selection may be utilized in conjunction with token triggered threading and instruction pipelining. Advantageously, the invention reduces register file port requirements and thus processor power consumption, while maintaining desired levels of concurrency.

Abstract: A task control block is implemented to provide more efficient user task access to task-specific variables and context information. The task control block uses multiple portions located in both protected system space and unprotected “user” space. Task-specific variables may be located in the user task control block, allowing user tasks to directly access these variables (without a system call). Sensitive task-specific state information may be located in the system task control block, preventing direct access by user tasks. The amount of time needed to perform context switching is reduced, and the execution time for user tasks may be reduced as well.

Abstract: A method for the direct call of a target function by a start function by means of a processor with a memory management unit (MMU) in a computer operated by an operating system. In today's multitasking operating systems, the call of a function of a first task by a second task is executed and managed by the task scheduler of the operating system. The time of the execution of the called function is uncertain and is dependent on the operating system as well as the tasks managed at every point in time by the operating system. One object of the invention is to disclose a method which enables a time-determined call of a function and which is executed immediately in connection with the call. This object is achieved in that the start function is a component of a first task with a first memory context and in that the first task performs a context switch from the first memory context into the other memory context and this memory switch is reversed after the execution of the target function.

Abstract: A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices. When application program threads require access to a PCI device, the operating system writes the high order bits of the PCI device address to two places: (1) the extension register of the PCI host bridge to allow immediate addressing of the PCI device, and (2) separate memory locations associated with the threads. When a context switch occurs from a first thread to a second thread, the operating system retrieves the stored value from the memory location associated with the second thread and writes the value to the extension register. In this manner, when the second thread requires access to its PCI device, the proper address value is already located in the extension register.

Abstract: Methods and apparatus for managing execution of an application according to an application lifecycle. The application lifecycle is managed by an application manager through a set of commands that enable the application manager to cause the application to enter one of a plurality of states. In addition, the application can communicate with the application manager to indicate that the application cannot change its state as the application manager has requested or to request that the application manager change the state of the application to a particular state.

Abstract: A processing system that executes multiple instruction contexts includes an instruction memory for storing instructions that are executed by the system, a processor unit executing the instructions in a pipelined fashion, a plurality of context registers for storing instructions and instruction addresses for contexts to be executed and fetch logic for selecting an address from one of the context registers and for selecting an instruction from a second of the context registers for execution substantially simultaneously for each cycle of execution of processor unit.

Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. A flow marker is inserted into an instruction stream, the instruction stream including the instruction information of the first thread dispatched from the instruction information source, and the flow marker indicating that the thread switching operation has occurred. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.

Abstract: A pipelined, simultaneous and redundantly threaded (“SRT”) processor comprising, among other components, load/store units configured to perform load and store operations to or from data locations such as a data cache and data registers and a cycle counter configured to keep a running count of processor clock cycles. The processor is configured to detect transient faults during program execution by executing instructions in at least two redundant copies of a program thread and wherein false errors caused by incorrectly replicating cycle count values in the redundant program threads are avoided by implementing a cycle count queue for storing the actual values fetched by read cycle count instructions in the first program thread. The load/store units then access the cycle count queue and not the cycle counter to fetch cycle count values in response to read cycle count instructions in the second program thread.

Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A flow marker within instruction information for the first thread received at the instruction information source is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the detection of the flow marker, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.

Abstract: Tasking systems and methods are provided that support user interfaces for displaying objects, the displayed objects enabling user access to resources that provide for effecting tasks among the system and devices of the systems' environment. More particularly, tasking systems and methods are provided that support the foregoing features, wherein the systems and methods support clustering operations respecting such task-associated objects so as to enhance the effecting of the associated tasks, such clustering operations responding to context. The clustering operations preferably are both adaptive and dynamic. Tasking systems and methods preferably support the tracking of selected states, including, as examples, one or more of environment states, device states, and system states. Tracked states typically also include states respecting other relevant criteria, such as temporal criteria.

Abstract: A system and method for multi-level memory domain protection. A user process for executing operating system code at a first protection level and user code at a second protection level. A domain process for executing the operating system code at the first protection level and domain code at the second protection level. The operating system code protecting the domain code, executing at the second protection level, from the user code, executing at the second protection level, by context switching between the user process context and the domain process context.

Abstract: A method for reducing cache memory misses in a computer that performs context switches between at least a first context and a second context. A First logic identifies a first prefetch region in a first memory element and a second logic identifies critical memory references within the first prefetch region during compilation of a computer program. The critical memory references within the first prefetch region correspond to data in cache memory if a context switch occurs from a process or thread associated with the second context to a process or thread associated with the first context during program execution. Third logic prefetches data associated with the identified critical memory references and stores the prefetched data in cache memory prior to a process or thread associated with the first context being resumed when a switch from the second context to the first context occurs during program execution.

Abstract: Techniques for token triggered multithreading in a multithreaded processor are disclosed. An instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled by associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions, and utilizing the stored value to control the instruction issuance sequence. For example, each of a plurality of hardware thread units of the multithreaded processor may include a corresponding local register updatable by that hardware thread unit, with the local register for a given one of the hardware thread units storing a value identifying the next thread to be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions. A global register arrangement may also or alternatively be used.

Abstract: An automatic context association system includes a context association schema for representing context associations between objects. The schema comprises a series of tables, including association tables with type-independent entries to support the association of objects of different types, and object tables that define the various objects. The schema supports the observation of user interaction with various system objects, including documents, photos, web pages, and interaction with other people, in order to find and utilize meaningful associations between them.

Abstract: A data processing system comprising a block move engine, a memory, a register and a reader. The block move engine may be configured to process data. The memory may be configured to store data in the form of a linked list comprising a plurality of items of control data. The register may be associated with the block move engine and configured to control the block move engine, in response to the control data. The reader may be configured to read the control data from the memory and apply the control data to the register.

Abstract: An operating system is provided that employs a nano-kernel and that reduces the number of times of revocation of a scheduler without impairing operation of a system incorporating the operating system. Each time a context switch occurs to switch from one to another thread, the operating system records the history of the context switch. When a scheduler that controls the sequence of execution of threads is invoked, a queue managed by the scheduler is updated tracking back the recorded history.

Abstract: A method, system and computer readable instructions for executing a file with a file format is provided. An attempt is made to execute the file with a first computer application within a plurality of computer applications. Responsive to the first computer application being unable to recognize the file format of the file, a second computer application within the plurality of computer applications is selected to execute the file. The file is then executed using the selected second computer application.

Abstract: Systems and methods for switching from a first Internet context to a second Internet context without process shutdown are described. Internet context data, such as cookies, history and user-defined data, is stored in containers unique to each user on a system. Internet content is stored in a common location so redundant downloaded information is not stored. Content information is found or stored by hashing a URL and indexing the memory location according to the resulting hash value. If content data is specific to a particular user, a hash is performed on a combination of the URL and an ordinal associated with the user's unique identity to obtain a hash value unique to the user. The user-specific content is then stored and the memory location is indexed according to the unique hash value.

Abstract: A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as an argument value or a static value. A second field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore static values and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor.

Abstract: A small footprint device, such as a smart card, can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same namespace or memory space or to see that a requested action is authorized for an object to be operated upon.

Abstract: A real-time operating system (RTOS) for use with minimal-memory controllers has a kernel for managing task execution, including context switching, a plurality of defined tasks, individual ones of the tasks having subroutines callable in nested levels for accomplishing tasks. In the RTOS context switching is constrained to occur only at task level, and cannot occur at any lower sub-routine level. This system can operate with a single call . . . return stack, saving memory requirement. The single stack can be implemented as either a general-purpose stack or as a hardware call . . . return stack. In other embodiments novel methods are taught for generating return addresses, and for using timing functions in a RTOS.

Abstract: In a computer system having a processor capable of operating at a plurality of performance states, including a first and a second performance state, wherein while the processor operates in any of the performance states it executes tasks at an expected processing performance, a system and method for dynamically adjusting to transitions between the first and second performance states. A determination is made that a performance state change is needed and a transition is initiated. The system halts task scheduling, measures CPU performance at the new performance state and resumes task scheduling within the constraints of the new performance state. The system also adjusts tasks as a function of CPU performance within the new performance state, wherein adjusting includes notifying each task of the transition between performance states.

Abstract: A system and method are disclosed for distributing events in a data processing system from an event generator to an event recipient, while retaining processing control at the event generator. A manager object is created to manage the event generator's event calls. In response to an event, a distributor object is created and assigned a new thread of execution. When multiple event recipients exist, a slave object is created for each recipient, with each slave assigned to a new thread of execution. The slave object distributes the event by calling an interface method that is created as part of the event generator.

Abstract: A multiprocessor computing machine is adapted to execute processes concurrently without interrupt to improve system throughput. The respective processors maintain local clocks initialized by a scheduler program to determine how long each process can execute without interrupt. Expiry of the local clock generates a hardware interrupt that switches out the process unless lock has been declared by the process. A process that is enabled to declare lock may continue to process for a predetermined period of time. A timer queue is also managed without interrupt. System resources are thereby conserved and throughput is improved.

Abstract: Method and a device are disclosed for a fast performance of network operations via a network with high delay times by means of a module for processing system calls of an application layer and for initiating network operations of a network layer. In the module a differentiation between a blocking and non-blocking implementation mode is made. A non-blocking execution mode means that the considered system call returns a logical value as a result to the application, which signals whether the system call was successfully executed. In this case it is provided by the method and device to directly send a logical value to the application when a non-blocking system call is called, without having waited for the actual result of the operation executed in the communicating partner instance and corresponding to the system call. The handling of the results of the actually executed operations takes place at a later time.

Abstract: A method and system in a computer within a computer network for automatically swapping application tasks running within the computer when access from the computer to a remote network site is delayed. Initially, a link from a local network site to a remote network site utilizing a communications application while multi-tasking applications are simultaneously running at the local network site is initiated. Data retrieval from the remote network site is then initiated in response to initiating the link. Focus is then automatically switched from the communications application to a multi-tasking application simultaneously running at the local network site, in response to initiation of the data retrieval. After retrieval of the data has been completed, user notification of such completion is automatically provided. In one embodiment, that notification is provided by automatically switching focus back to the communications program.

Abstract: The present invention provides providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems. In one embodiment, a scheduler accesses an activity scheduling graph. The activity scheduling graph is comprised of nodes each representing a recurring execution interval, and has one root, one or more leaves, and at least one path from the root to each leaf. Each node is on at least one path from the root to a leaf, and the number of times the execution interval represented by each node occurs during the traversal of the graph is equal to the number of paths from the root to a leaf that the node is on. Each node has associated with it an execution interval length, and is adapted to being dedicated to executing the threads of a single activity. There may be one scheduling graph for each processor, or a scheduling graph may traverse multiple processors.

Abstract: Methods and arrangements are provided for use in multiple user computing environments. These methods and arrangements can be configured to allow for a plurality of separate and concurrent desktops and workspaces within the shared computing environment. One method includes creating a separate desktop thread for each user that is authenticated during a logon process, creating a separate desktop associated with each desktop thread, and maintaining a list of desktop threads that are created. In this manner, several users can be logged on simultaneously. In certain implementations, the method further includes establishing a separate user environment associated with each desktop and launching a separate user shell associated with each desktop. The list of desktop threads allows for selective and/or automatic switching from a first desktop to a second desktop without terminating a desktop thread associated with the first desktop. The methods and arrangements are also applicable to remote process logon and switching.

Abstract: A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i.e., for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.

Abstract: An apparatus for measuring a CPU occupancy rate of a task in a real-time system. The apparatus includes a task register unit registering a task to be measured in flag bits, and a task selecting module selecting and outputting a bit address of the task having a high priority of the flag bit among the set flag bits. A count signal generating unit processing the bit address inputted from the task selecting module to generate a count signal, and a count unit counting an execution time of the task in accordance with the count signal are further included. A CPU sets the flag bit when the task is executed and calculates an execution number and the CPU occupancy rate of the task based on a count value of the count unit.

Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. An absence of a flow of instruction information of the first thread into the instruction information source from an upstream source in a processor pipeline is detected. The elapsing of a predetermined time interval subsequent to the detection of the absence of the flow of the instruction information is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer.

Abstract: A method of handling conflicts between threads, including an initiating thread and at least one other thread, for at least one shared resource in a multi-threaded processing system having a processor and memory includes setting a location in memory for each other thread on the processor with the initiating thread. The initiating thread signals an inter-processor interrupt (IPI) to all other threads on the processor. For each other thread, an interrupt handler is initiated where each other thread: acknowledges receipt of the interrupt, and proceeds to spin on the respective location in memory that was set, thereby guaranteeing that the respective other thread will not be using any shared resource of the processor.

Abstract: A system and a method of scheduling a plurality of threads from a multi-threaded program. A shared arena is provided in user memory, wherein the shared arena includes a register save area for each of the plurality of threads. A processor, when allocated to the application, executes the application's user-level scheduler and selects a user-level thread from a plurality of available threads, wherein the step of selecting includes the step of reading register context associated with the selected thread from one of the plurality of register save areas. In multikernel systems, kernels having access to an application's register save areas can execute preempted threads from that application with no kernel-to-kernel communication. Likewise, kernels having access to an application's user-level run queues can execute ready-to-run threads from that application with no kernel-to-kernel communication.

Abstract: A MODEM 1 has a one-chip single DSP 2, and the single DSP 2 executes a controller task (CT) and a data-pump task (DP). In the CT, a plurality of sub-tasks are continuously executed in the round robin mode in the CT task processing part 3. During the execution of the CT task, when the DP task is required to be started by an interrupt generated by an external event, the parameters for restarting the CT task that is being executed are stored in the task switching part 5, and then the task is switched from the CT task to the DP task according to the parameters for restarting the data-pump task, which are previously stored. Then, after the process of the switched DP task is finished, the parameters for restarting the DP task are stored and the task is, switched from the DP task to the CT task according to the parameters for restarting the CT task.

Abstract: Methods and systems are provided to control transitions between a virtual machine (VM) and Virtual Machine Monitor (VMM). A processor uses state action indicators to load and/or store associated elements of machine state before completing the transition. The state action indicators may be stored in a Virtual Machine Control Structure (VMCS), predetermined, and/or calculated dynamically. In some embodiments, the values loaded can be directly acquired from the VMCS, predetermined and/or calculated dynamically. In some embodiments, the values stored may be acquired directly from machine state, predetermined and/or calculated dynamically.

Abstract: Methods, apparatus and program products for using historical contextual data in a ubiquitous computing environment. The historical contextual data can be dispersed among components in an environment or logging services as well as stored on a particular component or logging service. The historical contextual data can be used to help create or re-create component configurations within the relevant environment through the use of abstract applications and abstract components. Abstract applications can be specified to create connections with specific components. Abstract applications can also be generalized so that they need not create connections with specific components, but can create component connections that perform a desired function by determining which components to use from the available components, and how to connect the selected components to perform the function.

Abstract: Disclosed is context swapping in a multitasking operating system for a processor that includes providing a plurality of context blocks for storing context information for a plurality of processes, providing an array of pointers to the context blocks, providing an index to the array of pointers, and swapping context by adjusting at least one pointer in the array of pointers to point to a context block of a new process. Further included may be incrementing the index prior to adjusting the at least one pointer in the array of pointers. Further included may be, after adjusting at least one pointer in the array of pointers, decrementing the index and causing the processor to jump to an address indicated by a program counter value of the new process. The context information may include values for registers, a stack pointer, and a program counter for a process.

Abstract: The source code of a migration able program is precompiled to insert possible migration points, and collection, transfer, and restoration macros associated with the possible migration points, with the functions analyzed or mapped in order that the function sequence of the actually migrating process, i.e., the execution state, can be collected from its most recent, or inner-most, function to its main, or outer-most function, and transferred and restored in the same order to the destination computer. The collection, transfer and restoration can be carried out concurrently for optimal performance. The memory state necessary to accomplish the functions of the migrated process is mapped and reconstructed in the destination computer so as to be collected, transferred and restored in the same order as the execution state sequence. The collection, transfer and restoration processes can be carried out concurrently for greater migration efficiency.

Abstract: A task stack and a context pointer in a task control block (TCB) are implemented to provide more efficient context switching. Additionally, multiple routines each of which saves or restores a certain combination of volatile registers is implemented. A task can store in its task control block a routine identifier to select from the multiple routines a set of routines for saving and restoring volatile registers during context switching. On the occurrence of an event that may lead to a context switch a scheduler selects based on the routine identifier a routine that only saves registers used by the task, thereby, reducing execution overhead. The registers are saved on the task stack and a context pointer to the registers is saved in the TCB. In the event a context switch is necessary, it is not necessary to copy the registers to the TCB because the context pointer is in the TCB. A non-volatile register indicator that indicates whether non-volatile registers are used is stored in the task control block.

Abstract: A computer instruction includes a declaration instruction that results in a variable name being associated with a memory location in one of a plurality of memories, the declaration instruction having a first field to specify the variable name, a second field to specify a one of the plurality of memory systems to associate with the variable name.