Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.

Abstract: Systems and methods for scheduling program units that are part of a process executed within an operating system are disclosed. Additionally, at least one thread is started within the operating system, the thread is associated with the process. Further, a plurality of streams within the thread are selected for execution on a multiple processor unit. Upon the occurrence of a context shifting event, one of the streams enters a kernel mode. If the first stream to enter kernel mode must block, then the execution of the other streams of the plurality of streams is also blocked.

Abstract: A background memory manager (BMM) for managing a memory in a data processing system has circuitry for transferring data to and from an outside device and to and from a memory, a memory state map associated with the memory, and a communication link to a processor. The BMM manages the memory, determining if each data structure fits into the memory, deciding exactly where to place the data structure in memory, performing all data transfers between the outside device and the memory, and maintaining the memory state map according to memory transactions made, and informing the processor of new data and its location. In preferred embodiments the BMM, in the process of storing data structures into the memory, provides an identifier for each structure to the processor. The system is particularly applicable to Internet packet processing in packet routers.

Abstract: An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed by OS1, a second area storing a reset handler containing instructions for returning to OS2 and for branching to OS2, and a switching unit that switches connection/disconnection of the first area with outside; a table storing unit storing information showing the reset handler's position; a CPU having a program counter and executing an instruction at a position indicated by positional information in the program counter; and a management unit that, when instructed to switch from OS1 to OS2 while the apparatus is operating with OS1, instructs the switching unit to disconnect the first area and the CPU to reset. When instructed to reset itself, the CPU initializes its state and sets the reset handler positional information into the program counter.

Abstract: Method for selecting a virtualization algorithm to virtualize a context change. An exit-enter time (EET) to exit and enter a context and a save-restore time (SRT) to save and restore a machine state are calculated. A selective algorithm that selectively saves and restores the machine state when there is a change of context is executed. Statistics are accumulated on an expected value for EET overhead plus an expected value for SRT overhead while executing the selective algorithm. A cost of the selective algorithm is computed as the expected value for EET overhead plus the expected value for SRT overhead. The cost of the selective algorithm is compared to two times SRT which is the cost of an unconditional algorithm that always saves and restores the machine state on context changes. One of the selective algorithm or the unconditional algorithm having the least cost is selected as the virtualization algorithm.

Abstract: A processing block is equipped with a storage to facilitate storage and maintenance of a thread switching structure to provide multi-threading support in a light-weight manner. In various embodiments, the structure includes a current thread identifier, and a thread array of thread entries describing the threads to be executed interleavingly. Further, in various embodiments, the processing block includes an execution sub-block and a thread management sub-block equipped to support at least a create thread, a thread execution termination, and a thread execution switching instruction.

Abstract: Multi-threaded processing with reduced context switching is disclosed. Context switches may be avoided through the use of pre-emption notification, a pre-emption wait time attribute and a no-context-save yield.

Abstract: An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.

Abstract: Described is a protocol controller that supports calls to a packet subroutine which includes a packet processing engine programmed to retrieve packets from a packet memory and to interpret the packets, a working chain pointer module of the packet processing engine programmed to generate a packet memory address for each packet and a return address register of the working chain pointer module, adapted to store a return packet address. Upon processing a call packet, the packet processor engine instructs the working chain pointer module to save a next packet address of a normal packet flow in the return address register, and instructs the working chain pointer module to generate the packet address to execute the packet routine.

Abstract: An apparatus and a method dynamically reassign resources in a coprocessor among master processors that require service from the coprocessor. The method includes each processor, in each processor cycle, keeping track of a number of resource units required for executing operations sent to the coprocessor in that processor cycle and receiving from the coprocessor a number of resource units released during the processor cycle. When the resources need to be reassigned, the coprocessor asserts a signal to the resource yielding processor to cause it to reduce its expectation of resources to zero and ceasing sending service requests to the coprocessor. The coprocessor then moves resources from the yielding processor to the resource receiving processor. Resources are then released to both processors over time to their respective adjusted resource allocations. Such resources may be the number of operations that is allowed to be executing in the coprocessor simulataneously.

Abstract: An embodiment of the invention provides an apparatus and a method for direct switching of software threads. The apparatus and method include performing acts including: issuing a wakeup call from a first thread to a second thread in a sleep state; removing the second thread from the sleep state; switching out the first thread from the resource; switching in the second thread to the resource; and running the second thread on the resource.

Abstract: A system and method for intelligent, context-sensitive enhancement of transactions among a plurality of mobile hosts, each having a local coordinator, engaging in services comprising an actual coordinator and an intelligence coordinator that determines context regarding the mobile hosts, and leverages the context to enhance the transactions between the local coordinators and the actual coordinator. The context can be leveraged by reducing the number and/or the amount of data of the transactions. The context can comprise a physical location, temporal data, and a network load near and at a network location of the mobile host. The system can also have an application operating on the services, in which the intelligence coordinator can improve performance of the application. The intelligence coordinator can receive and parse a meta-expression piggy-backed on a transaction message to enhance transactions.

Abstract: Provided is a method, system, deployment and program for resource allocation unit queuing in which an allocation unit associated with a task is classified. An allocation unit freed as the task ends is queued for use by another task in a queue at a selected location within the queue in accordance with the classification of said allocation unit. In one embodiment, an allocation unit is queued at a first end of the queue if classified in a first class and is queued at a second end of the queue if classified in said second class. Other embodiments are described and claimed.

Abstract: Methods and/or systems and/or apparatus for improved security in information processing systems provide secure control transfer and object-oriented programming support at an architectural level using hardware readable data structures that represent different object structures in order to securely switch context. An architectural level Object-Oriented Programming (OOP) processor allows OOP software to be directly mapped into hardware and object security can be enforced not only in software, but also in hardware. The processor performs security checks for objects and eliminates most of the software work for access checking. In some embodiments, a hardware or hardware-like (e.g., firmware) device is used for communication and access control, to compute instructions, with a mapping mechanism of access control for object-oriented computing, through operand descriptor tables to describe the access control based on the object-orientation requirements, such as private, public, package, or protected, etc.

Abstract: A method of processing network data in a network processor includes assigning a group of receive threads to process network data from a port. Each of the group of receive threads process network data in a round-robin fashion.

Abstract: A small footprint device, such as a smart card, can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same namespace or memory space and to see that a requested action is appropriate for an object to be operated upon.

Abstract: A virtual machine application interrupts execution of a host OS under software control at a predetermined interruption point, instead of interrupting the execution at an arbitrary instruction. The context of the host OS is saved by using an inconsequential register as temporary storage. Context of the host OS is restored by using an inconsequential register as temporary storage.

Abstract: Various technologies and techniques are disclosed for preserving input element ordering in data parallel operations. This ordering may be based on element ordinal position in the input or a programmer-specified key-selection routine that generates sortable keys for each input element. Complex data parallel operations are re-written to contain individual data parallel operations that introduce partitioning and merging. Each partition is then processed independently in parallel. The system ensures that downstream operations remember ordering information established by certain other operations, using techniques that vary depending upon which categories the consumer operations are in. Data is merged back into one output stream using a final merge process that is aware of the ordering established among data elements.

Abstract: Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a maskable or non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a maskable non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread. In addition, the disclosed methods and computer-executable components also: (a) allow scheduling of CPU resources such that real-time threads are guaranteed respective portions of time slots, (b) enable real-time scheduling on a non-real-time operating system, and (c) provide scheduling of CPU resources on a uni-processor machine such that at least first and second real-time threads dependent on one another are synchronized.

Abstract: In various embodiments, a context or location service module, implemented in software, determines a vehicle context or a vehicle location based upon information that it receives from various context providers or location providers respectively. Software executing on a vehicle's computer can then cause one or more applications that are associated with a vehicle computer to be modified in a manner that changes their behavior.

Abstract: A multiprocessor computer system has nodes which use processor state information to determine which coherent caches are required to examine a coherency transaction produced by a single originating processor's storage request. A node has dynamic coherency boundaries such that the hardware uses only a subset of the total processors for a single workload at any specific point in time and can optimize cache coherency as the supervisor software or firmware expands and contracts the number of processors used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a larger multiprocessor system. The node controllers use the mode bits to determine which nodes must receive any given transaction. Logical partitions are mapped to allowable physical processors. Cache coherence regions and caches are chosen for their physical proximity. A distinct cache coherency region can be hypervisor defined for each partition.

Abstract: For an information system to be analyzed, restriction information indicating a restriction to be satisfied in the case where the information system is normal is acquired, and an anomalous state failing to satisfy the restriction is specified in a state transition model involving only the automatic transition. Also, the transition from an anomalous state to a normal state is retrieved in the state transition model involving only the manual transition thereby to output management work information indicating a management work specified by the retrieved manual transition as related to the anomalous state.

Abstract: In one embodiment, the present invention includes a method for receiving a signal in a filter register of a performance monitor from an execution unit to enable a field of the filter register associated with a first thread when a filter enable instruction is executed during execution of code of the first thread, receiving a thread identifier and event information in the performance monitor from the execution unit, and determining if the thread that corresponds to the received thread identifier is enabled in the filter register and if so, storing the event information in a first counter of the performance monitor. Other embodiments are described and claimed.

Abstract: An end user computer includes a processor running an operating system. A plurality of virtual private servers (VPSs) are supported within the operating system. A plurality of applications are available to a user of the end user computer. The applications are launched within different VPSs. At least one of the VPSs has multiple applications launched within it. At least two of the applications are launched within different VPSs, and communicate with each other using secure communications means, such as firewalls, proxies, dedicated clipboards, named pipes, shared memory, dedicated inter-process communications, Local Procedure Calls/Remote Procedure Calls, API, network sockets, TCP/IP communications, network protocol communications and memory mapped files. The VPSs can be dynamically created and terminated.

Abstract: A method, apparatus and system are described for seamlessly sharing I/O devices amongst multiple virtual machines (“VMs”) on a host computer. Specifically, according to one embodiment of the invention, the virtual machine manager (“VMM”) on the host cycles access to the I/O devices amongst the VMs according to a round robin or other such allocation scheme. In order to provide direct access to the devices, the VMM may save the device state pertaining to the currently active VM, store the state in a memory region allocated to the currently active VM, retrieve a device state for a new VM from its memory region and restore the device using the retrieved device state, thus providing the illusion that each VM has direct, full-speed, exclusive access to the I/O device.

Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Abstract: Testing multithreaded application programs for errors can be carried out in an efficient and productive manner at least in part by prioritizing thread schedules based on numbers of context switches between threads therein. In particular, each thread schedule in a multithreaded application program can be prioritized based on whether a given thread schedule has the same as or less than some maximum value. A model checker module can then iteratively execute thread schedules that fit within a given context switch maximum value, or a progressively higher value up to some limit. In one implementation, for example, the model checker module executes all thread schedules that have zero preempting context switches, then all thread schedules that have only one preempting context switch, etc. Most errors in an application program can be identified by executing only those thread schedule with relatively few preempting context switches.

Abstract: An embodiment of the invention provides an apparatus and method for accurate measurement of utilizations in a hardware multithreaded processor core. The apparatus and method perform the acts including: determining idle time spent cycles which are cycles that are spent in idle by a hardware thread in a processor core; determining idle consumed cycles which are cycles that are consumed in the idle time spent cycles, by the hardware thread; and determining at least one of a processor core utilization and a logical processor utilization based upon at least one of the idle time spent cycles (d1) and idle consumed cycles (d3).

Abstract: A method and a system are described that involve processing a request in multiple threads and dispatching the request to a set of applications. The method includes receiving the request, wherein the request contains application context and session data, creating a request context object and associating it with the application context and the session data, storing an identifier of a first thread that processes the request in the request context object associated with the thread, creating a set of threads from the first thread to process the request in parallel threads, each thread in the set having a unique identifier and inheriting the request context object from the first thread, and invoking a request dispatcher on each thread in the set to forward the request to the set of applications.

Abstract: A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.

Abstract: A method for storing state information, the method includes storing, at a first circuit, state information representative of a state of a second circuit while the second circuit enters a low power mode; characterized by receiving an indication that a task switching from a first task to a second task should occur; storing a state information representative of a state of the second circuit, at the first circuit; receiving an indication that the first task should be resumed; and writing the stored state information from the first circuit to the second circuit. A system includes a first circuit and a second circuit, whereas the first circuit is connected to the second circuit and is adapted to store state information representative of a state of a second circuit; characterized by including a controller adapted to control a storage of the state information if at least a portion of the second circuit is powered down or if the second circuit is associated with a task switching operation.

Abstract: Multiple different operating systems are enabled to run concurrently on the same computer. A first operating system is selected to have a relatively high priority (the realtime operating system, such as C5). At least one secondary operating system is selected to have a relatively lower priority (the general purpose operating system, such as Linux). A common program (a hardware resource dispatcher similar to a nanokernel) is arranged to switch between these operating systems under predetermined conditions and modifications are provided to the first and second operating systems to allow them to be controlled by the common program.

Abstract: A task switch from a first data processing task to a second data processing task can be accomplished by the first task calling a function which saves the first task's context, restores the second task's context and then returns. Because the second task's context has been restored, the called function actually returns to the second task, thereby completing the task switch.

Abstract: The present invention provides a system and method, operable in a multi-context processor, for allowing a current context to change an event sensitivity of a future context. In one embodiment, the system includes a context control register, accessible to the current context, for receiving event mask data defining the event sensitivity of the future context. The system further includes a context controller, associated with the context control register and invokable from within the current context, that causes the event mask data to be employed in defining a content of an event mask register of the future context.

Abstract: A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.

Abstract: One embodiment of the present invention provides a method and a system for tracking memory usage of tasks in a shared heap. The system performs a full garbage-collection operation on the shared heap, during which a base memory usage is determined for each task. The system then periodically samples task state during execution to generate an estimate of newly allocated memory for each task. The base memory usage and the estimate of newly allocated memory for each task are combined to produce an estimate of current memory usage for each task. This estimate of current memory usage is used to determine whether a task is likely to be violating a memory quota. If so, the system triggers a remedial action, which can include: a full garbage-collection operation; a generational garbage-collection operation; or generation of a signal which indicates that a memory quota violation has occurred.

Abstract: A method for sharing a buffer among multiple context engines, is provided. The method includes loading a memory element with a first data sequence. The method further includes loading a corresponding first context information to one of the multiple context engines. Subsequently, a direct memory access engine is loaded with the first data sequence dictated by the first context information. Then, the first data sequence is processed. While the first data sequence is being processed, the method includes loading the context engine with a next context information for a next data sequence contemporaneously with the processing of the first data sequence.

Abstract: Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.

Abstract: An embodiment of the present invention enables the virtualizing of virtual memory in a virtual machine environment within a virtual machine monitor (VMM). Memory required for direct memory access (DMA) for device drivers, for example, is pinned by the VMM and prevented from being swapped out. The VMM may dynamically allocated memory resources to various virtual machines running in the platform. Other embodiments may be described and claimed.

Abstract: Methods and systems for parallel computation of an algorithm using a plurality of nodes configured as a Howard Cascade. A home node of a Howard Cascade receives a request from a host system to compute an algorithm identified in the request. The request is distributed to processing nodes of the Howard Cascade in a time sequence order in a manner to minimize the time to so expand the Howard Cascade. The participating nodes then perform the designated portion of the algorithm in parallel. Partial results from each node are agglomerated upstream to higher nodes of the structure and then returned to the host system. The nodes each include a library of stored algorithms accompanied by data template information defining partitioning of the data used in the algorithm among the number of participating nodes.

Abstract: A monitor method of computer system is provided, applying within an interrupt service routine. According to the application of interrupt service, when the interrupt controller sends an interrupt signal to the CPU, the CPU executes a corresponding interrupt service routine based on the interrupt signal, in the meantime, the daemon program generates an entrant code. Before the interrupt service routine stops, the daemon program generates an exit code and saves both the entrant code and the exit code in a storage device. It is benefit for solving the problems occurred in the debugging process according to the entrant code and the exit code of the storage device, and speeding up the process of testing and researching steps.

Abstract: A parallel process execution method that allocates CPU time to parallel processes at any desired ratios. The method sets a time allocation ratio to determine how much of a given cycle period should be allocated for execution of a parallel program. Process switching is then performed in accordance with the time allocation ratio set to the parallel program. More specifically, parallel processes produced from a parallel program are each assigned to a plurality of processors, and those parallel processes are started simultaneously on the processors. When the time elapsed since the start of the parallel processes has reached a point that corresponds to the time allocation ratio that has been set to the parallel program, the execution of the assigned parallel processes is stopped simultaneously on the plurality of processors.

Abstract: A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed within one bus cycle and a plurality of hardware contexts are provided. The deterministic microcontroller includes a configurable input/output interface that is programmable to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Abstract: Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of instructions. The instructions are compiled as instruction words of given length executable on a first processor. At least some of the instruction words of given length are converted into modified-instruction words executable on a second processor. The operation of modifying comprises in turn at least one operation chosen in the group consisting of: splitting the instruction words into modified-instruction words; and entering no-operation instructions in the modified-instruction words.

Abstract: Disclosed are a method, information processing system, and computer readable medium for resource recovery. The method comprises associating at least one bit with at least one block of memory. The bit denotes a borrow status for the block of memory. The bit is set for resource recovery. A resource recovery event is detected and in response to the bit being enabled for resource recovery, the block of memory is borrowed for a given duration of time. The bit is borrowed to temporarily store information associated with the resource recovery there into until the information is written to persistent storage.

Abstract: A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.

Abstract: A real time operating system (RTOS) for a vehicle electronic control unit (ECU) switches the CPU of the vehicle ECU to a low-power-consumption (LPC) mode, if there is no task in a running state and no task in a ready state and the time left before a task in a suspended state is switched to the ready state is longer than a predetermined allowable minimum duration of the LPC mode. Duration of the LPC mode is set to a length shorter than the time left before a task in the suspended state is switched to the ready state. When an interrupt occurs or the duration of the LPC mode expires, the CPU is switched to a normal mode and temporary suspension of the system clock during the LPC mode is compensated for using the duration of the LPC mode.

Abstract: A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries.

Abstract: A method for managing a mutex in a data processing system is presented. For each mutex, an average acquisition cost is maintained that indicates an average consumption of computational resources that has been incurred by threads attempting to acquire the mutex. If a thread attempts to acquire a locked mutex, then the thread enters a spin state or a sleep state based on restrictive conditions and the average acquisition cost value for the mutex at that time. A thread-specific current acquisition cost value is maintained that represents the consumption of computational resources by the thread after the initial attempt to acquire the mutex and prior to acquiring the mutex. When the thread acquires the mutex, the thread-specific current acquisition cost value is included into the average acquisition cost value.

Abstract: In an electronic unit having a stack in memory and adapted to run a plurality of tasks in accordance with a multitask operating system and to save context data in the stack, a scheduling unit schedules the plurality of tasks for wakeup so as to execute the plurality of tasks. Each of the plurality of tasks stays in at least one of a suspended state, a ready state, and a running state. A measurement unit measures an amount of space to be used in the stack during the at least one of the tasks staying in neither the running state nor the ready state.