Abstract: Methods, apparatus, and products are disclosed for thread selection during context switching on a plurality of compute nodes that includes: executing, by a compute node, an application using a plurality of threads of execution, including executing one or more of the threads of execution; selecting, by the compute node from a plurality of available threads of execution for the application, a next thread of execution in dependence upon power characteristics for each of the available threads; determining, by the compute node, whether criteria for a thread context switch are satisfied; and performing, by the compute node, the thread context switch if the criteria for a thread context switch are satisfied, including executing the next thread of execution.

Abstract: A virtual multithreading hardware mechanism provides multi-threading on a single-threaded processor. Thread switches are triggered by user-defined triggers. Synchronous triggers may be defined in the form of special trigger instructions. Asynchronous triggers may be defined via special marking instructions that identify an asynchronous trigger condition. The asynchronous trigger condition may be based on a plurality of atomic processor events. Minimal context information, such as only an instruction pointer address, is maintained by the hardware upon a thread switch. In contrast to traditional simultaneous multithreading schemes, the virtual multithreading hardware provides thread switches that are transparent to an operating system and that may be performed without operating system intervention.

Abstract: There is provided a method of interrupt scheduling. The method comprises: without allowing a target process woken up when an interrupt occurs to enter into a ready queue, directly comparing the priority of the woken-up target process with that of a current process performed before the occurrence of the interrupt, and executing a rescheduling in accordance with the compared result; and performing direct context switching with respect to the current process into the target process in accordance with whether or not the rescheduling is executed. Accordingly, in the method of interrupt scheduling, the preemption latency caused by the interrupt in the operating system of the computer system can be minimized by omitting the process of allowing the woken-up target process to enter into the ready queue and the process of selecting a process with the highest priority on the ready queue.

Abstract: An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of at least one instruction likely to be executed by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, one or more instructions may be prefetched on behalf of that thread so that when execution of the thread is resumed, those instructions are more likely to be cached, or at least in the process of being retrieved into cache memory, thus enabling a thread to begin executing instructions more quickly than if the thread was required to fetch those instructions upon resumption of its execution.

Abstract: Embodiments of the present invention provide for collecting a minimal subset of task execution context in real time and for restoring the task execution context and performing procedure frame unwinding operations at a post-processing stage. A first data structure may be constructed in real time to contain procedure linkage information along with references to the memory area or to a processor register context where each procedure linkage information element (procedure return address or a procedure frame pointer) was originally found. Procedure return addresses may be determined by decoding the instruction preceding the address in question and checking if it is a procedure call instruction. Procedure return addresses may also be determined using other methods (e.g., by checking whether the memory region the address in question belongs to is executable) if the probability of retrieving the correct result is acceptable for a particular area of application of an embodiment of the present invention.

Abstract: This present invention is a divided disk command processing system and method thereof, for processing a disk command by executing the multiple computing processes of the disk command separately in multiple processing stages, to reduce frequently storing and restoring the state as context switching of a CPU. And the processing capability of the CPU in each stage is adequately employed to speed up a disk command processing.

Abstract: A microprocessor includes a first information holding unit, a second information holding unit, and a switching authorization unit. The first information holding unit holds process identification information and authentication information which are associated with each other. The second information holding unit denies access from outside, and holds entry information of a process and the authentication information which are associated with each other. The switching authorization unit allows switching process when the authentication information held in the first information holding unit with the authentication information held in the second information holding unit match.

Abstract: An apparatus for managing resource in a multithreaded system, and attempting to increase the speed in which task switching occurs by controlling when thread state is stored to memory. The apparatus includes a thread dispatcher circuit capable of determining, based upon an estimated state retirement rate associated with the worker threads and a rate of saving state of the worker threads, if the worker threads should be halted and saved the state of the worker threads.

Abstract: An operating system permits sharing of a sub-process (or process unit) across multiple processes (or tasks). Each shared sub-process has its own context. The sharing is enabled by tracking when a process invokes a sub-process. When a process invokes a sub-process, the process is designated as a parent process of the child sub-process. The invoked sub-process may require use of process level variable data. To enable storage of the process level variable data for each calling process, the variable data is stored in memory using a base address and a fixed offset. Although the based address may vary from process to process, the fixed offset remains the same across processes.

Abstract: A multi-context register file for use in a multi-threaded processor includes at least one multi-context register file cell having internal routing functionality.

Abstract: Provided is the information communication processing device capable of executing terminal function switching control in linkage with an external communication content on one information communication processing device based on the external communication content without a problem in switching. The information communication processing device has at least one information processing device having a plurality of function environments for executing an application, and a switching control unit for switching a function environment, in which the switching control unit determines a function environment to be switched based on contents of communication with the outside of the information communication processing device and sets context of the function environment to be switched at context of a function environment being executed, thereby executing switching to the function environment to be switched.

Abstract: An apparatus, a method, and a computer program are provided for an architected register file system for multithread system. In conventional architected register file systems, a thread is only capable of utilizing a single register file. However, when register files of other thread are unused, the system resources are wasted. In the modified architected register file system, though, threads are enabled to utilize register files of other threads. The utilization of other thread registers is through the use of control fields added to a Status and Control Register (SCR) associated with each register file that enable and disable usage of other register files.

Abstract: Adaptive modifications of spinning and blocking behavior in spin-then-block mutual exclusion include limiting spinning time to no more than the duration of a context switch. Also, the frequency of spinning versus blocking is limited to a desired amount based on the success rate of recent spin attempts. As an alternative, spinning is bypassed if spinning is unlikely to be successful because the owner is not progressing toward releasing the shared resource, as might occur if the owner is blocked or spinning itself. In another aspect, the duration of spinning is generally limited, but longer spinning is permitted if no other threads are ready to utilize the processor. In another aspect, if the owner of a shared resource is ready to be executed, a thread attempting to acquire ownership performs a “directed yield” of the remainder of its processing quantum to the other thread, and execution of the acquiring thread is suspended.

Abstract: In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an image from geometry data. The post-processing object operates to generate a frame of pixel data from the fragment data and to store the pixel data in a frame buffer. In parallel with operations of the host processor, a scanout engine reads pixel data for a previously generated frame and supplies the pixel data to a display device. The scanout engine periodically triggers the host processor to operate the post-processing object to generate the next frame. Timing between the scanout engine and the post-processing object can be controlled such that the next frame to be displayed is ready in a frame buffer when the scanout engine finishes reading a current frame.

Abstract: This invention provides a method for multi-tasking on a media player in a time-slice-circular manner. The method comprises the step of: dividing each of different functions of the media player to a plurality of tasks by a controller unit; setting a priority to each of the tasks by the controller unit; checking the priority of said each of the tasks, and changing a state of a task from “READY” to “EXECUTING” according to the priority of the task by the controller unit; and executing the tasks alternately by using time slices associated therewith by the controller unit. Since all the tasks are executed within a short time, from the user's point of view, all the tasks are executed simultaneously. Thus, multi-tasking on the media player is achieved.

Abstract: A transaction management engine, such as a business process management (BPM) engine, can allow an application to define transaction demarcations in order to ensure that portions of a workflow are processed atomically. In one such system, a JMS message is queued to the workflow as part of an existing transaction. If that transaction commits, the queued JMS message ensures that the workflow will be invoked in a new transaction that allows the workflow to perform the next unit of work in the newly initiated transaction. When the unit of work is completed, the workflow queues another JMS message. If this transaction commits, the transaction ensures the unit of work has executed in a transaction. When the workflow is invoked again due to the second JMS message, the workflow can continue its operation in a different transaction.

Abstract: A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command. A command processor communicates an interrupt signal on a communication path from to a plurality of pipeline processing blocks in a graphics pipeline. A token, which corresponds to an end of an interrupted context, is forwarded from the command processor to a first pipeline processing block and subsequently to other pipeline blocks in the graphics pipeline. Each pipeline processing block discards contents of associated memory units upon receipt of the interrupt signal until the token is reached. The token may be forwarded to one or more additional pipeline processing blocks and memory units so that the token is communicated throughout the graphics pipeline to flush data associated with the first context. Data associated with the second context may follow behind the token through graphics pipeline.

Abstract: The present disclosure is directed to a method and system for task switching with inline execution. In accordance with a particular embodiment of the present disclosure, a first state and a second state are identified for a function executing in the first state. A switch routine is invoked at a particular execution point in the function. A work element is generated in the switch routine. The work element includes status information for the function. The work element is transmitted to at least one alternate state task. The first state is altered to the second state according to the work element. Execution of the function in the second state is resumed at the particular execution point.

Abstract: Techniques for handling certain virtualization events occurring within a virtual machine environment. More particularly, at least one embodiment of the invention pertains to handling events related to the sub-operating system mode using a dedicated virtual machine monitor (VMM) called the system management mode VMM (SVMM), which exists in a separate portion of memory from a main virtual machine monitor (MVMM) used to handle virtualization events other than those related to the sub-operating system mode. In at least one embodiment, a technique for initializing and managing transitions to and from the SVMM is disclosed.

Abstract: A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command so that multiple programs can be executed by the GPU. The CPU creates and the GPU stores a run list containing a plurality of contexts for execution, where each context has a ring buffer of commands and pointers for processing. The GPU initiates processing of a first context in the run list and retrieves memory access commands and pointers referencing data associated with the first context. The GPU's pipeline processes data associated with first context until empty or interrupted. If emptied, the GPU switches to a next context in the run list for processing data associated with that next context. When the last context in the run list is completed, the GPU may switch to another run list containing a new list of contexts for processing.

Abstract: A state machine may have a sequence that is called by multiple threads within the state machine. Prior to calling the sequence, an address specific to the current state is stored in an address register. After the sequence has executed, the address register is queried and the thread may continue. Many different threads may call the sequence. In more complex hardware implemented state machines, the total number of gates may be reduced significantly.

Abstract: A method and system providing switching between a plurality of installed programs in a computer system. Embodiments include a jump function comprising the steps: (1) determining a jump program that is to be the next program to be run, possibly from a plurality of possible choices; (2) creating input data far the jump program based on data in the current program; (3) storing the program state of the currently running program into a context packet and saving the context packet to memory; (4) releasing temporary memory that is used by the program, so as to allow other programs to use the memory; (5) calling the jump program with the created input data as input and terminating the currently running program.

Abstract: To alleviate at least some of the costs associated with context switching, addition fields, either with associated Application Program Interfaces (APIs) or coupled to application modules, can be employed to indicate points of light weight context during the operation of an application. Therefore, an operating system can pre-empt applications at points where the context is relatively light, reducing the costs on both storage and bus usage.

Abstract: Application programs supporting multiple contexts on a computer system having an operating system supporting threads.

Abstract: Various embodiments of the present invention are directed to bimodal virtual device approaches (that is, “bimodal devices”). In certain embodiments, the bimodal device is a virtual device that is primarily based on a real piece of hardware to provide a broad degree of compatibility with software running in the guest environment (similar to the hardware device virtualization approach). However, to overcome the problem of poor performance that plague hardware virtual devices, these embodiments also provide an idealized “high-performance mode” that is not found in the original hardware-based device. Software drivers (and other software) developed for interacting with the original hardware device and which are unaware of (and unable to use) the high-performance mode will continue to use the “legacy mode” (hardware virtualization), while enhanced versions of guest software will be able to recognize and utilize the high-performance mode (idealized virtualization).

Abstract: Embodiments of an invention using cached dirty bits for context switch consistency checks are disclosed. In one embodiment, a processor includes control logic and a cache. The control logic is to cause a consistency check to be performed on a subset of a plurality of state components during a first context switch. The cache is to store a dirty entry for each state component to indicate whether the corresponding state component is included in the subset.

Abstract: Systems for context switching a requestor engine during an atomic process without corrupting the atomic process. Typically an atomic process cannot be interrupted prior to completion and if it is interrupted, the process will terminated abnormally resulting in a corrupted transaction. Systems that allow for a controlled interruption of an atomic process without corruption with subsequent context switching are presented. The system consists of a context-switchable requester engine, a context switch controller, shared resource synchronizer, and a shared resource system. The system may also containing multiple local and remote context-switchable requestor engines as well as multiple local and remote shared resource systems. A method for context switching a requestor engine during an atomic process without corrupting the atomic process is also presented.

Abstract: In a method of and system for program thread synchronization, an instruction cache line is determined each of a plurality of program threads to be synchronized. For each processor executing one or more of the threads to be synchronized, execution of the thread is halted at a barrier by rendering the determined instruction cache line unavailable. Execution of the threads resumes by rendering the determined instruction cache lines available.

Abstract: A method of generating a unique identifier without requiring platform-specific software, a computer readable medium embodying instructions for implementing the method, and a system therefor are described. In response to an event occurrence on a computer system, execution of the method retrieves an event timestamp from an intermediate operating environment on the computer system. Further execution of the method retrieves a system name and a hash value from the intermediate operating environment on the computer system. The combination of the system name, event timestamp, and hash value creates a unique identifier uniquely identifying the intermediate operating environment on the computer system without requiring platform-specific software.

Abstract: A method and a device may be provided for saving and restoring one or more settings associated with the device. The one or more settings may be saved and changed before performing a task. After completion of the task, or after a determined failure of the task to complete, the one or more settings may be restored. Communications may be exchanged between a host and the device to create a restore point for saving the one or more settings, to change any of the one or more settings before performing the task, and to restore the one or more settings after completion of the task, or after determining the failure of the task to complete. The device may create and store the one or more settings in a restore point in the device, or may send the one or more settings to the host for storing.

Abstract: A dynamic race detection system and method overcomes drawbacks of previous lockset approaches, which may produce many false positives, particularly in the context of thread fork/join and asynchronous calls. For each shared memory location, a set of locks that are protecting the location and a set of concurrent thread segments that are accessing the location are maintained. To maintain these sets, each thread maintains a set of locks it is currently holding and a set of thread segments ordered before its current thread segment. Each thread also maintains a virtual clock that is incremented when it forks a second thread. A thread segment is a pair comprising a thread identifier and a virtual clock value. A data race is reported when the lockset for a particular shared memory location is empty and the cardinality of the set of concurrent threads for that memory location is greater than one.

Abstract: A graphics processing unit (“GPU”) is configured to receive an interrupt command from a CPU or internal interrupt event while the GPU is processing a first context. The GPU saves the first context to memory and records a precise processing position for the first context corresponding to the point interrupted. Thereafter, the GPU loads a second context to the processing portion of the GPU from memory and begins executing instructions associated with the second context. After the second context is complete of if an interrupt command directs restoration of the first context, the GPU's processor switches to the first context for continued processing. The first context is retrieved from memory and restored to the precise processing position where previously interrupted. The GPU then processes a remainder portion of the first context from the precise processing point to an end of the first context.

Abstract: A method includes performing a file system integrity validation on a host machine having a hypervisor architecture when a file system of a second process is mounted on a file system of a first process. The file system integrity validation occurs independently of booting the host machine.

Abstract: In an embodiment, a data processing system comprises a storage system coupled to a unit under test comprising a heap memory, a static memory and a stack; second logic operable to perform: detecting one or more changes in a first state of the heap memory and the static memory; storing, in the storage system, as a state point of the unit under test, the one or more changes in the first state of the heap memory and the static memory; third logic operable to perform: receiving a request to change the memory under test to a particular state point; in response to the request, loading the particular state point from the storage system and applying the state point to the heap memory and the static memory to result in changing the heap memory and the static memory to a second state that is substantially equivalent to the first state.

Abstract: A system and method are presented for converting a multi-boot computer to a virtual machine. Existing boot images on a multi-boot computer are identified and converted into virtual machine instances. Each virtual machine instance represents an operating system and is capable of running at the same time. Finally, a new hosting operating system is installed. The new hosting operating system launches and manages the converted virtual machine instances.

Abstract: A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.

Abstract: An apparatus initiates, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.

Abstract: Various operations are disclosed for improving the operational efficiency of interrupt handling in a virtualized environment. A virtualized interrupt controller may obviate the need for an explicit end-of-interrupt command by providing an automatic EOI capability even when a physical interrupt controller offers no such mechanism. The use of a message pending bit for inter-partition communications facilitates avoiding an EOI command of inter-processor interrupts used in inter-partition communications whenever no further messages are cued for a particular message slot. A virtualized interrupt controller facilitates the selective EOI of an interrupt even when it is not the highest priority in-service interrupt irrespective of whether a physical interrupt controller provides such functionality.

Abstract: Context-aware systems and methods, location-aware systems and methods, context-aware vehicles and methods of operating the same, and location-aware vehicles and methods of operating the same are described. In various embodiments, a context or location service module, implemented in software, determines a vehicle context or a vehicle location based upon information that it receives from various context providers or location providers respectively. Software executing on a vehicle's computer can then cause one or more applications that are associated with a vehicle computer to be modified in a manner that changes their behavior. The behavior modification is based on the current context or location of the vehicle and thus provides a context-specific or location-specific user experience. The context or location can be ascertained through the use of one or more hierarchical tree structures that comprises individual nodes. Each node is associated with a context or location.

Abstract: Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.

Abstract: A resource scheduler is provided for allocating a computer system resource to database management system (DBMS) processes. The resource scheduler operates according to resource plans and resource allocation methods. Each plan allocates the resource according to a resource allocation method. During operation of the DBMS, any of the active plans and resource allocation method may be exchanged for alternate plans or resource allocation methods. The resource scheduler enforces an emphasis resource allocation method in which processor time is allocated in percentages to groups of database processes groupified according to common execution requirements. A selected plan includes multiple process groups and/or sub-plans. The resource scheduler allocates processor time in multiple levels among the sub-plans and groups of database processes. Database processes are automatically switched between the groups of a plan according to switch criteria.

Abstract: A configurable input/output interface is described that can be programmed to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Abstract: A method for application managed CPU context switching. The method includes determining whether state data of a CPU is valid for a process. The determining is performed by the process itself. If the state data of the CPU is not valid for the process, the process accesses functional hardware of the CPU to load new state data into the CPU. The process then continues to execute on the CPU using the new state data. If a context switch occurs, the existing state data of the CPU is invalidated. The state data of the CPU can be invalidated by an operating system without storing the state data in main memory.

Abstract: In general, the invention relates to a system that includes a multi-core processor and a dispatcher operatively connected to the multi-core processor. The dispatcher is configured to receive a first plurality of threads during a first period of time, dispatch the first plurality of threads only to a first core of the plurality of cores, receive a second plurality of threads during a second period of time, dispatch the second plurality of threads only to a second core of the plurality of cores, migrate to the second core any of the first plurality of threads that are still executing on the first after the first period of time has elapsed. The duration of the first period of time and the duration of the second period of time are determined using a thread migration schedule, and thread migration schedule is determined using at least one thermal characteristic of the multi-core processor.

Abstract: A method and system providing switching between a plurality of installed programs in a computer system. Embodiments include a jump function comprising the steps: (1) determining a jump program that is to be the next program to be run, possibly from a plurality of possible choices: (2) creating input data for the jump program based on data in the current program; (3) storing the program state of the currently running program into a context packet and saving the context packet to memory; (4) releasing temporary memory that is used by the program, so as to allow other programs to use the memory; (5) calling the jump program with the created input data as input and terminating the currently running program.

Abstract: A halt sequencing protocol permits a context switch to occur in a processing pipeline even before all units of the processing pipeline are idle. The context switch method based on the halt sequencing protocol includes the steps of issuing a halt request signal to the units of a processing pipeline, monitoring the status of each of the units, and freezing the states of all of the units when they are either idle or halted. Then, the states of the units, which pertain to the thread that has been halted, are dumped into memory, and the units are restored with states corresponding to a different thread that is to be executed after the context switch.

Abstract: The present invention relates to the implementation for implementing multi-tasking on a digital signal processor. For that purpose blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which in stead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

Abstract: Systems and methods for optimizing the task scheduling efficiency of firmware and/or software associated with optoelectronic transceiver devices. In one example, a scheduling module executes microcode that schedules tasks based on the operational parameters. The scheduling module compares operational parameters with their last known values and then flags necessary tasks to be initiated. The scheduling module flags only those tasks that rely on a particular operational parameter and only if the operational parameter has changed in value since the most recent time that it has been measured. Specifically, the scheduling module identifies leading tasks and dependent tasks and flags tasks only if data that relies on the operating parameter has changed since a previous task scheduling determination.

Abstract: Various technologies and techniques are disclosed that provide fast context switching. One embodiment provides a method for a context switch comprising preloading a host virtual machine context in a first portion of a processor, operating a guest virtual machine in a second portion of the processor, writing parameters of the host virtual machine context to a memory location shared by the host virtual machine and the guest virtual machine, and operating the host virtual machine in the processor. In this manner, a fast context switch may be accomplished by preloading the new context in a virtual processor, thus reducing the delay to switch to the new context.

Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.