Abstract: A computer has a table for managing a relationship between classes under which data to be processed unique to each of at least one first application program is classified according to a function/attribute thereof, and processes assigned to each class and each capable of being executed by a second application program. The table manages a relationship between said process and said second application program that executes said process. An in-context launching managing method comprises: when one of said data is selected, specifying the class to which said selected data belongs; extracting at least one process that is assigned to said specified class, creating a process list including the extracted process, and displaying said created process list; when one of said process is selected from said process list, accepting said selected process; and specifying the second application program related to said accepted process, and starting said specified second application program.

Abstract: The present invention relates to a processor system. The processor system is made up of a multithread control unit for selectively making switching among said threads to be executed in an arithmetic unit, a loop predicting unit for predicting a loop of an instruction string on the basis of a processing history of a branch instruction in the thread, and a loop detecting unit for, when the loop predicting unit predicts the loop, detecting the loop on the basis of an instruction. When the loop detecting unit detects the loop, the multithread control unit making the switching from the thread, which is in execution in the arithmetic unit, to a different thread. This prevents a wait condition stemming from the loop from interfering with the execution of other threads without retouching software.

Abstract: A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service. The system comprises, a first determination logic for determining control status of all of the contexts, a second determination logic for determining if a context is idle or not, a selection logic for selecting a context and a context release mechanism for releasing the selected context. Determination by the logic system that all contexts are singularly owned by an entity not responsible for packet processing and that at least one of the contexts is idle, triggers immediate selection and release of an idle one of the at least one idle contexts to an entity responsible for packet processing.

Abstract: A system and method for facilitating the collaborative co-browsing of a document or web page. A collaboration server retrieves content of a page on behalf of a collaboration participant or attendee. Each attendee operates or views the content with a browser that is augmented with a collaboration applet. Tags, links, script code and other references that may cause a different page to be accessed or loaded fro the current page are transformed or replaced on the server before the page is distributed to the attendees. In particular, events and redirections that may cause the attendee browser to directly navigate to another page are transformed on the server. Pre-determined rules may be applied to prevent some attendees from viewing certain content (e.g., financial or personal data). A page may be further transformed at a client browser, to redirect a hyperlink to the collaboration server or to trap some other event.

Abstract: According to some embodiments, a portion of local memory allocated to a thread by a programming statement includes an indication of a read/write status of the portion and symbolically references a buffer name wherein the symbolically referenced buffer name includes both letters and numbers.

Abstract: The present invention is directed to a method of operation and a control program for a central unit (e.g., CPU) in an automation system repeatedly executing a control program that is stored in the central unit and comprises at least two subprograms. A single instance of execution occurs within a cycle time which is stipulated by the control program. The central unit executes only one of the subprograms—the activated subprogram—at a time. The cycle time is independent of the activated subprogram, is shorter than the time required in order to execute all of the subprograms, and is at least as long as the longest time period required in order to execute one of the subprograms once.

Abstract: A conversational computing system that provides a universal coordinated multi-modal conversational user interface (CUI) (10) across a plurality of conversationally aware applications (11) (i.e., applications that “speak” conversational protocols) and conventional applications (12). The conversationally aware maps, applications (11) communicate with a conversational kernel (14) via conversational application APIs (13). The conversational kernel (14) controls the dialog across applications and devices (local and networked) on the basis of their registered conversational capabilities and requirements and provides a unified conversational user interface and conversational services and behaviors. The conversational computing system may be built on top of a conventional operating system and APIs (15) and conventional device hardware (16). The conversational kernel (14) handles all I/O processing and controls conversational engines (18).

Abstract: A data-processing circuit includes first and second cooperating processors where one of the processors context switches between applications without running an operating system. In one implementation, the first processor operates under the control of an operating system to switch back and forth between executing a first application or portion thereof and executing a second application or portion thereof. And the second processor operates in a stand-alone mode to switch back and forth between the first application or a portion thereof and the second application or a portion thereof. In another implementation, the first processor runs a single application or portion thereof but no operating system, and the second processor operates in a stand-alone mode to switch back and forth between different applications or different portions of the same or different applications.

Abstract: A method, apparatus or stored program for adjusting the clock throttle rate of a central processing unit (CPU) included in a computer, in which the usage of the CPU is measured, so that the clock throttle rate of the CPU can be automatically adjusted on the measured usage of the CPU, thereby reducing the consumption of electric power without any influence on the performance of the computer.

Abstract: Methods and arrangements are provided for use in multiple user computing environments. These methods and arrangements can be configured to allow for a plurality of separate and concurrent desktops and workspaces within the shared computing environment. One method includes creating a separate desktop thread for each user that is authenticated during a logon process, creating a separate desktop associated with each desktop thread, and maintaining a list of desktop threads that are created. In this manner, several users can be logged on simultaneously. In certain implementations, the method further includes establishing a separate user environment associated with each desktop and launching a separate user shell associated with each desktop. The list of desktop threads allows for selective and/or automatic switching from a first desktop to a second desktop without terminating a desktop thread associated with the first desktop. The methods and arrangements are also applicable to remote process logon and switching.

Abstract: A navigation tool permits access between separate program modules by communicating state information between each program. By communicating state information between separate program modules, it is possible for a user to access previous screens of data, irrespective of the program module which generated the display, or to advance to previous screens of data if the user has already accessed a previous display. In other words, interactions between separate program modules become seamless in presentation to the user, analogous to how information can be displayed with a internet browser or as if separate program modules were operating under a common shell.

Abstract: An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated from the source code descriptive of operation of the parallel operation apparatus according to limiting conditions, registered in advance, representing a physical structure, etc. of the parallel operation apparatus, and scheduled in a Control Data Flow Graph (CDFG). An Register Transfer Level (RTL) description is generated from the CDFG, converting a finite-state machine into an object code and converting a data path into a net list. An object code of the processing circuits is generated in each context from the net list.

Abstract: A method and apparatus for implementing vertical multi-threading in a microprocessor without implementing additional signal wires in the processor has been developed. The method uses a pre-existing signal to serve as a multi-function signal such that the multi-function signal can be used for clock enable, clock disable, and scan enable functions. The single multi-function signal exhibits multiple functionalities as needed by a flip-flop to operate in a plurality of modes. The method allows for the use of a pre-existing signal wire to be used as a process thread switch signal that would otherwise have to be explicitly hard-wired in the absence of the multi-functioning signal. The method further includes allowing multiple-bit flip-flops to be placed at sequential stages in a pipeline in order to facilitate vertical multi-threading and, in effect, increase processor performance. The apparatus provides means for distinguishing between specific characteristics exhibited by the multi-function signal.

Abstract: A technique for tracking a state of one or more input/output (I/O) channels associated with an application, by the application itself, comprises the steps of: (i) storing, by an operating system kernel, one or more selected elements of the state of at least a portion of the one or more I/O channels associated with the application in a memory which is shared by the application and the operating system kernel, when the one or more elements are available to the operating system kernel; (ii) acquiring, by the application, at least a portion of the stored elements through one or more memory read operations of the shared memory; and (iii) assessing, by the application, one or more of the acquired elements to determine the state of the one or more I/O channels corresponding thereto. In this manner, a need for context switching to track the state of the one or more I/O channels is thereby eliminated.

Abstract: The present invention accepts an acyclic concurrent control-flow graph (CCFG) and produces a sequential control flow graph (SCFG) that, when executed, behaves functionally like the CCFG would if it were run on concurrent hardware. An SCFG can be easily translated into a traditional sequential programming language such as C or assembly to be executed on a traditional sequential processor. Determining the order in which CCFG nodes will be run is the first step in the process. Control edges in the CCFG constrain the order in which CCFG nodes must run; communication between threads generally impose further constraints. An easy way to further constrain a valid order of CCFG nodes is to augment the CCFG with data dependence edges (representing inter-thread communication) and to then topologically sort the nodes in the augmented graph to produce an ordering.

Abstract: A method, system, and program product for saving a state of a task and executing the task by processors such that following the termination of execution of the first task in a first processor, at least a portion of a state of the first task is maintained in registers of the first processor until the first processor executes a second task. Prior to executing the first task on the second processor, a determination is made as to whether the state of the first task is at least partially stored in the registers of another processor, such as the first processor. If the state of the first task is at least partially stored in the registers of the first processor, then contents of said registers in the first processor are stored into a memory system. Thereafter, the first task is executed in the second processor.

Abstract: A small footprint device can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same namespace or memory space or to see that a requested action is authorized for an object to be operated upon. Each program or set of programs runs in a separate context. Access from one program to another program across the context barrier can be achieved under controlled circumstances by using shared interface objects. Shared interface objects have a property that permits them to be accessed across the context barrier regardless of security restrictions that would otherwise apply. Shared interface objects, however, may enforce their own security rules independently of the context barrier.

Abstract: A method and data processing system are presented for multitasking a plurality of simultaneous tasks over one or more data processors. The invention significantly reduces the overhead required for multitasking without sacrificing responsiveness or flexibility. Both the number and length of context switches are reduced. The resulting environment is also capable of providing real-time operation and memory protection to tasks. No modifications to the tasks are required to make use of the invention.

Abstract: An embedded system and method for performing a background code update of a current code image with an incoming code image is provided. The method includes executing the current code image in the embedded system; executing one or more code update routines from the incoming code image to update the current code image with the incoming code image; and executing a task switching function from the current code image to switch microprocessor control from executing the one or more code update routines of the incoming image to execute a function in the current code image. The system and method also involves retrieving an offset from the incoming code image for the one or more code update routines in the incoming code image. The system and method further involves retrieving an offset from the current code image of a task switching function.

Abstract: System for providing transitions between operating modes of a device. The system includes a method for providing transitions between a privileged and a non-privileged operating mode. The method comprises executing an application in the non-privileged mode, generating an interrupt to request the services of a privileged function, and transitioning to the privileged mode to execute the privileged function, wherein the privileged function is executed as part of the same thread of execution as the application.

Abstract: The invention comprises a modem apparatus adapted to provide full messaging and communications interface between a control device and a communications medium such as a telephone line. The modem can comprise an interface adapted to communicate directly with a control system device, such as a programmable logic controller (PLC), using a communications protocol compatible with the normal network communications used in a distributed control system. The apparatus advantageously interfaces directly with unmodified control system devices, providing the ability to send and receive messages from remote devices or personnel via a communications medium. The invention also comprises a control system including a modem device providing full communications between a control device and remote personnel and/or devices.

Abstract: An electronic controller for conducting trusted lightweight e-commerce transactions. A trusted transactional cache and the associated transactional protocol allow e-commerce transactions to be committed to a remote server extremely quickly and with little network overhead. The end-to-end transactions are completed is just a few seconds or less. The invention operates equally well on robust private networks as on unpredictable Internet or wireless networks. The transaction is automatically completed following a temporary communication failure with the central site or following a temporary local controller failure. The invention can advantageously be used in embedded Internet products such as fixed or mobile Internet kiosks, transactional terminals, and Internet Appliances.

Abstract: Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system management mode while waiting for polled hardware events, handling any pending lower-priority interrupts and then resuming polling. The present invention does this by multi-threading SMI source handlers, using an idle thread, and using protocols for software-generated system management interrupts that insure that lower priority interrupts are serviced.

Abstract: Methods, systems, and computer program products that, by defining a common interface, allow for a single implementation of operations common to both kernel mode and user mode processing, relative to a hardware adapter. Corresponding kernel mode and user mode implementations of the operations are provided. For a given process, a call to the common interface is mapped to the kernel mode implementation for kernel mode processes and to the user mode implementation for user mode processes. The mapping may be performed at runtime or may be static. The common operation may provide a user mode process direct access to a hardware adapter, such as for sending and receiving information, without switching to kernel mode. A kernel mode implementation for operations unique to kernel mode processing, such as specifying security parameters for the hardware adapter to enforce, or initiating and terminating communication through the hardware adapter, also may be provided.

Abstract: A system and method is described which provides for context checking of an operating environment. A context manager controls the execution of context checks requested by applications or processes. In one embodiment, the context check modules are defined as self-contained modules located in a database. When the data base is opened, these modules are loaded and registered with the context manager. Upon occurrence of certain user actions, the context manager will issue an event to cause the appropriate modules to perform a context check of certain context of the environment. The resulting context information is stored in memory by the context manager and provided to the applications by the context manager when needed. One advantage is that the context checks performed can be changed simply by adding or deleting modules from the database.

Abstract: System and method for supporting split transactions on a bus. The method may comprise processing a periodic frame list of external bus data frame by frame, and traversing each frame node by node. When a save place node is encountered in a first frame, the traversing jumps to a destination node pointed to by the save place node in a second frame, and continues the traversing there. When a restore place node is encountered when traversing the nodes in the second frame, the traversing returns to the node after the save place node in the first frame and continues the processing in the first frame. The method may be implemented on a system that comprises a processor, a memory, an internal bus, and an external bus controller. The external bus controller and the external bus data may support one or more versions of the Universal Serial Bus standard.

Abstract: A method and multithreaded processor for handling livelocks in a simultaneous multithreaded processor. A number of instructions for a thread in a queue may be counted. A counter in the queue may be incremented if the number of instructions for the thread in the queue in a previous clock cycle is equal to the number of instructions for the thread in the queue in a current clock cycle. If the value of the counter equals a threshold value, then a livelock condition may be detected. Further, if the value of the counter equals a threshold value, a recovery action may be activated to handle the livelock condition detected. The recovery action may include blocking the instructions associated with a thread causing the livelock condition from being executed thereby ensuring that the locked thread makes forward progress.

Abstract: A physical memory of a single computer is divided for each of a plurality of operating system (OS). A first OS is first loaded into the computer and runs. A multi-OS management program common to a plurality of OSs is incorporated into a virtual address space of the first OS as a device driver of the first OS. The multi-OS management program incorporated as the device driver is rearranged in a memory area shared by OSs so that the multi-OS management program has the same virtual address in any OS. In this state, the second OS program itself is loaded in the virtual address space of the second OS by execution of the multi-OS management program in the first OS. Execution of the multi-OS management program is switched from the multi-of management program in the first OS to the multi-OS management program in the second OS. Then, the second OS is started by execution of the multi-OS management program in the second OS to thereby run the plurality of OSs on the single computer.

Abstract: Preparing one or more secure media effect programs, generating a binary image of the programs and associated data, loading the binary image into memory of a secondary processor, and executing the programs of the binary image with the secondary processor, substantially independent from a primary processor. A binary image builder automatically maps one or more programs and data to secondary processor memory by changing encoded binary instructions of each program before execution by the secondary processor. The changes identify locations at which the programs and data will be stored in secondary processor memory, identify locations of parameters that can be updated in real time, and enable execution control to return to a secondary processor execution kernel. The secondary processor execution kernel polls flags in a main memory to determine whether to download new or updated state data and/or program code from main memory to the secondary processor memory.

Abstract: A context management and administration system includes a context manager, which manages the context of plural applications programs, and an administration suite, which oversees and manages the manager. Context administration can include setting up and maintaining subject data definitions, intervening in context manager operations, providing security functions to protect sensitive context information against tampering by unauthorized users, etc.

Abstract: Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread.

Abstract: The present invention discloses a communication system including an entire object including multiple objects connected with the networks and storing the object's own data, a database including a polling table storing information for an object being performed data polling among the multiple objects, and a mapping controller for controlling data flows of the entire object, and of the object of the polling table in the database, where the mapping controller includes a configuration module for performing data polling to, and for managing the entire object, a performance module for managing performance data of the entire object and for each of the objects, a performance-polling module for calculating performance data by an alarm information for an object having troubles among the entire objects, for receiving the performance data accumulated in the entire object periodically, and for informing the received performance data to the performance module, and a mutual exclusion module for determining priority among each

Abstract: Method and apparatus for handling communication requests at a server without context switching. An application protocol subsystem and protocol modules are disposed within an operating system kernel at a server. The protocol subsystem creates an “in-kernel” protocol stack that stores information regarding application protocol requests, such as HTTP and FTP requests, in a kernel request structure. A user space application can then continue execution while the operating system responds to the application protocol request without context switching. In this way, application protocol requests received over a network are handled and responded to by the server without causing a context switch.

Abstract: A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) a time slice instruction counter that counts a number of instructions executed with respect to a given background task and (2) a background task controller that cyclicly executes a context corresponding to another background task when the number of instructions executed equals a dynamically-programmable time slice value.

Abstract: A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

Abstract: A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The utilization of processor resources is distributed between threads according to the quantity of instruction data for a particular thread that has been processed (or dispatch for processing), and not according to an arbitrary timing mechanism.

Abstract: A method and apparatus for synchronizing and communicating between processing entities, such as cores or threads, in a multiprocessor. Two registers are used as a “hardware mailbox” by two processing entities of a microprocessor. A first register is used to communicate information from a first processing entity to a second processing entity, while a second register is used to communication information from the second processing entity to the first processing entity. The first and second registers are cross-decoded by the two processing entities. One or more bits in each register are used to synchronize operation of the processing entities. In a microprocessor including three or more such processing entities, a read-write register of each processing entity holds outgoing information and a read-only register of each processing entity holds incoming information. A separate logic circuit logically combines the contents of the read-write registers and stores the result in the read-only registers.

Abstract: A multithreaded processor includes an interrupt controller for processing a cross-thread interrupt directed from a requesting thread to a destination thread. The interrupt controller in an illustrative embodiment receives a request for delivery of the cross-thread interrupt to the destination thread, determines whether the destination thread of the cross-thread interrupt is enabled for receipt of cross-thread interrupts, and utilizes a thread identifier to control delivery of the cross-thread interrupt to the destination thread if the destination thread is enabled for receipt of cross-thread interrupts. The requesting thread requests delivery of the cross-thread interrupt to the destination thread by setting a corresponding interrupt pending bit in a flag register of the multithreaded processor. The destination thread is enabled for receipt of cross-thread interrupts if a corresponding enable bit is set in an enable register of the multithreaded processor.

Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The predetermined quantity of the instruction information may be equal to or greater than a minimum quantity of instruction information for a full instruction of a first instruction set.

Abstract: A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other threads to reclaim its queue node immediately (in the absence of preemption), or mark its queue node to allow reclamation by a successor thread.

Abstract: An application initiates a parent process (102) to begin executing the application. The parent process (102) creates a child process (104) to execute the application. The parent monitors the death of the child process using inter-process communications (118). The child process monitors the parent process using polling (114, 116). If the parent process detects the death of the child, the parent process creates another child to continue the processing of the dead child. If the child process detects the death of the parent process (119), the child creates another child process (120) to execute the application it previously executed. The original child, now a parent, monitors the child process via inter-process communication (128).

Abstract: The present invention provides a method, system, and computer program product for improving scheduling of tasks in systems that accumulate execution time. An upper bound is computed on the amount of additional time each schedulable task in the system may continue to execute after exceeding its predetermined cost, without adversely affecting overall operation of the system (that is, ensuring that the continued execution will not cause invocations of subsequent tasks to fail to meet their execution deadlines). By allowing tasks to run longer, the potential that the task will successfully end is increased, thereby yielding a more efficient overall system. In the preferred embodiment, the extensions are iteratively computed as a fixed percentage of the cost of each task until reaching an amount of time where the system is no longer feasible.

Abstract: A method and apparatus is provided for providing and integrating high-performance message queues. “Contexts” are provided that allow independent worlds to be created and execute in parallel. A context is created with one or more threads. Each object is created with context affinity, allowing any thread inside the context to modify the object or process pending messages. Threads in a different context are unable to modify the object or process pending messages for that context. To help achieve scalability and context affinity, both global and thread-local data is often moved into the context. Remaining global data has independent locks, providing synchronized access for multiple contexts. Each context has multiple message queues to create a priority queue. There are default queues for sent messages and posted messages, carry-overs from legacy window managers, with the ability to add new queues on demand. A queue bridge is also provided for actually processing the messages.

Abstract: A graphics system comprising a plurality of rendering pipelines and a scheduling network. Each rendering pipeline couples to the scheduling network, and includes a media processor, a rendering unit and a memory. A communication bus may couple the scheduling network and the memory of each rendering pipeline. The media processor in each rendering pipeline may direct the saving of state information of the corresponding rendering pipeline to the corresponding memory in response to receiving a corresponding context switch indication. A first of the media processors initiates the transfer of a resume token to the scheduling network through the corresponding rendering pipeline if the context switch occurs during an ordered processing mode. The scheduling network unblocks one or more rendering pipelines other than the first rendering pipeline in response to receiving the resume token.

Abstract: A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.

Abstract: The present invention provides a method and apparatus for controlling a processing priority assigned alternately to a first thread and a second thread in a multithreaded processor to prevent deadlock and livelock problems between the first thread and the second thread. In one embodiment, the processing priority is initially assigned to the first thread for a first duration. It is then determined whether the first duration has expired in a given processing cycle. If the first duration has expired, the processing priority is assigned to the second thread for a second duration.

Abstract: A small footprint device can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same context or to see that a requested action is authorized for an object to be operated upon. Each program or set of programs runs in a separate context, however, one context has access to all program modules without context barrier constraints.

Abstract: A program control apparatus ensuring real time response by ensuring execution of a process exclusively without locking the system includes a unit responsive to an application program interface call from a thread which interface requesting start of detection of presence/absence of a context switching, for setting a flag indicating presence/absence of a context switching to a state corresponding to absence of a context switching, a unit for setting, after said flag is set to the state corresponding to absence of a context switching and a scheduler switches context, the flag to a state corresponding to presence of a context switching, and a unit responsive to an application program interface call from the thread, which interface requesting termination of detection of presence/absence of a context switching, returning a value corresponding to the state of the flag to the thread.

Abstract: A small footprint device can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same namespace or memory space or to see that a requested action is authorized for an object to be operated upon. Each program or set of programs runs in a separate context. Access from one program to another program across the context barrier can be achieved under controlled circumstances by using a global data structure.