Abstract: A method for controlling an address conversion buffer, constituted on a processor capable of executing a plurality of threads simultaneously on one core, includes registering address conversion information in an entry of the address conversion buffer that includes a first memory area usable by one of the threads and a second memory area shared among all the threads, allocating a part of the second memory area as a swap area of the first memory area, and transferring data in the swap area to the first memory area, based on thread switching executed by the processor.

Abstract: Network processes within a group of network processes are configured to share stack space by controlling when a context switch may be performed between processes in the group. Since a context switch will not be performed between group members during execution of the event loop, the dedicated stack requirements of the process are limited to that required to store state information when the process is idling on a select function. This reduces system stack requirements by allowing a large portion of the stack to be shared by multiple network processes without creating unintended dependencies between the processes. A semaphore may be used to control access to the shared stack space to prevent unintended context switches between group members. If there is more than one group of processes, the operating system may perform context switches between processes in different groups since each group has its own dedicated area of shared stack.

Abstract: A determination of processor core utilization by a plurality of hardware threads over a time interval is made through a division of a length of the time interval by a total count of the plurality of hardware threads.

Abstract: An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority of a thread, the software uses a special form of a “no operation” (NOP) instruction (hereafter termed thread priority NOP). When the thread priority NOP is dispatched, its special NOP is decoded in the decode unit of the IDU into an operation that writes a special code into the completion table for the thread priority NOP. A “trouble” bit is also set in the completion table that indicates which instruction group contains the thread priority NOP. The trouble bit indicates that special processing is required after instruction completion. The thread priority instruction is processed after completion using the special code to change a thread's priority.

Abstract: Described is an enhanced application of a fast kernel trap, or kernel function call, in combination with a kernel system call providing a system of handling complications during kernel thread operations. In the event of a complication during kernel function call processing, the kernel function call promotes to a system call. If the kernel function call holds a spin lock at the time of promotion, the spin lock is released. Kernel function call processing is divided into phases and a phase identifier is provided to the system call. To avoid repeating processing steps already performed by the kernel function call, system call processing begins at the phase where the complication occurred. When the system call processing reaches a suspend phase, the system call will demote to a kernel function call and release its kernel stack.

Abstract: A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.

Abstract: The present invention provides a method and system for automated handling of resolvable and non-resolvable errors in the execution of system management flows by enhancing Workflow Engines (30) by an Error Handling component (40) and by adding a supportive Error Handling Layer (60,90,100) to invoked system management tasks which serves as the counterpart to the Workflow Engine's Error Handling component (see FIG. 2). The additional functionality of the task-provided Error Handling Layer (90, 70, 100) is accessible for the Workflow Engine via extended web services interfaces (91, 71, 101). The Workflow Engine's Error Handling component (40) and the task-provided Error Handling Layer allow for the definition of a standard protocol between the Workflow Engine and invoked tasks (31) for automated error handling.

Abstract: A method to locate, resolve, and invoke software functions, wherein the method forms a request comprising a resource identifier, resolves the request to an endpoint, evaluates the request by the endpoint to generate a resource representation.

Abstract: Server appliances provide context management functionality in the healthcare field and other fields. The server appliances may present themselves on a network as one or more World Wide Web sites accessible to applications whose context is managed.

Abstract: A register file bit includes a primary latch and a secondary latch with a feedback path and a context switch mechanism that allows a fast context switch when execution changes from one thread to the next. A bit value for a second thread of execution is stored in the primary latch, then transferred to the secondary latch. The bit value for a first thread of execution is then written to the primary latch. When a context switch is needed (when the first thread stalls and the second thread needs to begin execution), the register file bit can perform a context switch from the first thread to the second thread in a single clock cycle. The register file bit contains a backup latch inside the register file itself so that minimal extra wire paths are needed to or from the existing register file.

Abstract: A system and method for increasing Operating System (OS) idle loop performance in a simulator environment. Upon encountering an OS idle loop condition on a processor, OS program flow is skipped ahead by an amount of time, thereby conserving the host machine's resources that would otherwise have been spent in supporting the OS idle loop execution. If another processor initiates an inter-processor message directed to a processor whose OS program flow has been skipped forward, that processor is capable of skipping backward in time, if necessary, to service the inter-processor message.

Abstract: In a distributed control method of executing distributed control such that a lot of tasks distributively executed in a lot of nodes connected to a network and made to implement multitasking operations communicate a message with each other to operate cooperatively in time sequence, an estimated completion time of the distributed control is calculated by summing up the worst execution times of the processing times of all tasks pertaining to the distributed control and the communication times of all messages between the tasks and an initial value of a margin time with respect to a deadline is determined by subtracting the estimated completion time from a control cycle of the distributed control. This margin time is set for each of all the distributed control to be executed on the system and is sequentially updated in accordance with the states of the tasks and messages. The processing on the tasks or the transmission of the messages is made preferentially in the order of lengthening margin time.

Abstract: Method, system, apparatus and computer program product for interrupt scheduling in processing communication. In one embodiment the method includes: a sending computer program and a receiving computer program, coupling at least one registered signal identifier and a corresponding registered signal function with said receiving computer program; sending a communication including a request signal identifier by said sending computer program to said receiving computer program; receiving said communication sent at (B) by said receiving computer program; and performing said corresponding registered signal function without context switching of said receiving computer program if said request signal identifier received is coupled with said registered signal identifier. A system, router, computer program and computer program product are also disclosed.

Abstract: A method for utilizing concurrent context switching to support isochronous processes preferably comprises a main context that is configured to support system execution tasks, a first concurrent context that supports a first set of concurrent execution and loading procedures, and a second concurrent context that supports a second set of concurrent execution and loading procedures. A context control module preferably manages switching and loading procedures between the main context, the first concurrent context, and the second concurrent context. The context control module may perform successive concurrent context switching procedures by alternating between the first concurrent context and the second concurrent context to thereby sequentially support any desired number of isochronous processes.

Abstract: In a method for execution control acquisition of a program, during the execution of the program, it is determined when a hardware performance counter has reached a threshold. When the threshold is reached, execution control is switched to a dynamic optimizer. Thereafter, an optimized version of the program is executed. In a method for executing an optimized version of a program, during execution of the optimized version, an interrupt is received and execution control is returned to an operating system. An original version of the program is then executed. During the execution of the original version, a hardware performance counter is monitored. When the hardware performance counter reaches a threshold during the execution of the original version, execution control is switched to a dynamic optimizer. Thereafter, the execution of the optimized version of the program is continued as directed by the dynamic optimizer.

Abstract: A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.

Abstract: A task stack and a context pointer in a task control block (TCB) are implemented to provide more efficient context switching. Additionally, multiple routines each of which saves or restores a certain combination of volatile registers is implemented. A task can store in its task control block a routine identifier to select from the multiple routines a set of routines for saving and restoring volatile registers during context switching. On the occurrence of an event that may lead to a context switch a scheduler selects based on the routine identifier a routine that only saves registers used by the task, thereby, reducing execution overhead. The registers are saved on the task stack and a context pointer to the registers is saved in the TCB. In the event a context switch is necessary, it is not necessary to copy the registers to the TCB because the context pointer is in the TCB. A non-volatile register indicator that indicates whether non-volatile registers are used is stored in the task control block.

Abstract: A multi-context register file for use in a multi-threaded processor includes at least one multi-context register file cell having internal routing functionality.

Abstract: A method, system and computer readable storage medium for executing a set of tasks. The method includes selecting an incomplete task in the set and then either starting its execution (if it was not previously suspended) or resuming its execution (if it was previously suspended). An execution timer is also started. If the selected task completes before expiry of the execution timer, the selection process is reinitiated; otherwise, the selected task is suspended, and the selection process is reinitiated. In this way, processing of a lengthy or lower-priority task can be pre-empted by processing of a shorter or higher-priority task. The method may also involve recognizing that a new version of an existing task already in the task set has been added thereto. In such a case, the older version is removed from the task set even if it is not yet complete.

Abstract: A system and method for performing an interface save/restore procedure in an electronic device includes a processor that begins to execute a first task in conjunction with a host interface of a display processor. The processor subsequently receives an interrupt request for executing a second task that has a higher priority than the first task. A save/restore module responsively stores task states from the host interface into an interface states register. The task states correspond to an interrupted execution point in the first task. The processor temporarily stops the first task to execute the second task. The save/restore module restores the stored task states to the host interface after the second task is completed, and the processor may then efficiently resume the first task.

Abstract: A processor system includes a processor to execute a plurality of tasks by switching to one another, a task ID storage section to store a task ID to identify a task executed in the processor, an evaluation ID storage section to store an evaluation ID to be compared with an at least partial area of the task ID, a counter to measure a performance measurement value of a task executed in the processor, and a matching section to check a task ID stored in the task ID storage section against an evaluation ID stored in the evaluation ID storage section and operate the counter in accordance with a check result.

Abstract: A method, apparatus, and computer instructions for use in an operating system for managing requests for files. A request for a switch file from an application is received. The application points to the switch file. Many files may point to the same switch file. Location information for the switch file points to a set of files. A file from the set of files based on system information to form an identified file is identified. The identified file passes to the application. The system information may be already present within the system or passed to the system by a user or process.

Abstract: A method and a control unit for controlling technical procedures, particularly in a motor vehicle. In the method, a control program of a computing element, particularly a microprocessor, is processed. The control program is subdivided into several tasks and each task is subdivided into several processes. The tasks are processed in a cooperative mode or in a preemptive mode. After the processing of the control program, in order to make possible a simulation as close to reality as possible, particularly an offline open loop simulation, it is proposed that the process sequence be stored during the processing of the control program. Preferably, before the processing of the control program, a unique identifier is assigned to each process, and, during the processing of the control program, only the identifier of the processed process most recently processed before the beginning of a finished task is stored.

Abstract: Disclosed is providing one of a plurality of schedulers for a multitasking system for a processor that includes choosing a particular one of the schedulers, setting a program counter to an address corresponding to code of the particular one of the schedulers, and the processor executing code at an address corresponding to the program counter. Also included may be setting a stack pointer to an address corresponding to stack space for the particular one of the schedulers and the processor using the stack space at the stack pointer after executing code at the address corresponding to the program counter. The system described herein provides a small kernel that can run on a variety of hardware platforms, such as a PowerPC based Symmetrix adapter board used in a Symmetrix data storage device provided by EMC Corporation of Hopkinton, Ma. The core kernel code may be written for the general target platform, such as the PowerPC architecture.

Abstract: Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second value in a second register, is to be restored to a first register. A third value is encoded in a second field of the instruction for adjusting the second value in the second register.

Abstract: With a single program divided into a plurality of threads A to C, at the execution of the threads in parallel to each other by a plurality of processors, determination is made of a forkability of a slave thread into other processor in response to a fork instruction in a master thread being executed by a predetermined processor and when forkable, the slave thread is forked into other processor and when not forkable, the fork instruction is invalidated to execute an instruction subsequent to the fork instruction by the predetermined processor and then execute a group of instructions of the slave thread by the predetermined processor.

Abstract: A method, system and article of manufacture to establish a virtual drive accessible to pre-boot and operating system runtime phases. A virtual drive is constructed from a physical storage device of a computer system during a pre-boot phase of the computer system. A virtual drive controller is initialized during the pre-boot phase to support the virtual drive. Information on the virtual drive is accessed using the virtual drive controller by firmware during the pre-boot phase. The information on the virtual drive is accessed using the virtual drive controller by an operating system (OS) of the computer system during an OS runtime phase, wherein the information is comprehensible by the firmware and the OS.

Abstract: One or more embodiments of the invention provide a method, apparatus, and article of manufacture for collaborating application programs executing on a client such as a personal digital assistant (PDA). A shared database on the client is obtained and used as a common launch parameter stack. One or more program entry records are stored in the database and the last program entry record stored is identified as the top of the stack. Each program entry record may include information regarding an application launched on the client. When the last program identified on the stack has completed execution, the last program entry record is popped off of the stack. Thereafter, control is returned to an application that corresponds to the new program entry record on the top of the stack.

Abstract: A task execution environment switching method in a multitask system, which comprises the steps of: a first step for evacuating current task execution environment information in a stack-exclusive-use execution environment stack to a context evacuating region, as pre-processing for calling processing of a sub-function from a main function within the task; a second step for storing execution environment information of the sub-function in a execution environment stack for function of the task from an execution environment table of the task; a third step for calling the sub-function from the main function within the task; and a fourth step for storing the task execution environment information evacuated in the context evacuating region in the first step in a task of the task-exclusive-use execution environment stack, when processing is returned from the sub-function to the main function.

Abstract: A user interface function for a virtual machine system based on a server or a PC is provided only by applying software without using SVP or the like. A control virtual machine is provided for controlling a virtual machine control screen which is displayed for defining virtual machines and instructing operations to the virtual machines. A virtual machine control program exclusively displays either a screen for each virtual machine or the virtual machine control screen in response to a screen switching instruction from an input device.

Abstract: In a method for dynamic allocation of memory address space, an original version of a program is executed. This execution includes the execution of a request to use memory address space occupied by an optimized version of the program that is protected from modification. When this request is detected, execution control is passed to an optimization code that was used to define the optimized program. The optimization code copies a portion of the optimized program residing in the memory address space requested by the original program, writes the copied portion to unallocated memory address space, and adjusts the code of the optimized program. The protection of the copied portion of the optimized program is released, and execution control is returned to the original program. The request to use the memory address space occupied by the portion of the optimized for which the protection has been released is then re-executed.

Abstract: The present invention relates to a multiprocessor system, which comprises two or more processor elements to be executed by a common program, a control section for switching such plural processor elements one from another for execution by the common program, and a storing section storing handover information relating to the common program which information is to be handover from the one processor element to the another processor element. This not only optimizes each of the functions of the processor elements, but also achieves certain delivery or interchange of the information between these process or elements, and even reduces the power consumption.

Abstract: The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; p? [1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; q? [1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; t? [1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).

Abstract: The present invention provides a virtualized computing systems and methods for transitioning in real time between LONG SUPER-MODE and LEGACY SUPER-MODE in the x86-64 architecture. In doing so, a virtual machine, which relies on the traditional 32-bit modes, i.e., REAL MODE and PROTECTED MODE (V86 SUB-MODE, RING-0 SUB-MODE, and RING-3 SUB-MODE), is able to run alongside other applications on x86-64 computer hardware (i.e., 64-bit). The method of performing a temporary processor mode context switch includes the steps of the virtual machine monitor's setting up a “virtual=real” page, placing the transition code for performing the processor mode context switch on this page, jumping to this page, disabling the memory management unit (MMU) of the x86-64 computer hardware, modifying the mode control register to set either the LONG SUPER-MODE bit or LEGACY SUPER-MODE bit, loading a new page table, and reactivating the MMU of the x86-64 computer hardware.

Abstract: In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a plurality of paths through a mapping array T are being handled by a processor. This sequence of operations, including instructions from the plurality of sets of operations, ensures that there is another operation in the pipeline if a cache miss on any given lookup operation in the mapping array results in a slower main memory access. In this way, the processor utilization is improved. While the sets of operations in the sequence of operations are independent of another other, there will be an overlap of a plurality of the main memory access operations due to the long time required for main memory access.

Abstract: Techniques are provided for use in spin-yielding in multi-threaded systems. Each thread that is waiting for a lock is bound to a spin-yield processor in the list of a plurality of spin-yield processors so that other processors that otherwise may be used for spin-yield cycles by the waiting threads can be used for other purposes by other threads. Further, in a defined time period, a thread is bound to or removed from a spin-yield processor based on the number of context switches experienced by that thread in that defined time period.

Abstract: Systems and methods are provided for managing the computational resources of coprocessor(s), such as graphics processor(s), in a computing system. The systems and methods illustrate management of computational resources of coprocessors to facilitate efficient execution of multiple applications in a multitasking environment. By enabling multiple threads of execution to compose command buffers in parallel, submitting those command buffers for scheduling and dispatch by the operating system, and fielding interrupts that notify of completion of command buffers, the system enables multiple applications to efficiently share the computational resources available in the system.

Abstract: A method is provided for sharing and/or transporting data within a single node of a multi-node data processing. The method avoids the necessity of making more than one copy of the data to be shared or transported. The method is tunable based on the size of the data segment involved. A shared memory area between tasks running in different address spaces on the node is used to coordinate the process and for task to task communication. The increase in efficiency provided by the intranodal process described herein also provides advantages to the internodal communication process since more CPU cycles are available for that aspect of system operation.

Abstract: A method in a computer system for enabling a process to manage the execution of a periodic, single-execution (PSE) task is disclosed. The process represents one of a plurality of processes executing on the computer system, and the PSE task represents a task to be performed once by one of the plurality of processes for each rotation of a periodic schedule. Each of the plurality of processes is capable of performing the PSE task and scheduled to perform the PSE task during the each rotation of the periodic schedule. The method ensures that the PSE task is performed only once by one of a plurality of processes during each rotation of the periodic schedule.

Abstract: Various settings are stored into a setting storage table for stop-key processing. These settings are related to a job kind where an operation is stopped by manipulating a stop key, a job kind where an operation is made to pause, and a job kind where an operation is continued without any interruption. When the stop key is manipulated, the job set to the stop operation is directly stopped, and the job set to the execution continuation is continuously executed. The jobs set to the pausing operations are displayed in a list. These jobs are selected one by one, or in a batch mode. Thereafter, either the stop operation or the restart operation is instructed. Accordingly, even under such an environment that a plurality of jobs are executed in a parallel manner; a desirable job can be quickly stopped, and moreover, lowering of throughputs of other jobs can be suppressed.

Abstract: A processor which is switchable between a first execution mode (such as a scalar mode) and a second execution mode (such as a VLIW mode) is disclosed. The processor has a first processor context when in the first execution mode and a second processor context, different from the first processor context, when in the second execution mode. The processor generates an exception when the processor attempts to change from one execution mode to the other. When the processor switches to a thread of execution which is in the first execution mode, or when the processor switches to a thread of execution which was the last thread to be in the second execution mode, only the first processor context is preserved. The processor may be arranged such that the number of threads that may be in the second execution mode at any one time is less than the total number of threads that may be active on the processor at any one time.

Abstract: A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.

Abstract: The method and apparatus feature detecting an interrupt service request; storing into an instruction cache interrupt service instructions in response to detecting the interrupt service request; and fetching instructions from the instruction cache into an instruction stream sequence, the instruction stream sequence including mainline program instructions and the interrupt service instructions resulting in allocating core processor bandwidth between the interrupt servicing and mainline program instructions while executing the instruction stream sequence based on an interrupt priority; and processing instructions within the instruction stream sequence including the mainline program instructions and the inserted interrupt servicing instructions. The method and apparatus further feature recycling of executed micro-ops and detecting imminent context switch for interrupt service instruction preparation.

Abstract: Methods and apparatuses are provided for controlling application software while switching between sessions in a multi-session computing environment. An apparatus includes memory coupled to switching logic and application program managing logic. The switching logic is configured to selectively switch console control of a computing device between at least two user kernel sessions that are maintained in the memory. The application program managing logic is configured to selectively control at least one application program that is operatively configured within at least one of the user kernel sessions. For example, the application program managing logic can be configured to stop the operation, re-start certain application programs, notify application programs about switching events, and/or adjust the playback of audio and/or video signals associated certain application programs.

Abstract: The invention provides for a real-time multi-task operating process in which a set of fixed adjustable duration observation windows are defined having an allocation stage, in each observation window, of a maximum execution duration for each task, during which a scheduler guarantees a minimum execution time for lower priority tasks; a calculation stage for the time used by each task during each observation window; and a sanction stage during which the tasks, which exceed their quota in a given observation window, are sanctioned and can only return to a central resource unit during the following observation window.

Abstract: Transitions among schedulable entities executing in a computer system are tracked in computer hardware or in a virtual machine monitor. In one aspect, the schedulable entities are operating system processes and threads, virtual machines, and instruction streams executing on the hardware. In another aspect, the schedulable entities are processes or threads executing within the virtual machines under the control of the virtual machine monitor. The virtual machine monitor derives scheduling information from the transitions to enable a virtual machine system to guarantee adequate scheduling quality of service to real-time applications executing in virtual machines that contain both real-time and non-real-time applications. In still another aspect, a parent virtual machine monitor in a recursive virtualization system can use the scheduling information to schedule a child virtual machine monitor that controls multiple virtual machines.

Abstract: A computer system includes a software virtual machine (such as Java) for running one or more applications. An object is provided that is responsive to a call from an application for placing the virtual machine and application into a state of suspension. This involves interrupting all current threads, and recording the state of the components of the virtual machine, including heap, threads, and stack, into a serialization data structure. Subsequently the serialization data structure can be invoked to resume the virtual machine and application from the state of suspension. Note that many virtual machines can be cloned from the single stored data structure. One benefit of this approach is that a new virtual machine can effectively be created in an already initialized state.

Abstract: Mechanisms and techniques operate in a scalable or non-scalable processing architecture computerized device to execute critical code while overcoming interference from interruptions. A critical signal handler is registered and a non-operating system thread sets a value of a critical code register to indicate a critical execution condition. The non-operating system thread then executes a critical code section until an interruption occurs. In response to the interruption to the critical code section, an operating system thread detects if the critical code register is equivalent to a critical execution condition and if so, sets the value of the critical code register to indicate a critical execution failure. Upon returning to execution of the critical code section, the critical code section attempts to execute a contingent instruction in the critical code section that is contingent upon the value of the critical code register.

Abstract: A REPEAT instruction for repeated execution of an associated instruction (INSTR). Once a program counter stores the address for the instruction to be repeated, it remains unchanged until the associated instruction (INSTR) has been executed the number of times indicated by a COUNT value in a preloaded register, or alternatively, by the REPEAT instruction itself. In this manner, the present invention reduces the number of instruction fetches required to repeatedly execute the associated instruction (INSTR). Consequently, there is a significant improvement in the efficiency of the program code execution.

Abstract: A method of dynamically hooking runtime processes without interrupting the flow of execution includes: suspending a thread; hooking a function comprising modifying code of the function; and determining whether the thread was executing the modified code when the thread was suspended. If the thread was not executing the modified code, the thread is resumed. If the thread was executing the modified code, the context of the thread is changed to redirect the thread to a saved copy of the original prologue. In this manner, unpredictable behavior of the thread is avoided.