Information Storage Or Retrieval Using Nanostructure Patents (Class 977/943)
  • Patent number: 9036289
    Abstract: A magnetic storage medium is formed of magnetic nanoparticles that are encapsulated within nanotubes (e.g., carbon nanotubes).
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: May 19, 2015
    Assignee: Sigma Pro Ltd. LLC
    Inventor: Tyson York Winarski
  • Patent number: 9029936
    Abstract: A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Purayath, George Samachisa, George Matamis, James Kai, Yuan Zhang
  • Patent number: 9029248
    Abstract: A nano-ionic memory device is provided. The memory device includes a substrate, a chemically inactive lower electrode provided on the substrate, a solid electrolyte layer provided on the lower electrode and including a silver (Ag)-doped telluride (Te)-based nano-material, and an oxidizable upper electrode provided on the electrolyte layer.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: May 12, 2015
    Assignee: EWHA University-Industry Collaboration Foundation
    Inventors: William Jo, Ah-Reum Jeong
  • Patent number: 9006712
    Abstract: The invention relates to an organic memory with an electrode and a counter-electrode, comprising at least one oxide layer, an electrically undoped organic layer and an electrically doped organic layer between the electrode and the counter-electrode, wherein the oxide layer is adjacent to the electrode and the undoped organic layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: April 14, 2015
    Assignee: Novaled AG
    Inventors: Philipp Sebastian, Bjoern Luessem, Karl Leo
  • Patent number: 9006810
    Abstract: A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Jeffrey W. Sleight
  • Publication number: 20150098153
    Abstract: A disk drive includes a disk including a magnetizable layer of material, and a transducer. The transducer has a read element that includes a first shield layer, a pinned layer, a metallic spacer, an AP (anti-parallel) free layer, and a second shield layer. The pinned layer has a surface area which is greater than the area of the AP free layer. The read element also includes an anti-ferromagnetic layer for substantially fixing the magnetic orientation of a plurality of domains in the pinned layer. The ferromagnetic layer is adjacent the pinned layer. The pinned layer, and the anti-ferromagnetic layer both have surface areas which are greater than the area associated with the AP free layer. The anti-ferromagnetic layer, in one embodiment, has a pinning strength in the range of 0.5 erg/cm2 to 1.5 erg/cm2.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: HGST Netherlands B.V.
    Inventors: Matthew Joseph CAREY, Jeffrey Robinson CHILDRESS, Young-suk CHOI, Goran MIHAJLOVIC, John Creighton READ, Neil SMITH
  • Publication number: 20150069133
    Abstract: Chipless RFID tags (200, 210, 220, 230, 240, 250, 260, 310, 320, 330, 400, 410, 420, 500, 510, 520, 600, 610, and 620) are designed and fabricated from the structures of the nanotube elements and their patterns on a dielectric substrate (202, 311, 401, and 501 etc.) by thin film coating or printing following by a polymer curing process.
    Type: Application
    Filed: September 9, 2013
    Publication date: March 12, 2015
    Inventor: ZHENGFANG QIAN
  • Patent number: 8958241
    Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; first insulating layers provided on a first surface of the magnetic nanowire, each of the first insulating layers having a first and second end faces, a thickness of the first insulating layer over the first end face being thicker than a thickness of the first insulating layer over the second end face; first electrodes on surfaces of the first insulating layers opposite to the first surface; second insulating layers on the second surface of the magnetic nanowire, each of the second insulating layers having a third and fourth end faces, a thickness of the second insulating layer over the third surface being thicker than a thickness of the second insulating layer over the fourth end face; and second electrodes on surfaces of the second insulating layers.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Kondo, Hirofumi Morise, Shiho Nakamura, Takuya Shimada, Yoshiaki Fukuzumi, Hideaki Aochi
  • Publication number: 20140376353
    Abstract: A device including a magnetic structure, the magnetic structure having a substrate adjacent surface and a second, opposing surface, the magnetic structure having a near field transducer (NFT), wherein the NFT includes gold or an alloy thereof, and is positioned at the second surface an overcoat structure; and a film structure, the film structure positioned between the magnetic structure and the overcoat structure, the film structure having a total thickness of not greater than about 100 ?, and the film structure including: a first interfacial structure having a first and a second opposing surface; a second interfacial structure having a first and a second opposing surface; and an intermediate structure wherein the first surface of the first interfacial structure is positioned adjacent the NFT of the magnetic structure, and the second surface of the second interfacial structure is positioned adjacent the overcoat structure, and the intermediate structure is positioned between the first interfacial structure an
    Type: Application
    Filed: August 26, 2014
    Publication date: December 25, 2014
    Inventors: Philip G. Pitcher, Sami C. Antrazi
  • Patent number: 8916845
    Abstract: Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: December 23, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Yi-Chou Chen
  • Publication number: 20140340788
    Abstract: A magnetic storage medium is formed of magnetic nanoparticles that are encapsulated within nanotubes (e.g., carbon nanotubes).
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventor: Tyson York Winarski
  • Patent number: 8866139
    Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer; a charge storage film that is formed on the first insulating film, includes C60 fullerenes, and is not less than 0.5 monolayer but is less than 1.0 monolayer; a second insulating film formed on the charge storage film; and a control electrode formed on the second insulating film.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: October 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsunehiro Ino
  • Publication number: 20140293687
    Abstract: A semiconductor device may include a substrate, and an array of PCM memory cells above the substrate. Each PCM memory cell may include first and second vertically aligned electrodes, a first dielectric layer between the first and second electrodes, a carbon nanotube extending vertically through the first dielectric layer from the second electrode and toward the first electrode, and a PCM body between the first electrode and the at least one carbon nanotube.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 2, 2014
    Applicant: STMICROELECTRONICS, INC.
    Inventor: John H. ZHANG
  • Publication number: 20140252447
    Abstract: A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: SANDISK TECHNOLOGIES, INC.
    Inventors: Donovan Lee, James K. Kai, George Samachisa, Henry Chien, George Matamis, Vinod R. Purayath
  • Patent number: 8823118
    Abstract: A STT-RAM MTJ is disclosed with a composite tunnel barrier comprised of a CoMgO layer that contacts a pinned layer and a MgO layer which contacts a free layer. A CoMg layer with a Co content between 20 and 40 atomic % is deposited on the pinned layer and is then oxidized to produce Co nanoconstrictions within a MgO insulator matrix. The nanoconstrictions control electromigration of Co into an adjoining MgO layer. The free layer may comprise a nanocurrent channel (NCC) layer such as FeSiO or a moment dilution layer such as Ta between two ferromagnetic layers. Furthermore, a second CoMgO layer or a CoMgO/MgO composite may serve as a perpendicular Hk enhancing layer formed between the free layer and a cap layer. One or both of the pinned layer and free layer may exhibit in-plane anisotropy or perpendicular magnetic anisotropy.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: September 2, 2014
    Assignee: Headway Technologies, Inc.
    Inventors: Cheng T Horng, Ru-Ying Tong
  • Publication number: 20140241052
    Abstract: A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 28, 2014
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Keith W. Golke, David K. Nelson
  • Publication number: 20140204647
    Abstract: A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire.
    Type: Application
    Filed: January 21, 2013
    Publication date: July 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Anthony J. Annunziata
  • Patent number: 8780601
    Abstract: A three-dimensional integrated circuit comprising a submicroscale integrated-circuit substrate and n nanoscale layers stacked above the submicroscale integrated-circuit substrate, a nanowire-junction memory element in each of which is independently controlled by two submicroscale subcomponents within the submicroscale integrated-circuit substrate, the first submicroscale subcomponent coupled through a first set of switches to each of the n nanowire-junction memory elements and the second submicroscale subcomponent coupled through a second set of switches to each of the n nanowire-junction memory elements, the total number of switches in the first and second sets of switches less than 2n, and n greater than or equal to 2.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: July 15, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Gregory Stuart Snider
  • Publication number: 20140191183
    Abstract: A resistive random access memory includes a first electrode, a second electrode and a first metal oxide composite layer. The second electrode is opposite to the first electrode. The first metal oxide composite layer is disposed between the first electrode and the second electrode. The first metal oxide composite layer has a film layer and a nanorod structure.
    Type: Application
    Filed: January 8, 2014
    Publication date: July 10, 2014
    Applicant: National Tsing Hua University
    Inventors: Yu-Lun CHUEH, Chi-Hsin HUANG
  • Publication number: 20140185371
    Abstract: An atomic-scale structure according to one embodiment has a net magnetic moment of zero or about zero, two or more stable magnetic states, and an array of atoms that has magnetic moments that alternate between adjacent magnetic atoms along one or more directions. Such structures may be used to store data at ultra-high densities. An antiferromagnetic nanostructure according to another embodiment includes multiple arrays each corresponding to a bit. Each array has at least eight antiferromagnetically coupled magnetic atoms. Each array has at least two readable magnetic states that are stable for at least one picosecond. Each array has a net magnetic moment of zero or about zero. No external stabilizing structure exerts influence over the arrays for stabilizing the arrays. Each array has 100 atoms or less along a longest dimension thereof.
    Type: Application
    Filed: March 4, 2014
    Publication date: July 3, 2014
    Applicant: International Business Machines Corporation
    Inventors: Donald M. Eigler, Andreas J. Heinrich, Sebastian Loth, Christopher P. Lutz
  • Patent number: 8759810
    Abstract: A phase change memory device that utilizes a nanowire structure. Usage of the nanowire structure permits the phase change memory device to release its stress upon amorphization via the minimization of reset resistance and threshold resistance.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 24, 2014
    Assignee: The Trustees Of The University Of Pennsylvania
    Inventors: Ritesh Agarwal, Mukut Mitra, Yeonwoong Jung
  • Patent number: 8753743
    Abstract: The invention relates to a material composed of nanoparticles essentially comprising a spin transition compound. The compound corresponds to the formula [ ( Fe 1 - y ? M y ? L 3 ) w ? L 3 ] [ X 2 x ? ( 1 - z x ? ) ? Y 2 ? ? z x ? ] w in which L represents a 1,2,4-triazole ligand carrying an R substituent on the nitrogen in the 4 position; X is an anion having the valency x, 1?x?2; Y is an anion other than X having the valency x?, 1?x??2; R is an alkyl group or an R1R2N— group in which R1 and R2 represent, each independently of the other, H or an alkyl radical; M is a metal having a 3d4, 3d5, 3d6 or 3d7 configuration, other than Fe; 0?y?1; 0?z?2; 3?w?1500. Applications: thermochromic pigment, data storage, optical limiters, contrast agent.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 17, 2014
    Assignee: Centre National de la Recherche Scientifique
    Inventors: Jean-Francois Letard, Olivier Nguyen, Nathalie Daro
  • Patent number: 8748968
    Abstract: Provided are a method of forming nano dots, method of fabricating a memory device including the same, charge trap layer including the nano dots and memory device including the same. The method of forming the nano dots may include forming cores, coating surfaces of the cores with a polymer, and forming graphene layers covering the surfaces of the cores by thermally treating the cores coated with the polymer. Also, the cores may be removed after forming the graphene layers. In addition, the surfaces of the cores may be coated with a graphitization catalyst material before coating the cores with the polymer. Also, the cores may include metal particles that trap charges and may also function as a graphitization catalyst.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-young Choi, Hyeon-jin Shin, Seon-mi Yoon
  • Publication number: 20140146414
    Abstract: A magnetic storage medium is formed of magnetic nanoparticles that are encapsulated within nanotubes (e.g., carbon nanotubes), which are arranged in a substrate to facilitate the reading and writing of information by a read/write head. The substrate may be flexible or rigid. Information is stored on the magnetic nanoparticles via the read/write head of a storage device. These magnetic nanoparticles are arranged into data tracks to store information through encapsulation within the carbon nanotubes. As carbon nanotubes are bendable, the carbon nanotubes may be arranged on flexible or rigid substrates, such as a polymer tape or disk for flexible media, or a glass substrate for rigid disk. A polymer may assist holding the nanoparticle-filled carbon tubes to the substrate.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Applicant: Sigma Pro Ltd. LLC
    Inventor: Tyson York Winarski
  • Publication number: 20140138610
    Abstract: A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicant: International Business Machines Corporation
    Inventors: Michael C. Gaidis, Alexander J. Gaidis
  • Publication number: 20140119111
    Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; a first electrode and a second electrode provided to different locations of the magnetic nanowire; a third electrode including a magnetic layer, the third electrode being provided to a location of the magnetic nanowire between the first electrode and the second electrode; an intermediate layer provided between the magnetic nanowire and the third electrode, the intermediate layer being in contact with the magnetic nanowire and the third electrode; a fourth electrode of a nonmagnetic material provided onto the magnetic nanowire and being on the opposite side of the magnetic wire from the third electrode; and an insulating layer provided between the magnetic nanowire and the fourth electrode, the insulating layer being in contact with the magnetic nanowire and the fourth electrode.
    Type: Application
    Filed: October 2, 2013
    Publication date: May 1, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shiho Nakamura, Tsuyoshi Kondo, Hirofumi Morise, Takuya Shimada
  • Publication number: 20140112115
    Abstract: Three structures, and processes for manufacturing them, that improve the performance of a TAMR feature in a magnetic write head are disclosed. This improvement is achieved by making the separation between the edge plasmon generator and the plasmon shield less than the separation between the edge plasmon generator and the optical wave-guide.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventors: Xuhui Jin, Hiroyuki Ito, Shigeki Tanemura, Dayu Zhou
  • Publication number: 20140104941
    Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; first insulating layers provided on a first surface of the magnetic nanowire, each of the first insulating layers having a first and second end faces, a thickness of the first insulating layer over the first end face being thicker than a thickness of the first insulating layer over the second end face; first electrodes on surfaces of the first insulating layers opposite to the first surface; second insulating layers on the second surface of the magnetic nanowire, each of the second insulating layers having a third and fourth end faces, a thickness of the second insulating layer over the third surface being thicker than a thickness of the second insulating layer over the fourth end face; and second electrodes on surfaces of the second insulating layers.
    Type: Application
    Filed: September 9, 2013
    Publication date: April 17, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi KONDO, Hirofumi MORISE, Shiho NAKAMURA, Takuya SHIMADA, Yoshiaki FUKUZUMI, Hideaki AOCHI
  • Patent number: 8699268
    Abstract: Field effect devices having a drain controlled via a nanotube switching element. Under one embodiment, a field effect device includes a source region and a drain region of a first semiconductor type and a channel region disposed therebetween of a second semiconductor type. The source region is connected to a corresponding terminal. A gate structure is disposed over the channel region and connected to a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the drain region and a terminal corresponding to the drain region. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the drain region and its corresponding terminal.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: April 15, 2014
    Assignee: Nantero Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
  • Patent number: 8693242
    Abstract: A nanoelectromechanical device is provided. The nanoelectromechanical device includes a nanotube, a first contact, and a first actuator. The nanotube includes a first end, the first end supported by a first structure, a second end opposite the first end, and a first portion. The first actuator is configured to apply a first force to the nanotube, the first force causing the nanotube to buckle such that the first portion couples to the first contact.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 8, 2014
    Assignee: Elwha LLC
    Inventors: Howard L. Davidson, Roderick A. Hyde, Jordin T. Kare, Richard T. Lord, Robert W. Lord, Nathan P. Myhrvold, Clarence T. Tegreene, Charles Whitmer, Lowell L. Wood, Jr.
  • Publication number: 20140091274
    Abstract: In one embodiment, a memory device includes a first electrode layer on a substrate; a data storing layer on the first electrode layer; and a second electrode layer on the data storing layer. At least one of the first and second electrode layers may be formed of a material having a conduction band offset that varies with an applied voltage. One of the first and second electrode layers may be connected to a bit line and the other may be connected to a word line. The first electrode layer may include one of graphene and metastable oxide. The second electrode layer may include one of graphene and metastable oxide.
    Type: Application
    Filed: July 15, 2013
    Publication date: April 3, 2014
    Inventors: Young-bae KIM, Kyung-min KIM, In-gyu BAEK, Seong-jun PARK
  • Patent number: 8687402
    Abstract: A non-volatile solid state resistive device that includes a first electrode, a p-type poly-silicon second electrode, and a non-crystalline silicon nanostructure electrically connected between the electrodes. The nanostructure has a resistance that is adjustable in response to a voltage being applied to the nanostructure via the electrodes. The nanostructure can be formed as a nanopillar embedded in an insulating layer located between the electrodes. The first electrode can be a silver or other electrically conductive metal electrode. A third (metal) electrode can be connected to the p-type poly-silicon second electrode at a location adjacent the nanostructure to permit connection of the two metal electrodes to other circuitry. The resistive device can be used as a unit memory cell of a digital non-volatile memory device to store one or more bits of digital data by varying its resistance between two or more values.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: April 1, 2014
    Assignee: The Regents of The University of Michigan
    Inventors: Wei Lu, Sung Hyun Jo, Kuk-Hwan Kim
  • Patent number: 8680503
    Abstract: Methods of forming a microelectronic structure are provided, the microelectronic structure including a first conductor, a discontinuous film of metal nanoparticles disposed on a surface above the first conductor, a carbon nano-film formed atop the surface and the discontinuous film of metal nanoparticles, and a second conductor disposed above the carbon nano-film. Numerous additional aspects are provided.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: March 25, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Yubao Li, April D. Schricker
  • Publication number: 20140063893
    Abstract: A shift register type magnetic memory according to an embodiment includes: a magnetic nanowire; a magnetic material chain provided in close vicinity to the magnetic nanowire, the magnetic material chain including a plurality of disk-shaped ferromagnetic films arranged along a direction in which the magnetic nanowire extends; a magnetization rotation drive unit configured to rotate and drive magnetization of the plurality of ferromagnetic films; a writing unit configured to write magnetic information into the magnetic nanowire; and a reading unit configured to read magnetic information from the magnetic nanowire.
    Type: Application
    Filed: January 25, 2013
    Publication date: March 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi
  • Publication number: 20140029332
    Abstract: Hydro-carbon nanorings may be used in storage. Sufficiently cooled, an externally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of electrons. Similarly, an internally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of positrons. When matched streams of positrons and electrons are sufficiently compressed they may form Cooper pairs with magnetic moments aligned to the movement of the stream. Matched adjacent Cooper pairs of electrons and positrons may contain information within their magnetic moments, and as such, may transmit and store information with little or no energy loss.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Inventor: Laurence H. COOKE
  • Patent number: 8631562
    Abstract: An electrostatic discharge (ESD) protection circuit for protecting a protected circuit is coupled to an input pad. The ESD circuit includes a nanotube switch electrically having a control. The switch is coupled to the protected circuit and to a discharge path. The nanotube switch is controllable, in response to electrical stimulation of the control, between a de-activated state and an activated state. The activated state creates a current path so that a signal on the input pad flows to the discharge path to cause the signal at the input pad to remain within a predefined operable range for the protected circuit. The nanotube switch, the input pad, and the protected circuit may be on a semiconductor chip. The nanotube switch may be on a chip carrier. The deactivated and activated states may be volatile or non-volatile depending on the embodiment.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: January 21, 2014
    Assignee: Nantero Inc.
    Inventors: Claude L. Bertin, Brent M. Segal, Thomas Rueckes, Jonathan W. Ward
  • Publication number: 20140003118
    Abstract: A magnetic domain wall shift register memory device includes a nanowire and a magnetic reference layer island disposed on the nanowire, wherein an interface between the nanowire and the magnetic tunnel junction island is a magnetic tunnel junction aligned with a width of the nanowire.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Michael C. Gaidis
  • Publication number: 20140003117
    Abstract: A magnetic domain wall shift register memory device includes a nanowire, a plurality of pinning sites disposed along the nanowire and a control line arranged substantially parallel to the nanowire and configured to support a current.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Michael C. Gaidis
  • Publication number: 20140004625
    Abstract: A method of fabricating a self-aligning magnetic tunnel junction the method includes patterning a lithographic strip on a second magnetic material deposited on a first magnetic material that is disposed on a substrate, forming a top magnetic strip by etching an exposed portion of the second magnetic material, patterning a nanowire and a magnetic reference layer island over the substrate and forming the nanowire and the magnetic reference layer island by etching an exposed portion of the first magnetic layer and an exposed portion of the top magnetic strip, wherein an interface between the magnetic nanowire and the magnetic reference layer island is an magnetic tunnel junction aligned with a width of the nanowire.
    Type: Application
    Filed: July 23, 2012
    Publication date: January 2, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Michael C. Gaidis
  • Patent number: 8611137
    Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: December 17, 2013
    Assignee: Altera Corporation
    Inventors: Lin-Shih Liu, Mark T. Chan, Yanzhong Xu, Irfan Rahim, Jeffrey T. Watt
  • Patent number: 8611134
    Abstract: Embodiments of the present invention are directed systems and methods for reading the resistance states of crossbar junctions of a crossbar array. In one aspect, a system includes one or more sense amplifiers connected to column wires of the crossbar array, a reference row wire connected to each sense amp, and a wire driver connected to the reference row wire and configured to drive the reference row wire. The sense amplifiers are configured so that when a selected row wire of the crossbar array is driven by a sense voltage, the column wires are held at approximately zero volts and pass currents through the column wires and sense amplifiers to the reference row wire so that resistive voltage losses along the reference row wire substantially mirror the resistive voltage losses along the selected row wire, allowing the sense amplifiers to determine the crossbar junction resistance states.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: December 17, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Richard J. Carter
  • Publication number: 20130330891
    Abstract: A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
    Type: Application
    Filed: February 22, 2013
    Publication date: December 12, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Jeffrey W. Sleight
  • Patent number: 8587989
    Abstract: NRAM arrays with nanotube blocks, traces and planes, and methods of making the same are disclosed. In some embodiments, a nanotube memory array includes a nanotube fabric layer disposed in electrical communication with first and second conductor layers. A memory operation circuit including a circuit for generating and applying a select signal on first and second conductor layers to induce a change in the resistance of the nanotube fabric layer between the first and second conductor layers is provided. At least two adjacent memory cells are formed in at least two selected cross sections of the nanotube fabric and conductor layers such that each memory cell is uniquely addressable and programmable. For each cell, a change in resistance corresponds to a change in an informational state of the memory cell. Some embodiments include bit lines, word lines, and reference lines. In some embodiments, 6F2 memory cell density is achieved.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: November 19, 2013
    Assignee: Nantero Inc.
    Inventors: H. Montgomery Manning, Thomas Rueckes, Claude L. Bertin, Jonathan W. Ward, Garo Derderian
  • Patent number: 8580586
    Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: November 12, 2013
    Assignee: Nantero Inc.
    Inventors: Claude L. Bertin, Frank Guo, Thomas Rueckes, Steven L. Konsek, Mitchell Meinhold, Max Strasburg, Ramesh Sivarajan, X. M. Henry Huang
  • Publication number: 20130294180
    Abstract: A memory system is disclosed. The system comprises a memory layer between a first layer and a second layer, wherein the first layer and the second layer are configured to apply an electrical bias to the memory layer. In some embodiments the memory layer comprises nanodots made of a material selected from the group consisting of peptides and amino acids.
    Type: Application
    Filed: January 12, 2012
    Publication date: November 7, 2013
    Applicant: Ramot at Tel-Avlv University Ltd.
    Inventors: Simon Litsyn, Gil Rosenman
  • Patent number: 8546863
    Abstract: A memory cell, the memory cell comprising a substrate, a nanowire extending along a vertical trench formed in the substrate, a control gate surrounding the nanowire, and a charge storage structure formed between the control gate and the nanowire.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: October 1, 2013
    Assignee: NXP B.V.
    Inventors: Almudena Huerta, Michiel Jos Van Duuren, Nader Akil, Dusan Golubovic, Mohamed Boutchich
  • Patent number: 8536015
    Abstract: In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: September 17, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Alper Ilkbahar, April D. Schricker
  • Publication number: 20130234130
    Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer; a charge storage film that is formed on the first insulating film, includes C60 fullerenes, and is not less than 0.5 monolayer but is less than 1.0 monolayer; a second insulating film formed on the charge storage film; and a control electrode formed on the second insulating film.
    Type: Application
    Filed: December 26, 2012
    Publication date: September 12, 2013
    Inventor: Tsunehiro INO
  • Publication number: 20130223166
    Abstract: Memory technology adapted to store data in a binary format. Such technology includes a semiconductor memory device having memory cells, each having a substrate and at least three graphene layers that are oriented to define a graphene stack disposed in a plane. The graphene stack of each memory cell is connected to a bit line and to a ground connection so that a conductive path is defined in the plane of the graphene stack.
    Type: Application
    Filed: February 25, 2013
    Publication date: August 29, 2013
    Applicant: OCZ TECHNOLOGY GROUP INC.
    Inventor: OCZ Technology Group Inc.
  • Patent number: 8520430
    Abstract: A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy Cohen, Amlan Majumdar, Jeffrey W. Sleight