Information Storage Or Retrieval Using Nanostructure Patents (Class 977/943)
  • Patent number: 8507888
    Abstract: According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: August 13, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Aoyama, Kazuhiko Yamamoto, Satoshi Ishikawa, Shigeto Oshino
  • Publication number: 20130200327
    Abstract: According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided.
    Type: Application
    Filed: January 21, 2013
    Publication date: August 8, 2013
    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventor: Agency for Science, Technology and Research
  • Publication number: 20130187116
    Abstract: Disclosed herein is an RRAM device with free-forming conductive filament(s), and various methods of making such an RRAM device. In one example, a device disclosed herein includes a first electrode, a second electrode positioned above the first electrode and a variable resistance material positioned between the first and second electrodes, wherein the variable resistance material is a metal oxide with a plurality of metal nano-crystals embedded therein.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE LTD
    Inventors: Shyue Seng Tan, Wei Zhu, Tu Pei Chen
  • Publication number: 20130175644
    Abstract: A STT-RAM MTJ is disclosed with a composite tunnel barrier comprised of a CoMgO layer that contacts a pinned layer and a MgO layer which contacts a free layer. A CoMg layer with a Co content between 20 and 40 atomic % is deposited on the pinned layer and is then oxidized to produce Co nanoconstrictions within a MgO insulator matrix. The nanoconstrictions control electromigration of Co into an adjoining MgO layer. The free layer may comprise a nanocurrent channel (NCC) layer such as FeSiO or a moment dilution layer such as Ta between two ferromagnetic layers. Furthermore, a second CoMgO layer or a CoMgO/MgO composite may serve as a perpendicular Hk enhancing layer formed between the free layer and a cap layer. One or both of the pinned layer and free layer may exhibit in-plane anisotropy or perpendicular magnetic anisotropy.
    Type: Application
    Filed: January 5, 2012
    Publication date: July 11, 2013
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventors: Cheng T. Horng, Ru-Ying Tong
  • Publication number: 20130168632
    Abstract: A resistance variable memory device includes: a first electrode; a second electrode; a resistance variable layer interposed between the first electrode and the second electrode; and nano particles that are disposed in the resistance variable layer and have a lower dielectric constant than the resistance variable layer.
    Type: Application
    Filed: August 28, 2012
    Publication date: July 4, 2013
    Inventors: Ji-Won MOON, Moon-Sig JOO, Sung-Hoon LEE, Jung-Nam Kim
  • Patent number: 8472239
    Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
  • Publication number: 20130155829
    Abstract: A recording apparatus characterized in that comprising a firmware configured to execute the following operation: performing a recording operation onto a rewritable optical recording medium with a recording speed selected from one of a plurality of recording speeds for an one-time optical recording medium; wherein the recording layer of the rewritable optical recording medium comprises at least four elements from Ge, In, Sb, Te, and Sn, wherein the component proportion of Sb/Te is ranged from 3 to 8, and the thickness of the recording layer is ranged from 3 nm to 25 nm.
    Type: Application
    Filed: September 12, 2012
    Publication date: June 20, 2013
    Applicant: CMC MAGNETICS CORPORATION
    Inventors: Yung-Hui HUNG, Cheng-Pi LEE, Kun-Ling LI, Min-Hao PAN
  • Patent number: 8465855
    Abstract: Encapsulated particles and methods for manufacturing encapsulated particles and structures are described. Such particles may have a length no greater than 40 nm, and include at least one material selected from the group consisting of ferromagnetic materials and ferrimagnetic materials. A polymeric encapsulant surrounds the particle, the polymeric encapsulant including a phase-separated block copolymer including a glassy first phase and a rubbery second phase, the glassy first phase positioned between the particle and the second rubbery phase. The glassy first phase includes a hydrophobic copolymer having a glass transition temperature of at least 50° C. The rubbery second phase includes a polymer having at least one of (i) a glass transition temperature of no greater than 30° C., and (ii) a tan delta peak maximum of no greater than 30° C. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: June 18, 2013
    Assignees: International Business Machines Corporation, Arizona Board of Regents on Behalf The University of Arizona
    Inventors: Richard Lionel Bradshaw, Dong-Chul Pyun
  • Publication number: 20130140268
    Abstract: A TAMR (Thermally Assisted Magnetic Recording) write head is formed with a narrow pole tip, a trailing edge magnetic shield and, optionally, a plasmon shield. The narrow pole tipped write head uses the energy of laser generated edge plasmons, formed in a plasmon generating layer, to locally heat a PMR magnetic recording medium slightly below its Curie temperature, Tc. When combined with the effects of the narrow tip, this local heating to a temperature below Tc is sufficient to create good transitions and narrow track widths in the magnetic medium. The write head is capable of writing effectively on state-of-the-art PMR recording media having Hk of 20 kOe or more.
    Type: Application
    Filed: February 4, 2013
    Publication date: June 6, 2013
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventor: HEADWAY TECHNOLOGIES, INC.
  • Publication number: 20130128391
    Abstract: A magneto-resistance effect element, including: a fixed magnetization layer of which a magnetization is substantially fixed in one direction; a free magnetization layer of which a magnetization is rotated in accordance with an external magnetic field and which is formed opposite to the fixed magnetization layer; a spacer layer including a current confining layer with an insulating layer and a conductor to pass a current through the insulating layer in a thickness direction thereof and which is located between the fixed magnetization layer and the free magnetization layer; a thin film layer which is located in a side opposite to the spacer layer relative to the free magnetization layer; and a functional layer containing at least one element selected from the group consisting of Si, Mg, B, Al which is formed in or on at least one of the fixed magnetization layer, the free magnetization layer and the thin film layer.
    Type: Application
    Filed: January 14, 2013
    Publication date: May 23, 2013
    Applicants: TDK CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventors: KABUSHIKI KAISHA TOSHIBA, TDK CORPORATION
  • Patent number: 8446779
    Abstract: A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: May 21, 2013
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Elgin Quek, Chunshan Yin, Shyue Seng Tan, Jae Gon Lee, Chung Foong Tan
  • Patent number: 8445884
    Abstract: A memristor having an active region includes a first electrode. The first electrode comprises a nanostructure formed of at least one metallic single walled nanotube. The memristor also includes a second electrode formed of at least one metallic single walled nanotube. The second electrode is positioned in a crossed relationship with respect to the first electrode. The memristor further includes a switching material positioned between the first electrode and the second electrode, in which the active region is configured to form in the switching material at a cross point of the first electrode and the second electrode.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: May 21, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Qiangfei Xia, Jing Tang
  • Publication number: 20130120869
    Abstract: In one embodiment, a magnetic head includes a main pole configured to produce a magnetic writing field applied to a magnetic medium at an overall angle with respect to a magnetic anisotropy axis which is oriented in a direction perpendicular to a plane of a surface of the magnetic medium, and at least one current carrying element positioned near a media facing surface of the main pole configured to produce an assisting magnetic field applied in a cross-track direction parallel to the plane of the surface of the magnetic medium. In another embodiment, a method includes applying a writing magnetic field to write data to a magnetic medium and applying an assisting magnetic field to the magnetic medium for assisting the writing magnetic field, the assisting magnetic field being applied in a cross-track direction of the magnetic medium and parallel to a plane of a surface of the magnetic medium.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 16, 2013
    Inventors: Sarbanoo Das, Masafumi Mochizuki
  • Patent number: 8434221
    Abstract: The present invention discloses a method for generating nano patterns upon material surfaces. The method for generating nano patterns upon material surfaces comprises the following steps: providing a thin film capable of controlling lattice directions, applying a nanoindentation action to the thin film to generate an indentation at a specific position on the thin film. At least one hillock is then generated in a specific direction to generate a pattern and to be applied to a data storage system.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: May 7, 2013
    Assignee: National Chung Cheng University
    Inventors: Yeau-Ren Jeng, Chung-Ming Tan
  • Publication number: 20130107617
    Abstract: A quantum memory component including a quantum dot molecule having first and second quantum dots provided in respective first and second layers separated by a barrier layer; an exciton comprising an electron and hole bound state in said quantum dot molecule, the spin state of said exciton forming a qubit; first and second electrical contacts respectively provided below the first quantum dot and above the second quantum dot; a voltage source to apply an electric field across said quantum dot molecule; a controller to modulate the electric field across the quantum dot molecule, including an information acquiring circuit to acquire information concerning the relationship between fine structure splitting of the exciton and the applied electric field and a timing circuit to allow switching of the exciton from an indirect configuration to a direct configuration at predetermined times derived from the fine structure splitting.
    Type: Application
    Filed: July 30, 2012
    Publication date: May 2, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Niklas Adam Bilbo Skold, Anthony John Bennett, Andrew James Shields
  • Publication number: 20130105881
    Abstract: A non-volatile memory fabrication process includes the formation of a complete memory cell layer stack before isolation region formation. The memory cell layer stack includes an additional place holding control gate layer. After forming the layer stack columns, the additional control gate layer will be incorporated between an overlying control gate layer and underlying intermediate dielectric layer. The additional control gate layer is self-aligned to isolation regions between columns while the overlying control gate layer is etched into lines for contact to the additional control gate layer. In one embodiment, the placeholder control gate layer facilitates a contact point to the overlying control gate layer such that contact between the control gate layers and the charge storage layer is not required for select gate formation.
    Type: Application
    Filed: October 5, 2012
    Publication date: May 2, 2013
    Inventors: James K. Kai, Vinod R. Purayath, George Matamis, Nima Mokhlesi, Cuong Trinh
  • Patent number: 8422273
    Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
  • Patent number: 8422289
    Abstract: A method of producing nanoparticles by using chemical curing. The method includes depositing a metal thin film on a substrate, applying an insulator precursor on a metal thin film, and adding a curing agent and a catalyst to the insulator precursor to perform the chemical curing. The method also includes mixing metal powder and an insulator precursor, applying a mixture on a substrate, and adding a curing agent and a catalyst to the mixture to perform the chemical curing. Since the chemical curing process is used in the method, it is possible to form nanoparticles by using a simple process at low cost while a high temperature process such as thermal curing is not used.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: April 16, 2013
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Young-Ho Kim, Wenguo Dong, Gun-Hong Kim, Jun-Ro Yoon
  • Publication number: 20130082319
    Abstract: According to one embodiment, a memory device includes the following structure. A first double tunnel junction structure includes a first nanocrystal layer that includes first conductive minute particles, and first and second tunnel insulating films arranged to sandwich the first nanocrystal layer. A second double tunnel junction structure includes a second nanocrystal layer that includes second conductive minute particles, and third and fourth tunnel insulating films arranged to sandwich the second nanocrystal layer. A charge storage layer is arranged between the first and second double tunnel junction structures. First and second conductive layers are arranged to sandwich the first double tunnel junction structure, the charge storage layer, and the second double tunnel junction structure. The first conductive minute particles has an average grain size which is different from that of the second conductive minute particles.
    Type: Application
    Filed: March 22, 2012
    Publication date: April 4, 2013
    Inventor: Ryuji OHBA
  • Publication number: 20130075685
    Abstract: In some aspects, a reversible resistance-switching metal-insulator-metal stack is provided that includes a first conducting layer, a carbon nano-tube (“CNT”) material above the first conducting layer, a second conducting layer above the CNT material, and an air gap between the first conducting layer and the CNT material. Numerous other aspects are provided.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Inventors: Yubao Li, Chu-Chen Fu
  • Publication number: 20130056702
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 7, 2013
    Applicant: Intermolecular, Inc.
    Inventors: Yun Wang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik, Tony Chiang
  • Patent number: 8385113
    Abstract: Nanoelectromechanical systems are disclosed that utilize vertically grown or placed nanometer-scale beams. The beams may be configured and arranged for use in a variety of applications, such as batteries, generators, transistors, switching assemblies, and sensors. In some generator applications, nanometer-scale beams may be fixed to a base and grown to a desired height. The beams may produce an electric potential as the beams vibrate, and may provide the electric potential to an electrical contact located at a suitable height above the base. In other embodiments, vertical beams may be grown or placed on side-by-side traces, and an electrical connection may be formed between the side-by-side traces when beams on separate traces vibrate and contact one another.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: February 26, 2013
    Assignee: CJP IP Holdings, Ltd.
    Inventor: Joseph F. Pinkerton
  • Publication number: 20130039115
    Abstract: The field programmable read-only memory device comprises a memory cell having a switching element for storing bit information. The switching element provides a switchable electrical connection between word line and a bit line and comprises a static body and a moveable connecting element. The switchable electrical connection is non-volatile.
    Type: Application
    Filed: July 17, 2012
    Publication date: February 14, 2013
    Inventors: Meinolf Blawat, Holger Kropp
  • Publication number: 20130027808
    Abstract: An aspect of the present invention relates to a magnetic tape comprising a magnetic layer containing a hexagonal ferrite magnetic powder and a binder on a nonmagnetic support, wherein a standard deviation ?Hk of a magnetic anisotropy constant Hk of the magnetic layer is equal to or less than 30%, and a magnetic interaction ?M as calculated by equation (1) below falls within a range of ?0.20??M??0.03: ?M=(Id(H)+2Ir(H)?Ir(?))/Ir(?) . . . (1) wherein Id(H) denotes a residual magnetization measured with DC demagnetization, Ir(H) denotes a residual magnetization measured with AC demagnetization, and Ir(?) denotes a residual magnetization measured at an applied magnetic field of 796 kA/m.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 31, 2013
    Applicant: FUJIFILM CORPORATION
    Inventor: Norihito KASADA
  • Patent number: 8365311
    Abstract: Provided is a highly selective and non-destructive method and apparatus for the measurement of one or more target molecules within a target environment. The apparatus comprises of a modified AFM (atomic force microscope) tip to create a tapered nanoscale co-axial cable, and wherein the application of an alternating potential between the inner and outer electrodes of the co-axial cable creates a dielectrophoretic force for attracting molecules toward the tip-end which is pre-treated with one or more specific ligands.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: January 29, 2013
    Assignee: The Regents of the University of California
    Inventors: Dharmakeerthi Nawarathna, H. Kumar Wickaramsinghe
  • Publication number: 20130008954
    Abstract: The disclosed methods and apparatus relate generally to the electronics media industry, such as cable television (CATV), home shopping services, on-line computer services and computer memory applications. These methods and apparatus allow a user to access and make use of electronic media input and output devices by reference to and/or utilization of standard printed matter, such as magazines, textbooks, or any other printed matter that can be correlated to electronic media.
    Type: Application
    Filed: September 6, 2012
    Publication date: January 10, 2013
    Applicant: MARSHALL FEATURE RECOGNITION, LLC
    Inventors: Spencer A. Rathus, Jeffrey S. Nevid
  • Publication number: 20130011680
    Abstract: The invention relates to a material composed of nanoparticles essentially comprising a spin transition compound. The compound corresponds to the formula [ ( Fe 1 - y ? M y ? L 3 ) w ? L 3 ] [ X 2 x ? ( 1 - z x ? ) ? Y 2 ? ? z x ? ] w in which L represents a 1,2,4-triazole ligand carrying an R substituent on the nitrogen in the 4 position; X is an anion having the valency x, 1?x?2; Y is an anion other than X having the valency x?, 1?x??2; R is an alkyl group or an R1R2N— group in which R1 and R2 represent, each independently of the other, H or an alkyl radical; M is a metal having a 3d4, 3d5, 3d6 or 3d7 configuration, other than Fe; 0?y?1; 0?z?2; 3?w?1500. Applications: thermochromic pigment, data storage, optical limiters, contrast agent.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: Centre National De La Recherche Scientifique
    Inventors: Jean-François LETARD, Olivier NGUYEN, Nathalie DARO
  • Publication number: 20130010521
    Abstract: Embodiments of the present invention are directed systems and methods for reading the resistance states of crossbar junctions of a crossbar array. In one aspect, a system includes one or more sense amplifiers (512-514) connected to column wires of the crossbar array, a reference row wire (516) connected to each sense amp, and a wire driver (518) connected to the reference row wire and configured to drive the reference row wire. The sense amplifiers are configured so that when a selected row wire of the crossbar array is driven by a sense voltage, the column wires are held at approximately zero volts and pass currents through the column wires and sense amplifiers to the reference row wire so that resistive voltage losses along the reference row wire substantially mirror the resistive voltage losses along the selected row wire, allowing the sense amplifiers to determine the crossbar junction resistance states.
    Type: Application
    Filed: March 25, 2010
    Publication date: January 10, 2013
    Inventor: Richard Carter
  • Publication number: 20130006878
    Abstract: Some embodiments of the inventive subject matter are directed to incorporating one or more nanoprocessors to one or more physical structures of one or more components of a product. The product is transportable via a chain of supply. Some embodiments are further directed to configuring the one or more nanoprocessors to store data that describes characteristics of the one or more components, the product, and/or the chain of supply. Some embodiments are further directed configuring the one or more nanoprocessors to transmit one or more signals that contain the data.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: International Business Machines Corporation
    Inventors: Bradford O. Brooks, Alan L. Kohlscheen, Scott W. Pollyea, Srinivas B. Tummalapenta, Hamza Yaswi
  • Publication number: 20130006877
    Abstract: Some embodiments of the inventive subject matter are directed to incorporating a plurality of nanoparticles with a physical structure of an object. The object is transportable via locations associated with a chain of supply. Some embodiments are further directed to writing charges to modifiable portions of the plurality of nanoparticles incorporated with the physical structure of the object. Some embodiments are further directed to configuring the charges on the modifiable portions of the plurality of nanoparticles as data. The data describes one or more characteristics of the object and components of the object. The data is accessible via the locations associated with the chain of supply.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: International Business Machines Corporation
    Inventors: Bradford O. Brooks, Scott W. Pollyea, Srinivas B. Tummalapenta, Hamza Yaswi
  • Publication number: 20120325906
    Abstract: The disclosed methods and apparatus relate generally to the electronics media industry, such as cable television (CATV), home shopping services, on-line computer services and computer memory applications. These methods and apparatus allow a user to access and make use of electronic media input and output devices by reference to and/or utilization of standard printed matter, such as magazines, textbooks, or any other printed matter that can be correlated to electronic media. The methods and apparatus further allow the user to tailor the retrieval of electronic data by using a user profile.
    Type: Application
    Filed: September 6, 2012
    Publication date: December 27, 2012
    Applicant: MARSHALL FEATURE RECOGNITION, LLC
    Inventors: Spencer A. Rathus, Jeffrey S. Nevid
  • Patent number: 8331138
    Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: December 11, 2012
    Assignee: Agate Logic, Inc.
    Inventors: David Richard Trossen, Malcolm John Wing
  • Publication number: 20120308846
    Abstract: A ferromagnetic graphene includes at least one antidot such that the ferromagnetic graphene has ferromagnetic characteristics. A spin valve device includes a ferromagnetic graphene. The ferromagnetic graphene includes a first region, a second region, and a third region. At least one antidot is formed in each of the first region and the third region. The first region and the third region are ferromagnetic regions, whereas the second region is a non-ferromagnetic region.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 6, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sung-Hoon Lee
  • Patent number: 8324940
    Abstract: An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first nanowire, and a first n-type field effect transistor (nFET) device having a gate disposed on the first nanowire.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy Cohen, Amlan Majumdar, Jeffrey W. Sleight
  • Publication number: 20120278650
    Abstract: Methods, apparatus and articles of manufacture for controlling nanostore operation based on monitored performance are disclosed. An example method disclosed herein comprises monitoring performance of a nanostore, the nanostore including compute logic and a datastore accessible via the compute logic, and controlling operation of the nanostore in response to detecting a performance indicator associated with wearout of the compute logic to permit the compute logic to continue to access the datastore.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 1, 2012
    Inventors: Naveen Muralimanohar, Parthasarathy Ranganathan, Jichuan Chang
  • Patent number: 8299520
    Abstract: According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-pil Kim, Yoon-dong Park, Jae-young Choi, June-mo Koo, Byung-hee Hong
  • Publication number: 20120267703
    Abstract: Provided is an information storage medium using nanocrystal particles, a method of manufacturing the information storage medium, and an information storage apparatus including the information storage medium. The information storage medium includes a conductive layer, a first insulating layer formed on the conductive layer, a nanocrystal layer that is formed on the first insulating layer and includes conductive nanocrystal particles that can trap charges, and a second insulating layer formed on the nanocrystal layer.
    Type: Application
    Filed: June 26, 2012
    Publication date: October 25, 2012
    Applicant: Seagate Technology LLC
    Inventors: Seung-bum Hong, Simon Buehlmann, Shin-ae Jun, Sung-hoon Choa, Eun-joo Jang, Yong-kwan Kim
  • Patent number: 8293654
    Abstract: A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: October 23, 2012
    Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry Foundation
    Inventors: Jin-gyoo Yoo, Cheol-soon Kim, Jung-hoon Lee
  • Publication number: 20120262985
    Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with a primary gate and forming a charge storage layer on the substrate over the primary gate. A secondary gate electrode layer is formed on the substrate over the charge storage layer. The charge storage and secondary gate electrode layers are patterned to form first and second secondary gates on first and second sides of the primary gate.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 18, 2012
    Applicant: GLOBALFOUNDRIES SINGAPORE Pte. Ltd.
    Inventors: Ying Qian WANG, Yu CHEN, Swee Tuck WOO, Bangun INDAJANG, Sung Mun JUNG
  • Publication number: 20120263024
    Abstract: A TAMR (Thermal Assisted Magnetic Recording) writer has a narrow pole tip with a trailing edge magnetic shield. The narrow pole tipped write head uses the energy of laser generated edge plasmons, formed in a plasmon generating layer, to locally heat a PMR magnetic recording medium below its Curie temperature, Tc. When combined with the effects of the narrow tip, this local heating to a temperature below Tc is sufficient to create good transitions and narrow track widths in the magnetic medium. The write head is capable of writing effectively on state-of-the-art PMR recording media having Hk of 20 kOe or more.
    Type: Application
    Filed: April 14, 2011
    Publication date: October 18, 2012
    Inventors: Xuhui Jin, Yuchen Zhou, Kenichi Takano, Joe Smyth
  • Patent number: 8288264
    Abstract: A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 16, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Publication number: 20120235122
    Abstract: The invention relates to an organic memory with an electrode and a counter-electrode, comprising at least one oxide layer, an electrically undoped organic layer and an electrically doped organic layer between the electrode and the counter-electrode, wherein the oxide layer is adjacent to the electrode and the undoped organic layer.
    Type: Application
    Filed: October 18, 2011
    Publication date: September 20, 2012
    Applicants: TECHNISCHE UNIVERSITAET DRESDEN, NOVALED AG
    Inventors: Philipp Sebastian, Bjoern Luessem, Karl Leo
  • Patent number: 8270200
    Abstract: A nanoscale three-terminal switching device has a bottom electrode, a top electrode, and a side electrode, each of which may be a nanowire. The top electrode extends at an angle with respect to the bottom electrode and has an end section going over and overlapping the bottom electrode. An active region is disposed between the top electrode and bottom electrode and contains a switching material. The side electrode is disposed opposite from the top electrode and in electrical contact with the active region. A self-aligned fabrication process may be used to automatically align the formation of the top and side electrodes with respect to the bottom electrode.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: September 18, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Wu, Qiangfei Xia, Philip J. Kuekes, R. Stanley Williams
  • Publication number: 20120230128
    Abstract: Some embodiments include switches that have a graphene structure connected to a pair of spaced-apart electrodes. The switches may further include first and second electrically conductive structures on opposing sides of the graphene structure from one another. The first structure may extend from one of the electrodes, and the second structure may extend from the other of the electrodes. Some embodiments include the above-described switches utilized as select devices in memory devices. Some embodiments include methods of selecting memory cells.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 13, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Gurtej S. Sandhu
  • Publication number: 20120223414
    Abstract: In some aspects, a method of forming a reversible resistance-switching metal-insulator-metal (“MIM”) stack is provided, the method including: forming a first conducting layer comprising a titanium nitride material having between about 50% Ti and about 95% Ti, forming a carbon nano-tube (CNT) material above the first conducting layer, forming a second conducting layer above the CNT material, and etching the first conducting layer, CNT material and second conducting layer to form the MIM stack. Numerous other aspects are provided.
    Type: Application
    Filed: August 8, 2011
    Publication date: September 6, 2012
    Inventors: April D. Schricker, Er-Xuan Ping
  • Publication number: 20120217461
    Abstract: A semiconductor memory device according to an embodiment includes: first lines provided on a substrate; second lines provided between the first lines and the substrate so as to intersect the first lines; and a first memory cell array including first memory cells, each of the first memory cells being provided at respective intersections of the first lines and the second lines and including a current rectifying element and a variable resistor connected in series. The variable resistor of the first memory cell includes a first recording layer and a second recording layer, the first recording layer being made of an oxide of a first metal material, the second recording layer being made of the first metal material and being formed so as to contact with the first recording layer. The second recording layer is closer to the first line than the first recording layer is.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 30, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki KOBAYASHI, Takashi Shigeoka, Mitsuru Sato, Takahiro Hirai, Katsuyuki Sekine, Kazuya Kinoshita, Soichi Yamazaki, Ryota Fujitsuka, Kensuke Takahashi, Yasuhiro Nojiri, Masaki Yamato, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Publication number: 20120205607
    Abstract: A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-change nanowires.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Inventor: Tae-Yon LEE
  • Patent number: 8245318
    Abstract: Sidewall tracing nanoprobes, in which the tip shape of the nanoprobe Is altered so that the diameter or width of the very tip of the probe is wider than the diameter of the supporting stem. Such side protruding probe tips are fabricated by a subtractive method of reducing the stem diameter, an additive method of increasing the tip diameter, or sideway bending of the probe tip. These sidewall tracing nanoprobes are useful for inspection of semiconductor devices, especially to quantitatively evaluate the defects on the side wall of trenches or via holes.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: August 14, 2012
    Assignee: The Regents of the University of California
    Inventors: Sungho Jin, Li-Han Chen, Gregory Dahlen, Hao-Chih Liu
  • Patent number: 8233313
    Abstract: A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier. The unit cell receives a plurality of voltage ranges to perform a plurality of operations. A read operation is performed when an input voltage is in a first voltage range. A first write operation is performed when the input voltage is in a second voltage range higher than the first voltage range. A second write operation is performed when the input voltage is in a third voltage range higher than the second voltage range. An erase operation is performed when the input voltage is higher than the third voltage range.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: July 31, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jea-Gun Park, Sung-Ho Seo, Woo-Sik Nam, Young-Hwan Oh, Yool-Guk Kim, Hyun-Min Seung, Jong-Dae Lee
  • Publication number: 20120189872
    Abstract: A perpendicular magnetic disk is provided. The disk includes, on a base and in the order from bottom, a first granular magnetic layer group including a plurality of magnetic layers each having a granular structure, a non-magnetic layer having Ru or a Ru alloy as a main component, a second granular magnetic layer group including a plurality of magnetic layers each having the granular structure, and an auxiliary recording layer having a CoCrPtRu alloy as a main component. Layers closer to a front surface among the plurality of magnetic layers included in the first granular magnetic layer group having an equal or smaller content of Pt. Layers closer to the front surface among the plurality of magnetic layers included in the second granular magnetic layer group having an equal or smaller content of Pt and having an equal or larger content of an oxide.
    Type: Application
    Filed: May 20, 2011
    Publication date: July 26, 2012
    Applicant: WD MEDIA (SINGAPORE) PTE. LTD.
    Inventors: Teiichiro Umezawa, Takenori Kajiwara, Tokichiro Sato