Abstract: A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode.

Abstract: The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls?t?2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics.

Abstract: A trench gate type IGBT includes: a first semiconductor layer; a second semiconductor on the first semiconductor layer; a third semiconductor on the second semiconductor layer; trenches for separating the third semiconductor layer into first regions and second regions; a gate insulation film on an inner wall of each trench; a gate electrode on the gate insulation film; a fourth semiconductor layer in a surface portion of each first region and contacting each trench; a first electrode connecting to the first region and the fourth semiconductor layer; and a second electrode connecting to the first semiconductor layer. The first regions and the second regions are alternately arranged. Two second regions are continuously connected together to be integrated into one body.

Abstract: To provide a semiconductor device that exhibits a high breakdown voltage, excellent thermal properties, a high latch-up withstanding capability and low on-resistance. The semiconductor device according to the invention, which includes a buried insulator region 5 disposed between an n?-type drift layer 3 and a first n-type region 7 above n?-type drift layer 3, facilitates limiting the emitter hole current, preventing latch-up from occurring, raising neither on-resistance nor on-voltage. The semiconductor device according to the invention, which includes a p-type region 4 disposed between the buried insulator region 5 and n?-type drift layer 3, facilitates depleting n?-type drift layer 3 in the OFF-state of the device.

Abstract: To enable driving at a high withstand voltage and a large current, increase latchup immunity, and reduce ON resistance per unit area in an IGBT, a trench constituted by an upper stage trench and a lower stage trench is formed over an entire wafer surface between an n+ emitter region and a p+ collector region, and the trench is filled with a trench-filling insulating film. Thus, a drift region for supporting the withstand voltage is folded in the depth direction of the wafer, thereby lengthening the effective drift length. An emitter-side field plate is buried in the trench-filling insulating film to block a lateral electric field generated on the emitter side of the trench-filling insulating film, and as a result, an electric field generated at a PN junction between an n? drift region and a p base region is reduced.

Abstract: A semiconductor device includes a spaced-channel IGBT and an antiparalell diode that are formed in a same semiconductor substrate. The IGBT includes a base layer and insulated gate trenches by which the base layer is divided into a body region connected to an emitter and a floating region disconnected from the emitter. The IGBT is formed in a cell region of an IGBT region, and the diode is formed in a diode region. A boundary region of the IGBT region is located between the cell region and the diode region. A spacing between adjacent gate trenches in the boundary region is less than a spacing between adjacent gate trenches between which the floating region is located in the cell region.

Abstract: A semiconductor device and/or a method for fabricating a semiconductor device (e.g. fabricating an LIGBT) that may minimize occurrences of latch-up due to increases of hole current. A semiconductor device and/or a method of fabricating a semiconductor device that may prevent and/or eliminate latch-up due to operation of a parasitic thyrister without significantly deteriorating performances of significant parameters considered when fabricating a high voltage power control device.

Abstract: A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions.

Abstract: A semiconductor device and a method of forming the semiconductor device include a substrate and an n drift layer on the substrate with an insulator film placed between them. A trench is provided in a section between a p base region and an n buffer layer on the surface layer of the n drift layer. Moreover, the distance between the bottom of the trench and the insulator film on the substrate is 1 ?m or more and 75% or less than the thickness of the n drift layer. This reduces the ON-state Voltage Drop and enhances the device breakdown voltage and the latch up current in a lateral IGBT or a lateral MOSFET.

Abstract: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing (100) platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing (102) platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming (104) a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating (105) the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.

Abstract: A semiconductor device includes a first layer having a first conductivity type, a second layer having a second conductivity type, a third layer having the second conductivity type, one or more first zones having the first conductivity type and located within the second layer, wherein each one of the one or more first zones is adjacent to the third layer, and one or more second zones having the second conductivity type and located within the second layer, wherein each one of the one or more second zones is adjacent to one or more of the one or more first zones.

Abstract: A p-type collector layer is formed on a reverse side of an n-type high-resistivity first base layer, a p-type second base layer is formed on an obverse side of the first base layer, an emitter layer is formed on the second base layer, gate electrodes are formed inside trenches extending in a direction and intruding through the emitter layer and the second base layer into intermediate depths of the first base layer, with gate insulating films in between, a collector electrode is connected to the collector layer, an emitter electrode is connected to the emitter layer, the first base layer and the second base layer, the emitter layer is composed of first emitter layers extending along the trenches in the direction, and second emitter layers extending in a perpendicular direction for a ladder form interconnection between first emitter layers, and the base contact layer has a higher impurity density than the second base layer, and envelopes the second emitter layers.

Abstract: The semiconductor device of the present invention has a body layer of a P-type impurity region formed on an N? layer of an N-type impurity region. A plurality of trenches is formed through the body layer from the main surface thereof. A gate insulating film and a gate electrode are formed in each trench. A contact layer of a P-type impurity region and an emitter layer of an N-type impurity region are formed on the main surface of the body layer. A plurality of floating ring layers of P-type impurity regions is formed on the main surface of the N? layer, being spaced apart from the body layer. A well layer of an N-type impurity region is formed between the body layer and N? layer in an area contained in the body layer in plane view.

Abstract: A semiconductor device with a field ring in an edge pattern of a semiconductor body with a central cell area and with field plate discharge pattern. The edge pattern exhibits at least one horizontal field plate which is arranged with one end over the field ring and with its other end on insulating layers towards the edge of the semiconductor body. A first ring-shaped area of a type of conduction doped complementary to a drift section material exhibits a field ring effect. A second highly doped ring-shaped area which contacts the one end of the horizontal field plate and forms a pn junction with the first ring-shaped area and which is arranged within the first area exhibits a locally limited punch-through effect or a resistive contact to the drift section material.

Abstract: An insulated gate bipolar transistor includes a first main electrode on a first main surface and in contact with a base region of an insulated gate transistor at the first main surface, a first semiconductor layer of a first conductivity type on a second main surface, a second semiconductor layer of a second conductivity type on the second main surface and vertically aligned with a region of the first main electrode in contact with the base region, and a second main electrode formed on the first and second semiconductor layers. An interface between the second main electrode and each of the first and second semiconductor layers is parallel to the first main surface, a distance between the first main surface and the interface is equal to 200 ?m or smaller, and a thickness of each of the first and second semiconductor layers is equal to 2 ?m or smaller.

Abstract: A semiconductor component comprising a monocrystalline semiconductor body, and to a method for producing the same is disclosed. In one embodiment, the semiconductor body has a semiconductor component structure with regions of a porous-mono crystalline semiconductor.

Abstract: A method for manufacturing a trench type power semiconductor device is provided. The method includes: forming a first silicon oxide film on a silicon substrate; forming a thermal oxidation-resistant film on the first silicon oxide film; forming an opening in the first silicon oxide film and the thermal oxidation-resistant film; forming a sidewall on an inner side surface of the opening; forming a trench in the silicon substrate by etching the silicon substrate using the first silicon oxide film, the thermal oxidation-resistant film, and the sidewall as a mask; removing the sidewall; forming a second silicon oxide film thicker than the first silicon oxide film on an inner surface of the trench by applying thermal oxidation to the silicon substrate; burying a trench gate electrode in the trench; removing the thermal oxidation-resistant film; and introducing impurities into at least part of a region of the silicon substrate between the trenches.

Abstract: A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N? doped, P? doped, and P+ doped semiconductor layers, the P? and P+ doped layers having a combined thickness of about 5 ?m to about 12 ?m. Recombination centers comprising noble metal impurities are disposed substantially in the N? and P? doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N? doped epitaxial layer on an N+ doped substrate, forming a P? doped layer in the N? doped epitaxial layer, forming a P+ doped layer in the P? doped layer, and forming in the P? and N? doped layers recombination centers comprising noble metal impurities. The P+ and P?doped layers have a combined thickness of about 5 ?m to about 12 ?m.

Abstract: An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate; a semiconductor layer having a P? type active region that is formed on the supporting substrate, interposing a buried oxide film between the semiconductor layer and the supporting substrate; and a gate electrode that is formed on the semiconductor layer, interposing a gate oxide film and a part of a LOCOS film between the gate electrode and the semiconductor layer, wherein the P? type active region has: an N+ type source region; a P type body region; a P+ type back gate contact region; an N type drain offset region; an N+ type drain contact region; and an N type drain buffer region that is formed in a limited region between the N type drain offset region and the P type body region, and the N type drain buffer region is in contact with a source sid

Abstract: A drift diffusion layer of a low concentration is formed so as to surround a collector buffer layer having a relatively high concentration including a high-concentration collector diffusion layer in a plane structure. Thereby, current crowding in corner portions of the high-concentration collector diffusion layer is suppressed while maintaining a short turnoff time, and the improvement of breakdown voltage at on-time is realized.

Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region is is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: A second impurity region is surrounded by a first impurity region at a first main surface. A third impurity region of the first main surface sandwiches the second impurity region with the first impurity region. Fourth and fifth impurity regions of a second main surface sandwich the first impurity region with the second impurity region. A control electrode layer is opposite to the second impurity region with an insulating film interposed. That portion of the second main surface which is opposite to the portion of the first main surface where the first impurity region is formed surrounds the regions for forming the fourth and fifth impurity regions of the second main surface, and it is a region of the first conductivity type or a region of the second conductivity type having impurity concentration not higher than that of the first impurity region.

Abstract: The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n? type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.

Abstract: The dense accumulation of hole carriers can be obtained over a wide range of a semiconductor region in a floating state formed within a body region of an IGBT. An n type semiconductor region (52) whose potential is floating is formed within a p? type body region (28). The n type semiconductor region (52) is isolated from an n+ type emitter region (32) and an n? type drift region (26) by the body region (28). Furthermore, a second electrode (62) is formed, so as to oppose to at least a part of the semiconductor region (52) via an insulator film (64). The second electrode (62) does not oppose to the emitter region (32).

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in the neutral region of the emitter layer. This quasi-drift field induces valence bandgap grading within the emitter layer so as to accelerate movement of holes from the base layer through the emitter layer. Accelerated movement of the holes from the base layer through the emitter layer reduces emitter delay time and thereby, increases the cut-off frequency (fT) and the maximum oscillation frequency (fMAX) of the resultant HBT.

Abstract: A semiconductor component and method of making a semiconductor component is disclosed. In one embodiment, the semiconductor component includes a drift region of a first conductivity type, a body region of a second conductivity type, and a trench extending into the body region. A semiconductor region of the first conductivity type is in contact with the drift region and the body region and is arranged at a distance from the trench.

Abstract: A semiconductor module includes: a semiconductor element (13) having a working unit (11) and a guard ring unit (12); and heat radiation members (15, 14) arranged on an upper surface and a lower surface of the semiconductor element for cooling the semiconductor element. A passivation film (20) covers the guard ring but does not cover the working unit. The upper heat radiation member (15) is made of a flat metal plate connected to the working unit without contact with the passivation film. The upper heat radiation member is connected to the lower heat radiation member (14) in the thermo-conducting way.

Abstract: A vertical power semiconductor component, e.g. a diode or an IGBT, in which there are formed, on the rear side of a substrate, a rear side emitter or a cathode emitter and, over that, a rear side metal layer that at least partly covers the latter, is defined by the fact that, in the edge region of the component, provision is made of injection attenuation means for reducing the charge carrier injection from the rear side emitter or the cathode emitter into said edge section.

Abstract: The invention relates to a trench MOSPET with drain (8), sub-channel region (10) body (12) and source (14). The sub-channel region is doped to be the same conductivity type as the body (12), but of lower doping density. A field plate electrode (34) is provided adjacent to the sub-channel region (10) 10 and a gate electrode (32) next to the body (12).

Abstract: A power IGBT includes a semiconductor body having an emitter zone of a first conduction type and a drift zone of a second conduction type proximate to the emitter zone. The IGBT further includes a cell array, each transistor cell of the array having a source zone, a body zone disposed between the source zone and the drift zone, the body zone and source zone short-circuited, and a gate electrode configured to be insulated with respect to the source zone and the body zone. The cell array has a first cell array section with a first cell density and a second cell array section with a second cell density that is lower than the first cell density. The emitter zone has a lower emitter efficiency in a region corresponding to the second cell array section than in a region corresponding to the first cell array section.

Abstract: An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the inside device region and divided in segments by insulated trench-shaped gates to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, an inner region defined in and insulated from the dummy base region, and a connection part to electrically connect the inner region to the emitter electrode.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried regions 44a of the second conductivity type are provided on the bottom surface of the base diffusion regions 17a. A distance between adjacent base buried regions 44a at the bottom of the same base diffusion region 17a is Wm1, a distance between adjacent base buried regions 44a at the bottom of the different base diffusion regions 17a is Wm2, and a distance between the guard buried regions 44b is WPE. A ratio of an impurity quantity Q1 of the first conductivity type and an impurity quantity Q2 of the second conductivity type included inside the widthwise center of the innermost guard buried region 44b is 0.90<Q2/Q1 when Wm1<WPE<Wm2.

Abstract: A method for manufacturing a semiconductor device includes steps of injecting a hole current into an N drift region while a constant voltage is applied to a P+ anode of a lateral insulated gate bipolar transistor, such that a majority of the hole current passes through a P+ cathode of the lateral insulated gate bipolar transistor via a P+ buried layer. Therefore, a hole-current path located under an N+ cathode area of a LIGBT structure is eliminated, thus securing sufficient latch-up current density.